trigger read ALU ready/valid from latch as well

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index cf3cf0ba5919ca37d1af93bd4185db8cd3b731ac..baa18031471107c871ed292a4384426e1e78c80e 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -286,9 +286,10 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # on a go_read, tell the ALU we're accepting data.
         # NOTE: this spells TROUBLE if the ALU isn't ready!
         # go_read is only valid for one clock!
-        with m.If(all_rd):                           # src operands ready, GO!
-            with m.If(~self.alu.p.ready_o):          # no ACK yet
-                m.d.comb += self.alu.p.valid_i.eq(1) # so indicate valid
+        m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
+        m.d.comb += self.alu.p.valid_i.eq(alui_l.q)
+        m.d.comb += alui_l.r.eq(self.alu.p.ready_o) # valid for one extra
+        m.d.comb += alui_l.s.eq(all_rd_pulse)
 
         # ALU output "ready" side.  alu "ready" indication stays hi until
         # ALU says "valid".

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 1be45181c9ee0ef25d55750cfc5a14fb8b2e6582..c765af1d3d2ffa7bac0ffb490695656fcb6ea5db 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -44,7 +44,7 @@ def get_cu_output(cu, idx):
         yield
     yield cu.wr.go[idx].eq(1)
     yield
-    result = yield cu.dst_i[idx]
+    result = yield cu.dest[idx]
     yield cu.wr.go[idx].eq(0)
     return result