argh add yet another latch to detect when LD/ST has completed

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 4cce7c2cc04b08388130845c9d478e81520d556b..233daf5a7b78deb1be8cfc792b5c4280547e6bc6 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -255,6 +255,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
+        m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
 
         ####################
         # signals
@@ -349,6 +350,10 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += sto_l.s.eq(addr_ok & op_is_st)
         comb += sto_l.r.eq(reset_s | p_st_go)
 
+        # ld/st done
+        comb += lsd_l.s.eq(issue_i)
+        sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
+
         # reset latch
         comb += rst_l.s.eq(addr_ok)  # start when address is ready
         comb += rst_l.r.eq(issue_i)
@@ -471,7 +476,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += pi.data_len.eq(self.oper_i.data_len)  # data_len
         # address
         comb += pi.addr.data.eq(addr_r)           # EA from adder
-        comb += pi.addr.ok.eq(alu_ok & (lod_l.q | sto_l.q)
+        comb += pi.addr.ok.eq(alu_ok & (lod_l.q | sto_l.q) & lsd_l.q
                               )  # "do address stuff"
         comb += self.addr_exc_o.eq(pi.addr_exc_o)  # exception occurred
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 085f478802222c88ea87018448c2d6979b0fb400..c6c39b07cb17d5b82ede3652ad1035203ad27e1c 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -90,7 +90,7 @@ def get_cu_outputs(cu, code):
             yield
     else: # LDST CompUnit
         # not a lot can be done about this - simply wait a few cycles
-        for i in range(10):
+        for i in range(5):
             yield
 
     wrmask = yield cu.wrmask
@@ -289,7 +289,6 @@ class TestRunner(FHDLTestCase):
             yield cu.rdmaskn.eq(0)
             yield
 
-
             # debugging issue with branch
             if self.funit == Function.BRANCH:
                 lr = yield cu.alu.pipe1.n.data_o.lr.data