Fix incorrect signal widths

dbg_data is the width of a write lane (granularity) and dbg_wrote is a
single bit.

diff --git a/src/soc/regfile/sram_wrapper.py b/src/soc/regfile/sram_wrapper.py
index 5ce85b826b02553f5c019531dfa3994ebbfbae27..024563e6ad434624f1c827155b85890000a02319 100644 (file)
--- a/src/soc/regfile/sram_wrapper.py
+++ b/src/soc/regfile/sram_wrapper.py
@@ -258,8 +258,9 @@ class PhasedDualPortRegfile(Elaboratable):
         # debug signals, only used in formal proofs
         self.dbg_addr = Signal(addr_width); """debug: address under test"""
         self.dbg_we_mask = Signal(we_width); """debug: write lane under test"""
-        self.dbg_data = Signal(data_width); """debug: data to keep in sync"""
-        self.dbg_wrote = Signal(addr_width); """debug: data is valid"""
+        gran = self.data_width // self.we_width
+        self.dbg_data = Signal(gran); """debug: data to keep in sync"""
+        self.dbg_wrote = Signal(); """debug: data is valid"""
 
     def elaborate(self, platform):
         m = Module()