radeonsi: rename init_config states to cs_preamble states

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index acd86730d0bd84121a3770f9fcd5132131ffc7dc..f596d51e0f6b805a8ae9006504fde4ba903ee155 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -411,12 +411,12 @@ static void si_log_chunk_type_cs_print(void *data, FILE *f)
 
    if (chunk->gfx_end != chunk->gfx_begin) {
       if (chunk->gfx_begin == 0) {
-         if (ctx->init_config)
-            ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw, NULL, 0,
+         if (ctx->cs_preamble_state)
+            ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0,
                         "IB2: Init config", ctx->chip_class, NULL, NULL);
 
-         if (ctx->init_config_gs_rings)
-            ac_parse_ib(f, ctx->init_config_gs_rings->pm4, ctx->init_config_gs_rings->ndw, NULL, 0,
+         if (ctx->cs_preamble_gs_rings)
+            ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0,
                         "IB2: Init GS rings", ctx->chip_class, NULL, NULL);
       }
 

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index ed7b8c12b269cd757f90c9632f21a37b96b54349..2e7b34e3a092d9fa536679ffe5928c2136a599e3 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -421,9 +421,9 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
    si_pm4_reset_emitted(ctx);
 
    /* The CS initialization should be emitted before everything else. */
-   si_pm4_emit(ctx, ctx->init_config);
-   if (ctx->init_config_gs_rings)
-      si_pm4_emit(ctx, ctx->init_config_gs_rings);
+   si_pm4_emit(ctx, ctx->cs_preamble_state);
+   if (ctx->cs_preamble_gs_rings)
+      si_pm4_emit(ctx, ctx->cs_preamble_gs_rings);
 
    if (ctx->queued.named.ls)
       ctx->prefetch_L2_mask |= SI_PREFETCH_LS;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 088ede2eb2f04a58f5134fb0dc20cf7229fdf710..99fa2b40c7a8bbce47b8886f01bb27db60839b4c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -194,9 +194,9 @@ static void si_destroy_context(struct pipe_context *context)
    si_resource_reference(&sctx->wait_mem_scratch, NULL);
    si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
 
-   si_pm4_free_state(sctx, sctx->init_config, ~0);
-   if (sctx->init_config_gs_rings)
-      si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
+   si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
+   if (sctx->cs_preamble_gs_rings)
+      si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
    for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
       si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
 
@@ -550,6 +550,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
       si_init_msaa_functions(sctx);
       si_init_shader_functions(sctx);
       si_init_state_functions(sctx);
+      si_init_cs_preamble_state(sctx);
       si_init_streamout_functions(sctx);
       si_init_viewport_functions(sctx);
 

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 1bf3441802781d8b8a94e0bbbe54779918f1af36..f56762a982096742eff036b521bc565f1111c2bf 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1011,9 +1011,9 @@ struct si_context {
    struct pipe_scissor_state window_rectangles[4];
 
    /* Precomputed states. */
-   struct si_pm4_state *init_config;
-   struct si_pm4_state *init_config_gs_rings;
-   bool init_config_has_vgt_flush;
+   struct si_pm4_state *cs_preamble_state;
+   struct si_pm4_state *cs_preamble_gs_rings;
+   bool cs_preamble_has_vgt_flush;
    struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
 
    /* shaders */

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 95775b4207d348b8a32f196c7dea8b7d8087e67b..2a0aa64056acbbce29d860273f345317c0f890de 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3248,7 +3248,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
    }
 
    /* Framebuffer dimensions. */
-   /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
+   /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_cs_preamble_state */
    radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
                           S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
 
@@ -4980,8 +4980,6 @@ static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
    return si_create_blend_state_mode(&sctx->b, &blend, mode);
 }
 
-static void si_init_config(struct si_context *sctx);
-
 void si_init_state_compute_functions(struct si_context *sctx)
 {
    sctx->b.create_sampler_state = si_create_sampler_state;
@@ -5042,8 +5040,6 @@ void si_init_state_functions(struct si_context *sctx)
    sctx->b.set_tess_state = si_set_tess_state;
 
    sctx->b.set_active_query_state = si_set_active_query_state;
-
-   si_init_config(sctx);
 }
 
 void si_init_screen_state_functions(struct si_screen *sscreen)
@@ -5112,7 +5108,7 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p
    }
 }
 
-static void si_init_config(struct si_context *sctx)
+void si_init_cs_preamble_state(struct si_context *sctx)
 {
    struct si_screen *sscreen = sctx->screen;
    uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
@@ -5358,5 +5354,5 @@ static void si_init_config(struct si_context *sctx)
       si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
    }
 
-   sctx->init_config = pm4;
+   sctx->cs_preamble_state = pm4;
 }

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index f7e78d2187bb9f8a2741901fda8deaf4cffd04d1..7e1c81d1dadb2389e8e24fb67e716cf356fa7c6a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -527,6 +527,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
 void si_init_state_compute_functions(struct si_context *sctx);
 void si_init_state_functions(struct si_context *sctx);
 void si_init_screen_state_functions(struct si_screen *sscreen);
+void si_init_cs_preamble_state(struct si_context *sctx);
 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
                                enum pipe_format format, unsigned offset, unsigned size,
                                uint32_t *state);

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index de5ca569473a4d572368113555c60e2746711e8e..396737bd2c22dd7d3a16cff2982b906eb2855970 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3295,21 +3295,21 @@ static void si_emit_spi_map(struct si_context *sctx)
 /**
  * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
  */
-static void si_init_config_add_vgt_flush(struct si_context *sctx)
+static void si_cs_preamble_add_vgt_flush(struct si_context *sctx)
 {
-   if (sctx->init_config_has_vgt_flush)
+   if (sctx->cs_preamble_has_vgt_flush)
       return;
 
    /* Done by Vulkan before VGT_FLUSH. */
-   si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
-   si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
-   si_pm4_cmd_end(sctx->init_config, false);
+   si_pm4_cmd_begin(sctx->cs_preamble_state, PKT3_EVENT_WRITE);
+   si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+   si_pm4_cmd_end(sctx->cs_preamble_state, false);
 
    /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
-   si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
-   si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
-   si_pm4_cmd_end(sctx->init_config, false);
-   sctx->init_config_has_vgt_flush = true;
+   si_pm4_cmd_begin(sctx->cs_preamble_state, PKT3_EVENT_WRITE);
+   si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
+   si_pm4_cmd_end(sctx->cs_preamble_state, false);
+   sctx->cs_preamble_has_vgt_flush = true;
 }
 
 /* Initialize state related to ESGS / GSVS ring buffers */
@@ -3378,7 +3378,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
          return false;
    }
 
-   /* Create the "init_config_gs_rings" state. */
+   /* Create the "cs_preamble_gs_rings" state. */
    pm4 = CALLOC_STRUCT(si_pm4_state);
    if (!pm4)
       return false;
@@ -3398,15 +3398,15 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
    }
 
    /* Set the state. */
-   if (sctx->init_config_gs_rings)
-      si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
-   sctx->init_config_gs_rings = pm4;
+   if (sctx->cs_preamble_gs_rings)
+      si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
+   sctx->cs_preamble_gs_rings = pm4;
 
-   if (!sctx->init_config_has_vgt_flush) {
-      si_init_config_add_vgt_flush(sctx);
+   if (!sctx->cs_preamble_has_vgt_flush) {
+      si_cs_preamble_add_vgt_flush(sctx);
    }
 
-   /* Flush the context to re-emit both init_config states. */
+   /* Flush the context to re-emit both cs_preamble states. */
    sctx->initial_gfx_cs_size = 0; /* force flush */
    si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 
@@ -3638,9 +3638,9 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
    if (!sctx->tess_rings)
       return;
 
-   si_init_config_add_vgt_flush(sctx);
+   si_cs_preamble_add_vgt_flush(sctx);
 
-   si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings), RADEON_USAGE_READWRITE,
+   si_pm4_add_bo(sctx->cs_preamble_state, si_resource(sctx->tess_rings), RADEON_USAGE_READWRITE,
                  RADEON_PRIO_SHADER_RINGS);
 
    uint64_t factor_va =
@@ -3648,26 +3648,26 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 
    /* Append these registers to the init config state. */
    if (sctx->chip_class >= GFX7) {
-      si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
+      si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE,
                      S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
-      si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
+      si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
       if (sctx->chip_class >= GFX10)
-         si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
+         si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
                         S_030984_BASE_HI(factor_va >> 40));
       else if (sctx->chip_class == GFX9)
-         si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
+         si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI,
                         S_030944_BASE_HI(factor_va >> 40));
-      si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
+      si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM,
                      sctx->screen->vgt_hs_offchip_param);
    } else {
-      si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
+      si_pm4_set_reg(sctx->cs_preamble_state, R_008988_VGT_TF_RING_SIZE,
                      S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
-      si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
-      si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+      si_pm4_set_reg(sctx->cs_preamble_state, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
+      si_pm4_set_reg(sctx->cs_preamble_state, R_0089B0_VGT_HS_OFFCHIP_PARAM,
                      sctx->screen->vgt_hs_offchip_param);
    }
 
-   /* Flush the context to re-emit the init_config state.
+   /* Flush the context to re-emit the cs_preamble state.
     * This is done only once in a lifetime of a context.
     */
    sctx->initial_gfx_cs_size = 0; /* force flush */