pi_ld busy waiting fix

diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py
index eea6532664689c0321390371ddc0a9f6a1571c1d..c8a4b39ad4d6122e37a7ae4d1954df1ec27ea41a 100644 (file)
--- a/src/soc/config/test/test_pi2ls.py
+++ b/src/soc/config/test/test_pi2ls.py
@@ -99,7 +99,7 @@ def pi_ld(port1, addr, datalen, msr_pr=0):
     if exc_happened:
         return 0
 
-    yield from wait_busy(port1, no=False)    # wait while not busy
+    yield from wait_busy(port1, no=True)    # wait while busy
 
     return data
 

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index cf34705920a750c2f0c095f61a42f81fb0938dab..3c4013d10fa3ba3ab27a880705c04c310d9effdb 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -7,7 +7,7 @@ from random import randint, seed
 from nmigen.sim import Simulator, Delay, Settle
 from nmutil.util import wrap
 
-from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
+from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, wait_busy
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.loadstore import ConfigMemoryPortInterface
 
@@ -137,8 +137,22 @@ def _test_loadstore1(dut, mem):
     assert(happened==1)
     assert(alignment==1)
     assert(dar==addr)
+    yield from wait_busy(pi, no=True)    # wait while busy
+    # wait is only needed in case of in exception here
     print("=== alignment error test passed ===")
 
+    """
+    #next test
+    addr = 0xFF100e000
+    ld_data = yield from pi_ld_debug(pi, addr, 8, msr_pr=1)
+    alignment = yield pi.exc_o.alignment
+    happened = yield pi.exc_o.happened
+    dar = yield pi.dar_o
+    assert(happened==1)
+    assert(alignment==1)
+    assert(dar==addr)
+    """
+
     yield
     stop = True