%.log:
$(GDBSERVER_PY) \
--isolate \
- --$(subst .log,,$@) \
+ targets/RISC-V/$(subst .log,.py,$@) \
--sim_cmd $(RISCV)/bin/$(RISCV_SIM) \
--server_cmd $(RISCV)/bin/openocd \
| tee $@ 2>&1 || (sed s/^/$@:\ / $@ && false)
64-bit Spike
------------
-`./gdbserver.py --spike64 --cmd $RISCV/bin/spike`
+`./gdbserver.py targets/RISC-V/spike64.py`
32-bit Spike
------------
-`./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
+`./gdbserver.py targets/RISC-V/spike32.py`
-32-bit SiFive Core on Supported FPGA Boards & Hardware
--------------------------------------
+32-bit SiFive Core on Supported FPGA Boards & Hardware
+------------------------------------------------------
-`./gdbserver.py --freedom-e300`
-`./gdbserver.py --hifive1`
+`./gdbserver.py targets/SiFive/E300.py`
+`./gdbserver.py targets/SiFive/HiFive1.py`
+Custom Target
+-------------
-32-bit rocket-chip core in Simulation
--------------------------------------
+For custom targets, you can create a .py file anywhere and pass its path on the
+command line. The Targets class in `targets.py` contains documentation on what
+every variable means.
-`./gdbserver.py --freedom-e300-sim`
+
+Log Files
+=========
+
+All output from tests ends up in the `logs/` subdirectory, with one log file
+per test. If a test fails, this is where to look.
Debug Tips
==========
-You can run just a single test by specifying <class>.<function> on the command
-line, eg: `./gdbserver.py --spike64 --cmd $RISCV/bin/spike
-SimpleRegisterTest.test_s0`.
-Once that test has failed, you can look at gdb.log and (in this case) spike.log
-to get an idea of what might have gone wrong.
+You can run just a single test by specifying any part of its name on the
+command line, eg: `./gdbserver.py targets/RISC-V/spike64.py S0` runs
+SimpleS0Test. Once that test has failed, you can look at the log file to get
+an idea of what might have gone wrong.
+
+You can see what spike is doing by adding `-l` to the spike command, eg.:
+`./gdbserver.py --sim_cmd "$RISCV/bin/spike -l" targets/RISC-V/spike32.py Breakpoint`
-You can see what spike is doing by add `-l` to the spike command, eg.:
-`./gdbserver.py --spike32 --cmd "$RISCV/bin/spike -l"
-DebugTest.test_breakpoint`. (Then look at spike.log.)
+You can see what OpenOCD is doing by adding `-d` to the OpenOCD command, eg.:
+`./gdbserver.py --server_cmd "openocd -d" targets/RISC-V/spike32.py Breakpoint`
-You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py --spike64
---gdb "valgrind riscv64-unknown-elf-gdb" -- -v DownloadTest`.
+You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py
+--gdb "valgrind riscv64-unknown-elf-gdb" targets/RISC-V/spike64.py
+DownloadTest`
# TODO: remove global
global parsed # pylint: disable=global-statement
parsed = parser.parse_args()
+ target = targets.target(parsed)
- target = parsed.target(parsed.server_cmd, parsed.sim_cmd, parsed.isolate)
if parsed.xlen:
target.xlen = parsed.xlen
+import importlib
import os.path
+import sys
import tempfile
import testlib
class Target(object):
- name = "name"
+ # pylint: disable=too-many-instance-attributes
+
+ # Name of the target. Defaults to the name of the class.
+ name = None
+
+ # XLEN of the target. May be overridden with --32 or --64 command line
+ # options.
xlen = 0
- directory = None
+
+ # GDB remotetimeout setting.
timeout_sec = 2
- temporary_files = []
- temporary_binary = None
- openocd_config = []
- use_fpu = False
+
+ # Path to OpenOCD configuration file relative to the .py file where the
+ # target is defined. Defaults to <name>.cfg.
+ openocd_config_path = None
+
+ # Path to linker script relative to the .py file where the target is
+ # defined. Defaults to <name>.lds.
+ link_script_path = None
+
+ # Will be autodetected (by running ExamineTarget) if left unset. Set to
+ # save a little time.
misa = None
- def __init__(self, server_cmd, sim_cmd, isolate):
- self.server_cmd = server_cmd
- self.sim_cmd = sim_cmd
- self.isolate = isolate
+ # Internal variables:
+ directory = None
+ temporary_files = []
+ temporary_binary = None
- def target(self):
- """Start the target, eg. a simulator."""
+ def __init__(self, path, parsed):
+ # Path to module.
+ self.path = path
+ self.directory = os.path.dirname(path)
+ self.server_cmd = parsed.server_cmd
+ self.sim_cmd = parsed.sim_cmd
+ self.isolate = parsed.isolate
+ if not self.name:
+ self.name = type(self).__name__
+ # Default OpenOCD config file to <name>.cfg
+ if not self.openocd_config_path:
+ self.openocd_config_path = "%s.cfg" % self.name
+ self.openocd_config_path = os.path.join(self.directory,
+ self.openocd_config_path)
+ # Default link script to <name>.lds
+ if not self.link_script_path:
+ self.link_script_path = "%s.lds" % self.name
+ self.link_script_path = os.path.join(self.directory,
+ self.link_script_path)
+
+ def create(self):
+ """Create the target out of thin air, eg. start a simulator."""
pass
def server(self):
"""Start the debug server that gdb connects to, eg. OpenOCD."""
- if self.openocd_config:
- return testlib.Openocd(server_cmd=self.server_cmd,
- config=self.openocd_config)
- else:
- raise NotImplementedError
+ return testlib.Openocd(server_cmd=self.server_cmd,
+ config=self.openocd_config_path)
def compile(self, *sources):
binary_name = "%s_%s-%d" % (
binary_name = self.temporary_binary.name
Target.temporary_files.append(self.temporary_binary)
march = "rv%dima" % self.xlen
- if self.use_fpu:
- march += "fd"
- if self.extensionSupported("c"):
- march += "c"
+ for letter in "fdc":
+ if self.extensionSupported(letter):
+ march += letter
testlib.compile(sources +
("programs/entry.S", "programs/init.c",
"-I", "../env",
"-march=%s" % march,
- "-T", "targets/%s/link.lds" % (self.directory or self.name),
+ "-T", self.link_script_path,
"-nostartfiles",
"-mcmodel=medany",
"-DXLEN=%d" % self.xlen,
else:
return False
-class SpikeTarget(Target):
- # pylint: disable=abstract-method
- instruction_hardware_breakpoint_count = 4
- reset_vector = 0x1000
-
-class Spike64Target(SpikeTarget):
- name = "spike64"
- directory = name
- xlen = 64
- use_fpu = True
- # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000...
- # boundary, but spike doesn't support that in the code where it generates
- # the reset vector.
- ram = 0x1212340000
- ram_size = 0x10000000
- openocd_config = "targets/%s/openocd.cfg" % directory
-
- def target(self):
- return testlib.Spike(self)
-
-class Spike32Target(SpikeTarget):
- name = "spike32"
- directory = name
- xlen = 32
- ram = 0x10000000
- ram_size = 0x10000000
- openocd_config = "targets/%s/openocd.cfg" % directory
-
- def target(self):
- return testlib.Spike(self)
-
-class FreedomE300Target(Target):
- name = "freedom-e300"
- xlen = 32
- ram = 0x80000000
- ram_size = 16 * 1024
- instruction_hardware_breakpoint_count = 2
- openocd_config = "targets/%s/openocd.cfg" % name
-
-class HiFive1Target(FreedomE300Target):
- name = "HiFive1"
- openocd_config = "targets/%s/openocd.cfg" % name
-
-class FreedomE300SimTarget(Target):
- name = "freedom-e300-sim"
- xlen = 32
- timeout_sec = 6000
- ram = 0x80000000
- ram_size = 256 * 1024 * 1024
- instruction_hardware_breakpoint_count = 2
- openocd_config = "targets/%s/openocd.cfg" % name
-
- def target(self):
- return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
-
-class FreedomU500Target(Target):
- name = "freedom-u500"
- xlen = 64
- ram = 0x80000000
- ram_size = 16 * 1024
- instruction_hardware_breakpoint_count = 2
- openocd_config = "targets/%s/openocd.cfg" % name
-
-class FreedomU500SimTarget(Target):
- name = "freedom-u500-sim"
- xlen = 64
- timeout_sec = 6000
- ram = 0x80000000
- ram_size = 256 * 1024 * 1024
- instruction_hardware_breakpoint_count = 2
- openocd_config = "targets/%s/openocd.cfg" % name
-
- def target(self):
- return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
-
-targets = [
- Spike32Target,
- Spike64Target,
- FreedomE300Target,
- FreedomU500Target,
- FreedomE300SimTarget,
- FreedomU500SimTarget,
- HiFive1Target]
-
def add_target_options(parser):
- group = parser.add_mutually_exclusive_group(required=True)
- for t in targets:
- group.add_argument("--%s" % t.name, action="store_const", const=t,
- dest="target")
+ parser.add_argument("target", help=".py file that contains definition for "
+ "the target to test with.")
parser.add_argument("--sim_cmd",
help="The command to use to start the actual target (e.g. "
- "simulation)")
+ "simulation)", default="spike")
parser.add_argument("--server_cmd",
help="The command to use to start the debug server (e.g. OpenOCD)")
help="Try to run in such a way that multiple instances can run at "
"the same time. This may make it harder to debug a failure if it "
"does occur.")
+
+def target(parsed):
+ directory = os.path.dirname(parsed.target)
+ filename = os.path.basename(parsed.target)
+ module_name = os.path.splitext(filename)[0]
+
+ sys.path.append(directory)
+ module = importlib.import_module(module_name)
+ found = []
+ for name in dir(module):
+ definition = getattr(module, name)
+ if type(definition) == type and issubclass(definition, Target):
+ found.append(definition)
+ assert len(found) == 1, "%s does not define exactly one subclass of " \
+ "targets.Target" % parsed.target
+
+ return found[0](parsed.target, parsed)
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x80000000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020
-
-# ...
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
-#-rtos riscv
-
-flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset
-halt
-flash protect 0 64 last off
-
-echo "Ready for Remote Connections"
--- /dev/null
+adapter_khz 10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+
+init
+reset halt
+
+echo "Ready for Remote Connections"
--- /dev/null
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+ /* Leave some space for pk's data structures, which includes tohost/fromhost
+ * which are special addresses we ought to leave alone. */
+ . = 0x10010000;
+ .text :
+ {
+ *(.text.entry)
+ *(.text)
+ }
+
+ /* data segment */
+ .data : { *(.data) }
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ }
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ .bss : { *(.bss) }
+
+ __malloc_start = .;
+ . = . + 512;
+
+ /* End of uninitalized data segement */
+ _end = .;
+}
--- /dev/null
+import targets
+import testlib
+
+class spike32(targets.Target):
+ xlen = 32
+ ram = 0x10000000
+ ram_size = 0x10000000
+ instruction_hardware_breakpoint_count = 4
+ reset_vector = 0x1000
+
+ def create(self):
+ return testlib.Spike(self)
--- /dev/null
+adapter_khz 10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+
+init
+reset halt
+
+echo "Ready for Remote Connections"
--- /dev/null
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+ . = 0x1212340000;
+ .text :
+ {
+ *(.text.entry)
+ *(.text)
+ }
+
+ /* data segment */
+ .data : { *(.data) }
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ }
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ .bss : { *(.bss) }
+
+ __malloc_start = .;
+ . = . + 512;
+
+ /* End of uninitalized data segement */
+ _end = .;
+}
--- /dev/null
+import targets
+import testlib
+
+class spike64(targets.Target):
+ xlen = 64
+ ram = 0x1212340000
+ ram_size = 0x10000000
+ instruction_hardware_breakpoint_count = 4
+ reset_vector = 0x1000
+
+ def create(self):
+ return testlib.Spike(self)
--- /dev/null
+import targets
+
+class E300(targets.Target):
+ xlen = 32
+ ram = 0x80000000
+ ram_size = 16 * 1024
+ instruction_hardware_breakpoint_count = 2
+ openocd_config_path = "Freedom.cfg"
+ link_script_path = "Freedom.lds"
--- /dev/null
+import targets
+
+class E300Sim(targets.Target):
+ xlen = 32
+ timeout_sec = 6000
+ ram = 0x80000000
+ ram_size = 256 * 1024 * 1024
+ instruction_hardware_breakpoint_count = 2
+ openocd_config_path = "Freedom.cfg"
+ link_script_path = "Freedom.lds"
+
+ def target(self):
+ return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
--- /dev/null
+adapter_khz 10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+
+init
+
+halt
+echo "Ready for Remote Connections"
--- /dev/null
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+ . = 0x80000000;
+ .text :
+ {
+ *(.text.entry)
+ *(.text)
+ }
+
+ /* data segment */
+ .data : { *(.data) }
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ }
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ .bss : { *(.bss) }
+
+ __malloc_start = .;
+ . = . + 512;
+
+ /* End of uninitalized data segement */
+ _end = .;
+}
--- /dev/null
+import targets
+
+class U500(targets.Target):
+ xlen = 64
+ ram = 0x80000000
+ ram_size = 16 * 1024
+ instruction_hardware_breakpoint_count = 2
+ openocd_config_path = "Freedom.cfg"
+ link_script_path = "Freedom.lds"
--- /dev/null
+class U500Sim(Target):
+ xlen = 64
+ timeout_sec = 6000
+ ram = 0x80000000
+ ram_size = 256 * 1024 * 1024
+ instruction_hardware_breakpoint_count = 2
+ openocd_config_path = "Freedom.cfg"
+ link_script_path = "Freedom.lds"
+
+ def target(self):
+ return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
--- /dev/null
+adapter_khz 10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+# ...
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+#-rtos riscv
+
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset
+halt
+flash protect 0 64 last off
+
+echo "Ready for Remote Connections"
--- /dev/null
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+ . = 0x80000000;
+ .text :
+ {
+ *(.text.entry)
+ *(.text)
+ }
+
+ /* data segment */
+ .data : { *(.data) }
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+ *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ }
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ .bss : { *(.bss) }
+
+ __malloc_start = .;
+ . = . + 512;
+
+ /* End of uninitalized data segement */
+ _end = .;
+}
--- /dev/null
+import targets
+
+class HiFive1(targets.Target):
+ xlen = 32
+ ram = 0x80000000
+ ram_size = 16 * 1024
+ instruction_hardware_breakpoint_count = 2
+ misa = 0x40001105
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x80000000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-#jtag_vpi_set_port 34448
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-init
-halt
-echo "Ready for Remote Connections"
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x80000000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-gdb_report_data_abort enable
-
-init
-
-halt
-echo "Ready for Remote Connections"
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x80000000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-init
-
-halt
-echo "Ready for Remote Connections"
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x80000000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-
-init
-
-halt
-echo "Ready for Remote Connections"
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- /* Leave some space for pk's data structures, which includes tohost/fromhost
- * which are special addresses we ought to leave alone. */
- . = 0x10010000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-gdb_report_data_abort enable
-
-init
-reset halt
-
-echo "Ready for Remote Connections"
+++ /dev/null
-OUTPUT_ARCH( "riscv" )
-
-SECTIONS
-{
- . = 0x1212340000;
- .text :
- {
- *(.text.entry)
- *(.text)
- }
-
- /* data segment */
- .data : { *(.data) }
-
- .sdata : {
- __global_pointer$ = . + 0x800;
- *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
- *(.srodata*)
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- }
-
- /* bss segment */
- .sbss : {
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.scommon)
- }
- .bss : { *(.bss) }
-
- __malloc_start = .;
- . = . + 512;
-
- /* End of uninitalized data segement */
- _end = .;
-}
+++ /dev/null
-adapter_khz 10000
-
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-gdb_report_data_abort enable
-
-init
-reset halt
-
-echo "Ready for Remote Connections"
try:
self.process.kill()
self.process.wait()
- except OSError:
+ except (OSError, AttributeError):
pass
class OpenocdCli(object):
todo = []
if parsed.misaval:
target.misa = int(parsed.misaval, 16)
- print "Assuming $MISA value of 0x%x. Skipping ExamineTarget." % \
- target.misa
+ print "Using $misa from command line: 0x%x" % target.misa
+ elif target.misa:
+ print "Using $misa from target definition: 0x%x" % target.misa
else:
todo.append(("ExamineTarget", ExamineTarget))
def classSetup(self):
self.compile()
- self.target_process = self.target.target()
+ self.target_process = self.target.create()
self.server = self.target.server()
self.logs.append(self.server.logname)
projects / riscv-tests.git / commitdiff