Add ilang output to test_maskgen.py

diff --git a/src/soc/shift_rot/test/test_maskgen.py b/src/soc/shift_rot/test/test_maskgen.py
index f9d28d70ec911f7129e69b093098ad43d376f696..1a4d34e676154b250f95ef120932a9b88fcaf937 100644 (file)
--- a/src/soc/shift_rot/test/test_maskgen.py
+++ b/src/soc/shift_rot/test/test_maskgen.py
@@ -1,6 +1,7 @@
 from nmigen import Signal, Module
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
+from nmigen.cli import rtlil
 from soc.alu.maskgen import MaskGen
 from soc.decoder.helpers import MASK
 import random
@@ -37,5 +38,11 @@ class MaskGenTestCase(FHDLTestCase):
         with sim.write_vcd("maskgen.vcd", "maskgen.gtkw", traces=dut.ports()):
             sim.run()
 
+    def test_ilang(self):
+        dut = MaskGen(64)
+        vl = rtlil.convert(dut, ports=dut.ports())
+        with open("maskgen.il", "w") as f:
+            f.write(vl)
+
 if __name__ == '__main__':
     unittest.main()