add dummy clock register for now

diff --git a/src/peripherals/sdram/sdr_top.bsv b/src/peripherals/sdram/sdr_top.bsv
index d886fd56425f88f50dcaf3c2d85463486b5fb7c4..781dd76af92a288095d043fc910cd41d51c8e71a 100644 (file)
--- a/src/peripherals/sdram/sdr_top.bsv
+++ b/src/peripherals/sdram/sdr_top.bsv
@@ -245,10 +245,8 @@ endfunction
 
 (*synthesize*)
     
-module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave);
+module mksdr_axi4_slave#(Clock clk0,  Reset rst0) (Ifc_sdr_slave);
     
-       Reset rst0 <- mkAsyncResetFromCR (0, clk0);
-
    Reg#(Bit#(9))        rg_delay_count <- mkReg(0,clocked_by clk0, reset_by rst0);
    Reg#(Bit#(9))        rg_rd_actual_len <- mkReg(0,clocked_by clk0, reset_by rst0);
    Reg#(bit)            rg_app_req <- mkDReg(0,clocked_by clk0, reset_by rst0);
@@ -341,6 +339,9 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave);
    AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor_cntrl_reg <- mkAXI4_Slave_Xactor;
    Ifc_sdram sdr_cntrl <- mksdrc_top(clocked_by clk0, reset_by rst0);
 
+   // TODO remove the following when clock to bit type conversion is done
+   Reg#(Bit#(1)) rg_dummy <- mkReg(0, clocked_by clk0,  reset_by rst0);
+
    function Action fn_wr_cntrl_reg(Bit#(64) data, Bit#(8) address);
        action
        case(address) 
@@ -828,7 +829,7 @@ module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave);
 
         interface osdr_clock = interface Get
           method ActionValue#(Bit#(1)) get;
-            return ?;
+            return rg_dummy;
           endmethod
         endinterface;
     endinterface