doh, bus-hack was the wrong way round. *output* the address with

3 extra LSBs at the front to fix the wishbone incompatibility

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d75b1f5e18bfab61cdd2f0893bb6219154d4ea2d..0ba9e8a0ce3920865e334c82e08152868f0a76fb 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -363,8 +363,8 @@ class TestIssuerBase(Elaboratable):
         if self.microwatt_compat:
             ibus = self.imem.ibus
             dbus = self.core.l0.cmpi.wb_bus()
-            comb += ibus.adr.eq(self.ibus_adr[3:])
-            comb += dbus.adr.eq(self.dbus_adr[3:])
+            comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+            comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
 
         cur_state = self.cur_state