--- /dev/null
+create verilog file "python issuer_verilog libresoc.v"
+copy to libresoc/ directory
+terminal 1: ./sim.py
+terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
--- /dev/null
+// Created using Xilinx iMPACT Software [ISE WebPACK - 5.1i]
+TRST OFF;
+ENDIR IDLE;
+ENDDR IDLE;
+STATE RESET IDLE;
+TIR 0 ;
+HIR 0 ;
+TDR 0 ;
+HDR 0 ;
+// Validating chain...
+TIR 0 ;
+HIR 0 ;
+TDR 0 ;
+HDR 0 ;
+SIR 4 TDI (f) SMASK (f) ;
+TIR 0 ;
+HIR 5 TDI (1f) SMASK (1f) ;
+// don't set header to 1 extra bit
+//HDR 1 TDI (00) SMASK (01) ;
+TDR 0 ;
+//Loading device with 'idcode' instruction.
+SIR 4 TDI (1) SMASK (f) ;
+SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
+//Loading device with 'conld' instruction.
+//SIR 8 TDI (f0) ;
+RUNTEST 110000 TCK;
+
--- /dev/null
+STATE RESET IDLE;
+TIR 0 ;
+HIR 5 TDI (1f) SMASK (1f) ;
+//HDR 1 TDI (00) SMASK (01) ;
+TDR 0 ;
+//Loading device with 'idcode' instruction.
+SIR 4 TDI (1) SMASK (1) ;
+//SDR 32 TDI (00000000) SMASK (ffffffff) TDO (00000c7f) SMASK (ffffffff) ;
+SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
+//
+// set to DMI "address"
+SIR 4 TDI (8) SMASK (f) ;
+// set DMI "ctrl" address (0)
+SDR 8 TDI (2) SMASK (ff) ;
+// set to DMI "data read"
+SIR 4 TDI (9) SMASK (f) ;
+// read 64 bit
+//SDR 32 TDI (00000000) SMASK (ffffffff) TDO (000018ff) MASK (ffffffff) ;
+//SDR 32 TDI (00000000) SMASK (00000000) TDO (00000000) MASK (ffffffff) ;
+SDR 64 TDI (0000000000000000) SMASK (0000000000000000) TDO (0000000000000000) MASK (ffffffffffffffff) ;
# this should be irlen=4
jtag newtap libresoc tap -irlen 4 -irmask 0xf -ircapture 0xf -expected-id 0x000018ff
-set _TARGETNAME libresoc.tap
-target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
+#set _TARGETNAME libresoc.tap
+#target create $_TARGETNAME.0 ppc64 -chain-position $_TARGETNAME -rtos hwthread
# Configure work area in on-chip SRAM
#$_TARGETNAME.0 configure -work-area-phys 0x80000000 \