def eq(self, rhs):
         """ Assign member signals. """
+        print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
             DivPipeBaseData.eq(self, rhs)
 
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
 
     def __init__(self, pspec):
-        DivPipeCoreSetupStage.__init__(self.get_core_config())
         self.pspec = pspec
+        DivPipeCoreSetupStage.__init__(self, pspec.core_config)
 
     def elaborate(self, platform):
         m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
 class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
 
     def __init__(self, pspec, stage_index):
-        DivPipeCoreCalculateStage.__init__(self.get_core_config(), stage_index)
         self.pspec = pspec
+        DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index)
 
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
 class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
 
     def __init__(self, pspec, stage_index):
-        DivPipeCoreFinalStage.__init__(self.get_core_config(), stage_index)
         self.pspec = pspec
+        DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index)
 
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
 
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
-from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInterstageData
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData,
+                                                 DivPipeSetupStage,
+                                                 DivPipeCalculateStage,
+                                                 DivPipeFinalStage,
+                                                )
 
 # TODO: write these
 from .div0 import FPDivStage0Mod