fix nmigen imports

diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py
index b865a01835669242c17be1dba094621cc69718fb..4c6c6ac98618febe8ea58191b2d4276e2662dfe1 100644 (file)
--- a/nmigen_soc/csr/bus.py
+++ b/nmigen_soc/csr/bus.py
@@ -1,5 +1,5 @@
 import enum
-from nmigen import *
+from nmigen import Record, Elaboratable, Module, Signal, Mux
 from nmigen.utils import log2_int
 
 from ..memory import MemoryMap

diff --git a/nmigen_soc/csr/wishbone.py b/nmigen_soc/csr/wishbone.py
index a1767fcc068bcce8cd2188ddee2f8c6a7717d369..54e3f490ba1ee4b1fe11f1b14c624aaa3af80d6b 100644 (file)
--- a/nmigen_soc/csr/wishbone.py
+++ b/nmigen_soc/csr/wishbone.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Cat
 from nmigen.utils import log2_int
 
 from . import Interface as CSRInterface

diff --git a/nmigen_soc/scheduler.py b/nmigen_soc/scheduler.py
index 9fffac58ebc392c097f461d9391dc8569c449ce9..29ab46266c22cc692437e0c681539d2efbb53dab 100644 (file)
--- a/nmigen_soc/scheduler.py
+++ b/nmigen_soc/scheduler.py
@@ -1,4 +1,4 @@
-from nmigen import *
+from nmigen import Signal, Elaboratable, Module
 
 
 __all__ = ["RoundRobin"]

diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py
index 3d530c17695ba37e92f2f8d5b4fa1fe6a6291fda..e53331839a316ec7648fa15e6406a2fded36caca 100644 (file)
--- a/nmigen_soc/test/test_csr_bus.py
+++ b/nmigen_soc/test/test_csr_bus.py
@@ -1,9 +1,9 @@
 # nmigen: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
+from nmigen import Record, Module
 from nmigen.hdl.rec import Layout
-from nmigen.back.pysim import *
+from nmigen.back.pysim import Simulator, Fragment
 
 from ..csr.bus import *
 

diff --git a/nmigen_soc/test/test_csr_wishbone.py b/nmigen_soc/test/test_csr_wishbone.py
index 7c41cf250183d1f9ac44782c4d56a733608dbab6..adfa590ed80ec2cbd966e9f4293a0afdb10ac261 100644 (file)
--- a/nmigen_soc/test/test_csr_wishbone.py
+++ b/nmigen_soc/test/test_csr_wishbone.py
@@ -1,8 +1,8 @@
 # nmigen: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.back.pysim import *
+from nmigen import Elaboratable, Signal, Module
+from nmigen.back.pysim import Simulator, Fragment
 
 from .. import csr
 from ..csr.wishbone import *

diff --git a/nmigen_soc/test/test_wishbone_bus.py b/nmigen_soc/test/test_wishbone_bus.py
index d93ea9d54ae6757dd3cd393df4eebaf80b9e5dd7..1e63155750d8e504c102a5a47a85b2890f8f1598 100644 (file)
--- a/nmigen_soc/test/test_wishbone_bus.py
+++ b/nmigen_soc/test/test_wishbone_bus.py
@@ -1,9 +1,9 @@
 # nmigen: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.hdl.rec import *
-from nmigen.back.pysim import *
+from nmigen import Module, Record, Elaboratable
+from nmigen.hdl.rec import Layout, DIR_FANOUT, DIR_FANIN
+from nmigen.back.pysim import Simulator, Delay, Tick
 
 from ..wishbone import *
 

diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py
index 580af84f6757f11886c7ee19fd2621cf5c48b16d..37ce285b686dbd0915903c98d7a5d247197548b7 100644 (file)
--- a/nmigen_soc/wishbone/bus.py
+++ b/nmigen_soc/wishbone/bus.py
@@ -1,5 +1,5 @@
 from enum import Enum
-from nmigen import *
+from nmigen import Record, Elaboratable, Module, Signal, Cat, Repl
 from nmigen.hdl.rec import Direction
 from nmigen.utils import log2_int
 

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index ac5f12b32837f30900471ee01b227248d56f74c8..f6734b2ef40c6407867d44df2caa8991619e1b05 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.utils import *
+from nmigen import Elaboratable, Memory, Module
+from nmigen.utils import log2_int
 
 from .bus import Interface