add simple GPIO wishbone bus to litex sim.py

diff --git a/src/soc/bus/simple_gpio.py b/src/soc/bus/simple_gpio.py
index 84467d4c43a094acd6eb6536d16f651370b7a452..86afebe3113d914ed60166d202816482632bb210 100644 (file)
--- a/src/soc/bus/simple_gpio.py
+++ b/src/soc/bus/simple_gpio.py
@@ -27,7 +27,7 @@ class SimpleGPIO(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec), name="icp_wb")
+        self.bus = Record(make_wb_layout(spec), name="gpio_wb")
         self.gpio_o = Signal(n_gpio)
 
     def elaborate(self, platform):

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index cf072784faf5e85c64c0723d0bc9ba7c3fd03f16..d28d424d6fb4a9230854217bc5e4562ac536b1b8 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -63,8 +63,8 @@ class LibreSoC(CPU):
 
         self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5)
         self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14)
+        self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=5)
 
-        self.ics_buses = [icp, ics]
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
@@ -106,6 +106,7 @@ class LibreSoC(CPU):
         self.cpu_params.update(make_wb_bus("dbus_", dbus))
         self.cpu_params.update(make_wb_bus("ics_wb_", ics))
         self.cpu_params.update(make_wb_bus("icp_wb_", icp))
+        self.cpu_params.update(make_wb_bus("gpio_wb_", gpio))
 
         # add verilog sources
         self.add_sources(platform)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 460a85d549c6973800ec35c05d39b208dfc40484..a2125900ac4162d071d0efb9086a2ce5f86207c1 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -65,9 +65,9 @@ class LibreSoCSim(SoCSDRAM):
         #            "hello_world/hello_world.bin"
 
         # reserve XICS ICP and XICS memory addresses.
-        # TODO: not have these conflict with csr locations
         self.mem_map['icp'] = 0xc0004000
         self.mem_map['ics'] = 0xc0005000
+        self.mem_map['gpio'] = 0xc0007000
         #self.csr_map["icp"] = 8  #  8 x 0x800 == 0x4000
         #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
 
@@ -110,16 +110,24 @@ class LibreSoCSim(SoCSDRAM):
             )
         self.platform.name = "sim"
 
-        # XICS interrupt devices
-        icp_addr = self.mem_map['icp']
-        icp_wb = self.cpu.xics_icp
-        icp_region = SoCRegion(origin=icp_addr, size=0x1000, cached=False)
-        self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+        if cpu == "libresoc":
+            # XICS interrupt devices
+            icp_addr = self.mem_map['icp']
+            icp_wb = self.cpu.xics_icp
+            icp_region = SoCRegion(origin=icp_addr, size=0x1000, cached=False)
+            self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+
+            ics_addr = self.mem_map['ics']
+            ics_wb = self.cpu.xics_ics
+            ics_region = SoCRegion(origin=ics_addr, size=0x20, cached=False)
+            self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+
+            # Simple GPIO peripheral
+            gpio_addr = self.mem_map['gpio']
+            gpio_wb = self.cpu.simple_gpio
+            gpio_region = SoCRegion(origin=gpio_addr, size=0x20, cached=False)
+            self.bus.add_slave(name='gpio', slave=gpio_wb, region=gpio_region)
 
-        ics_addr = self.mem_map['ics']
-        ics_wb = self.cpu.xics_ics
-        ics_region = SoCRegion(origin=ics_addr, size=0x20, cached=False)
-        self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 
         # CRG -----------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 854c0981410c617b0fd5a79743c4a3b70d6b13ba..b93d47c2ed3b10d6276ce4c6ab4c98e613dfa193 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -30,6 +30,7 @@ if __name__ == '__main__':
                          xics=True,
                          gpio=True, # for test purposes
                          units=units)
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")