remove clock

diff --git a/examples/alu_hier.py b/examples/alu_hier.py
index 52ca05a80183cc69f72c8012da002c7a38987fd0..b42fb1d32bb58c89eaaac4d31c6bc6f9faa2f46e 100644 (file)
--- a/examples/alu_hier.py
+++ b/examples/alu_hier.py
@@ -32,8 +32,6 @@ class ALU(Elaboratable):
         self.a   = Signal(width)
         self.b   = Signal(width)
         self.o   = Signal(width)
-        self.m_clock   = Signal(reset_less=True)
-        self.p_reset   = Signal(reset_less=True)
 
         self.add = Adder(width)
         self.sub = Subtractor(width)
@@ -41,8 +39,8 @@ class ALU(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        m.domains.sync = ClockDomain()
-        m.d.comb += ClockSignal().eq(self.m_clock)
+        #m.domains.sync = ClockDomain()
+        #m.d.comb += ClockSignal().eq(self.m_clock)
 
         m.submodules.add = self.add
         m.submodules.sub = self.sub
@@ -66,5 +64,5 @@ def create_ilang(dut, ports, test_name):
 
 if __name__ == "__main__":
     alu = ALU(width=16)
-    create_ilang(alu, [alu.m_clock, alu.p_reset,
+    create_ilang(alu, [#alu.m_clock, alu.p_reset,
                        alu.op, alu.a, alu.b, alu.o], "alu_hier")