up the delay-time on ddr3 reset, put loop around dram init just for fun

diff --git a/coldboot/Makefile b/coldboot/Makefile
index afab3c798f24d0e85103458bcef094eed0c1aca4..1fb242269456f7a2ab03e228f64b82ca3292384c 100644 (file)
--- a/coldboot/Makefile
+++ b/coldboot/Makefile
@@ -7,8 +7,8 @@ endif
 
 # a multiplier factor on sleep loops. this allows simulations to run
 # at much shorter intervals
-LONG_TIMER_MULT = 10000
-SHORT_TIMER_MULT = 100
+LONG_TIMER_MULT = 100000
+SHORT_TIMER_MULT = 1000
 #LONG_TIMER_MULT = 1
 #SHORT_TIMER_MULT = 1
 

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 31e081f929c16ef09ffb8016b979e90ecd278054..e9bce65c995b316163ec4ac9c158f13486db4011 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -176,133 +176,134 @@ for (i=0;i<1000;i++) {
     return 0;
 #endif
 
-       puts("DRAM init... ");
+    for (int persistence=0; persistence < 1000; persistence++) {
+        puts("DRAM init... ");
 
-       struct gramCtx ctx;
+        struct gramCtx ctx;
 #if 1
-       struct gramProfile profile = {
-               .mode_registers = {
-                       0xb20, 0x806, 0x200, 0x0
-               },
-               .rdly_p0 = 2,
-               .rdly_p1 = 2,
-       };
+        struct gramProfile profile = {
+            .mode_registers = {
+                0xb20, 0x806, 0x200, 0x0
+            },
+            .rdly_p0 = 2,
+            .rdly_p1 = 2,
+        };
 #endif
 #if 0
-       struct gramProfile profile = {
-               .mode_registers = {
-                       0x0320, 0x0006, 0x0200, 0x0000
-               },
-               .rdly_p0 = 1,
-               .rdly_p1 = 1,
-       };
+        struct gramProfile profile = {
+            .mode_registers = {
+                0x0320, 0x0006, 0x0200, 0x0000
+            },
+            .rdly_p0 = 1,
+            .rdly_p1 = 1,
+        };
 #endif
-       struct gramProfile profile2;
-       gram_init(&ctx, &profile, (void*)DRAM_BASE,
-                              (void*)DRAM_CTRL_BASE,
-                              (void*)DRAM_INIT_BASE);
-       puts("done\n");
-
-       puts("MR profile: ");
-       uart_writeuint32(profile.mode_registers[0]);
-       puts(" ");
-       uart_writeuint32(profile.mode_registers[1]);
-       puts(" ");
-       uart_writeuint32(profile.mode_registers[2]);
-       puts(" ");
-       uart_writeuint32(profile.mode_registers[3]);
-       puts("\n");
-
-       // FIXME
-       // Early read test for WB access sim
-       //uart_writeuint32(*ram);
+        struct gramProfile profile2;
+        gram_init(&ctx, &profile, (void*)DRAM_BASE,
+                                  (void*)DRAM_CTRL_BASE,
+                                  (void*)DRAM_INIT_BASE);
+        puts("done\n");
+
+        puts("MR profile: ");
+        uart_writeuint32(profile.mode_registers[0]);
+        puts(" ");
+        uart_writeuint32(profile.mode_registers[1]);
+        puts(" ");
+        uart_writeuint32(profile.mode_registers[2]);
+        puts(" ");
+        uart_writeuint32(profile.mode_registers[3]);
+        puts("\n");
+
+        // FIXME
+        // Early read test for WB access sim
+        //uart_writeuint32(*ram);
 
 #if 1
-       puts("Rdly\np0: ");
-       for (size_t i = 0; i < 8; i++) {
-               profile2.rdly_p0 = i;
-               gram_load_calibration(&ctx, &profile2);
-               gram_reset_burstdet(&ctx);
-
-               for (size_t j = 0; j < 128; j++) {
-                       tmp = readl((unsigned long)&(ram[i]));
-               }
-               if (gram_read_burstdet(&ctx, 0)) {
-                       puts("1");
-               } else {
-                       puts("0");
-               }
-       }
-       puts("\n");
-
-       puts("Rdly\np1: ");
-       for (size_t i = 0; i < 8; i++) {
-               profile2.rdly_p1 = i;
-               gram_load_calibration(&ctx, &profile2);
-               gram_reset_burstdet(&ctx);
-               for (size_t j = 0; j < 128; j++) {
-                       tmp = readl((unsigned long)&(ram[i]));
-               }
-               if (gram_read_burstdet(&ctx, 1)) {
-                       puts("1");
-               } else {
-                       puts("0");
-               }
-       }
-       puts("\n");
-
-       puts("Auto calibrating... ");
-       res = gram_generate_calibration(&ctx, &profile2);
-       if (res != GRAM_ERR_NONE) {
-               puts("failed\n");
-               gram_load_calibration(&ctx, &profile);
-       } else {
-               gram_load_calibration(&ctx, &profile2);
-       }
-       puts("done\n");
-
-       puts("Auto calibration profile:");
-       puts("p0 rdly:");
-       uart_writeuint32(profile2.rdly_p0);
-       puts(" p1 rdly:");
-       uart_writeuint32(profile2.rdly_p1);
-       puts("\n");
-#endif
-
-       puts("Reloading built-in calibration profile...");
-       gram_load_calibration(&ctx, &profile);
-
-       puts("DRAM test... \n");
-       for (size_t i = 0; i < kNumIterations; i++) {
-               writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
-       }
+        puts("Rdly\np0: ");
+        for (size_t i = 0; i < 8; i++) {
+            profile2.rdly_p0 = i;
+            gram_load_calibration(&ctx, &profile2);
+            gram_reset_burstdet(&ctx);
+
+            for (size_t j = 0; j < 128; j++) {
+                tmp = readl((unsigned long)&(ram[i]));
+            }
+            if (gram_read_burstdet(&ctx, 0)) {
+                puts("1");
+            } else {
+                puts("0");
+            }
+        }
+        puts("\n");
+
+        puts("Rdly\np1: ");
+        for (size_t i = 0; i < 8; i++) {
+            profile2.rdly_p1 = i;
+            gram_load_calibration(&ctx, &profile2);
+            gram_reset_burstdet(&ctx);
+            for (size_t j = 0; j < 128; j++) {
+                tmp = readl((unsigned long)&(ram[i]));
+            }
+            if (gram_read_burstdet(&ctx, 1)) {
+                puts("1");
+            } else {
+                puts("0");
+            }
+        }
+        puts("\n");
+
+        puts("Auto calibrating... ");
+        res = gram_generate_calibration(&ctx, &profile2);
+        if (res != GRAM_ERR_NONE) {
+            puts("failed\n");
+            gram_load_calibration(&ctx, &profile);
+        } else {
+            gram_load_calibration(&ctx, &profile2);
+        }
+        puts("done\n");
 
-#if 0
-       for (int dly = 0; dly < 8; dly++) {
-        failcnt = 0;
-        profile2.rdly_p0 = dly;
-        profile2.rdly_p1 = dly;
+        puts("Auto calibration profile:");
         puts("p0 rdly:");
         uart_writeuint32(profile2.rdly_p0);
         puts(" p1 rdly:");
         uart_writeuint32(profile2.rdly_p1);
-               gram_load_calibration(&ctx, &profile2);
+        puts("\n");
+#endif
+
+        puts("Reloading built-in calibration profile...");
+        gram_load_calibration(&ctx, &profile);
+
+        puts("DRAM test... \n");
         for (size_t i = 0; i < kNumIterations; i++) {
-            if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
-                puts("fail : *(0x");
-                uart_writeuint32((unsigned long)(&ram[i]));
-                puts(") = ");
-                uart_writeuint32(readl((unsigned long)&(ram[i])));
-                puts("\n");
-                failcnt++;
+            writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
+        }
 
-                if (failcnt > 10) {
-                    puts("Test canceled (more than 10 errors)\n");
-                    break;
+#if 0
+        for (int dly = 0; dly < 8; dly++) {
+            failcnt = 0;
+            profile2.rdly_p0 = dly;
+            profile2.rdly_p1 = dly;
+            puts("p0 rdly:");
+            uart_writeuint32(profile2.rdly_p0);
+            puts(" p1 rdly:");
+            uart_writeuint32(profile2.rdly_p1);
+            gram_load_calibration(&ctx, &profile2);
+            for (size_t i = 0; i < kNumIterations; i++) {
+                if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
+                    puts("fail : *(0x");
+                    uart_writeuint32((unsigned long)(&ram[i]));
+                    puts(") = ");
+                    uart_writeuint32(readl((unsigned long)&(ram[i])));
+                    puts("\n");
+                    failcnt++;
+
+                    if (failcnt > 10) {
+                        puts("Test canceled (more than 10 errors)\n");
+                        break;
+                    }
                 }
             }
         }
-    }
 #else
         failcnt = 0;
         for (size_t i = 0; i < kNumIterations; i++) {
@@ -320,6 +321,10 @@ for (i=0;i<1000;i++) {
                 }
             }
         }
+        if (failcnt == 0) { // fiinally...
+            break;
+        }
+    }
 #endif
        puts("done\n");
 

diff --git a/src/ls2.py b/src/ls2.py
index 2dff604f5b5396360f0a6ac5bb595904b8d51ba1..ce572696d063f9b9920881a1f0ec66833a006c75 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -644,7 +644,7 @@ def build_platform(fpga, firmware):
     if fpga == 'isim':
         clk_freq = 55e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
-        clk_freq = 50e6 # crank right down to test hyperram
+        clk_freq = 55e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
         # 50MHz works.  100MHz works.  55MHz does NOT work.
         # Stick with multiples of 50MHz...
@@ -680,7 +680,7 @@ def build_platform(fpga, firmware):
 
     # Get SPI resource pins
     spi_0_pins = None
-    if platform is not None and \
+    if False and platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Override here to get FlashResource out of the way and enable Tercel
         # direct access to the SPI flash.
@@ -781,7 +781,8 @@ def build_platform(fpga, firmware):
         hyperram_pins = platform.request("hyperram")
         print ("arty a7 hyperram", hyperram_ios)
     # VERSA ECP5
-    elif platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85']:
+    elif False and platform is not None and fpga in \
+                ['versa_ecp5', 'versa_ecp5_85']:
         hyperram_ios = HyperRAMResource(0, cs_n="B13",
                                         dq="E14 C10 B10 E12 D12 A9 D11 D14",
                                         rwds="C14", rst_n="E13", ck_p="D13",