create signal on test_issuer which gives PLL clk_sel_i a useful name

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index 168822c843eacf9a05d5258b92f0122cc8b35154..912490d29a0b08822f5ecdc52a373da70322fc0a 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -9,7 +9,6 @@ class DummyPLL(Elaboratable):
         self.clk_24_i = Signal(name="ref", reset_less=True) # external incoming
         self.sel_a0_i = Signal(name="a0", reset_less=True) # PLL selection
         self.sel_a1_i = Signal(name="a1", reset_less=True) # PLL selection
-        self.clk_sel_i = Signal(2, reset_less=True) # same as a0,a1
         self.clk_pll_o = Signal(name="out", reset_less=True)  # output clock
         self.pll_18_o = Signal(name="div_out_test", reset_less=True)  # test out
         self.pll_ana_o = Signal(name="vco_test_ana", reset_less=True) # analog
@@ -22,9 +21,6 @@ class DummyPLL(Elaboratable):
             m.d.comb += self.pll_ana_o.eq(self.clk_24_i)
             m.d.comb += self.pll_18_o.eq(~self.clk_24_i)
 
-        # same API
-        m.d.comb += self.clk_sel_i.eq(Cat(self.sel_a0_i, self.sel_a1_i))
-
         #self.attrs['blackbox'] = 1
 
         return m

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 725823dad3bbbe501a0f4af6d0dff52570f7644b..a5f7304f08771a3ddaaca9a79eac6955e17ff2a3 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1155,6 +1155,7 @@ class TestIssuer(Elaboratable):
         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
         if self.pll_en:
             self.pll_18_o = Signal(reset_less=True)
+            self.clk_sel_i = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -1183,6 +1184,9 @@ class TestIssuer(Elaboratable):
             # output 18 mhz PLL test signal
             comb += self.pll_18_o.eq(pll.pll_18_o)
 
+            # input to pll clock selection
+            comb += Cat(pll.sel_a0_i, pll.sel_a1_i).eq(self.clk_sel_i)
+
             # now wire up ResetSignals.  don't mind them being in this domain
             pll_rst = ResetSignal("pllclk")
             comb += pll_rst.eq(ResetSignal())
@@ -1206,7 +1210,7 @@ class TestIssuer(Elaboratable):
         ports.append(ClockSignal())
         ports.append(ResetSignal())
         if self.pll_en:
-            ports.append(self.pll.clk_sel_i)
+            ports.append(self.clk_sel_i)
             ports.append(self.pll_18_o)
             ports.append(self.pll.pll_ana_o)
         return ports