add sdr bypass routing via JTAG boundary scan

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 38c8d008deaebbc214d4bb37ddd7f89c7934472b..f72e2f076a9ca66132fe7cefe3823e291bbf55f4 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -50,19 +50,33 @@ def get_field(rec, name):
 def make_jtag_ioconn(res, pin, cpupads, iopads):
     (fn, pin, iotype, pin_name, scan_idx) = pin
     #serial_tx__core__o, serial_rx__pad__i,
+    # special-case sdram_clock
+    if pin == 'clock' and fn == 'sdr':
+        cpu = cpupads['sdram_clock']
+        io = iopads['sdram_clock']
+    else:
+        cpu = cpupads[fn]
+        io = iopads[fn]
     print ("cpupads", cpupads)
     print ("iopads", iopads)
     print ("pin", fn, pin, iotype, pin_name)
-    cpu = cpupads[fn]
-    io = iopads[fn]
     print ("cpu fn", cpu)
     print ("io fn", io)
-    sigs = []
-
     name = "%s_%s" % (fn, pin)
+    print ("name", name)
+    sigs = []
 
     if iotype in (IOType.In, IOType.Out):
-        if pin.isdigit():
+        ps = pin.split("_")
+        if pin == 'clock' and fn == 'sdr':
+            cpup = cpu
+            iop = io
+        elif len(ps) == 2 and ps[-1].isdigit():
+            pin, idx = ps
+            idx = int(idx)
+            cpup = getattr(cpu, pin)[idx]
+            iop = getattr(io, pin)[idx]
+        elif pin.isdigit():
             idx = int(pin)
             cpup = cpu[idx]
             iop = io[idx]
@@ -236,7 +250,7 @@ class LibreSoC(CPU):
             iopads = {}
             litexmap = {}
             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0'}#, 'sdr'}
+                      'pwm', 'sd0', 'sdr'}
             for periph in subset:
                 origperiph = periph
                 num = None
@@ -248,6 +262,8 @@ class LibreSoC(CPU):
                         periph, num = 'spimaster', None
                     else:
                         periph, num = 'spisdcard', None
+                elif periph == 'sdr':
+                    periph = 'sdram'
                 elif periph == 'mtwi':
                     periph = 'i2c'
                 elif periph == 'sd':
@@ -255,6 +271,12 @@ class LibreSoC(CPU):
                 litexmap[origperiph] = (periph, num)
                 self.cpupads[origperiph] = platform.request(periph, num)
                 iopads[origperiph] = self.pad_cm.request(periph, num)
+                if periph == 'sdram':
+                    # special-case sdram clock
+                    ck = platform.request("sdram_clock")
+                    self.cpupads['sdram_clock'] = ck
+                    ck = self.pad_cm.request("sdram_clock")
+                    iopads['sdram_clock'] = ck
 
             pinset = get_pinspecs(subset=subset)
             p = Pins(pinset)

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 29d89122f12675a76e2c57609fc4cd45942cd749..9da9d180a23c45448ddd1d1628549e1eb88791a6 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -385,7 +385,8 @@ class LibreSoCSim(SoCCore):
                             clk_freq   = sdram_clk_freq)
             #sdrphy_cls = HalfRateGENSDRPHY
             sdrphy_cls = GENSDRPHY
-            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
+            sdram_pads = self.cpu.cpupads['sdr']
+            self.submodules.sdrphy = sdrphy_cls(sdram_pads)
             #self.submodules.sdrphy = sdrphy_cls(sdram_module,
             #                                       phy_settings,
             #                                       init=ram_init
@@ -409,7 +410,7 @@ class LibreSoCSim(SoCCore):
 
             # SDRAM clock
             sys_clk = ClockSignal()
-            sdr_clk = platform.request("sdram_clock")
+            sdr_clk = self.cpu.cpupads['sdram_clock']
             #self.specials += DDROutput(1, 0, , sdram_clk)
             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index fe0a18a1abfe4010c1afc0c340e0e39bef1f8bdf..06911b6348d1b9dae09e01ad060b462828414b9e 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -85,7 +85,7 @@ class TestIssuerInternal(Elaboratable):
         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
         if self.jtag_en:
             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0'}#, 'sdr'}
+                      'pwm', 'sd0', 'sdr'}
             self.jtag = JTAG(get_pinspecs(subset=subset))
 
         # instruction go/monitor