remove niolib io_in/out signal, no longer needed

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 16f794c153c19422b9a60bb9477cdf72d1534f1d..2841a4cb8b78e2c36eb9349cbba2aa9559cbeda8 100644 (file)
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -107,11 +107,7 @@ def generate_spec():
         # where direction is "+" for out, "-" for in, "*" for bi-directionaly
         if len(pad) == 4:
             print("4-long io", pad)
-            if pad[-1] == '-':
-                en_sig = 'io_in'
-            if pad[-1] == '+':
-                en_sig = 'io_out'
-            padspec = [padside, None, padname, pad[1], pad[2], en_sig]
+            padspec = [padside, None, padname, pad[1], pad[2]]
 
         # format here is:
         # ['padname', 'something', 'to core', 'from core', 'en', 'direction']

diff --git a/experiments9/non_generated/ls180.vst b/experiments9/non_generated/ls180.vst
index e4d51e80728f0fb5250327c500a0b64ad151a5ac..9e24a4b5c474633782a7a8abaacd4adddae660a9 100644 (file)
--- a/experiments9/non_generated/ls180.vst
+++ b/experiments9/non_generated/ls180.vst
@@ -59,8 +59,6 @@ entity ls180 is
        ; gpio_o          : out bit_vector(15 downto 0)
        ; gpio_oe         : out bit_vector(15 downto 0)
        ; sdram_dq_o      : out bit_vector(15 downto 0)
-       ; io_in           : out bit
-       ; io_out          : out bit
        ; vdd             : linkage bit
        ; vss             : linkage bit
        );
@@ -92,23 +90,11 @@ architecture structural of ls180 is
 
 begin
 
-  zero_1 : zero_x0
-  port map ( nq  => io_in
-           , vdd => vdd
-           , vss => vss
-           );
-
   zero_0 : zero_x0
   port map ( nq  => i2c_scl
            , vdd => vdd
            , vss => vss
            );
 
-  one_0 : one_x0
-  port map ( q  => io_out
-           , vdd => vdd
-           , vss => vss
-           );
-
 end structural;