experiments9/non_generated/ls180.vst

   1
   2 -- =======================================================================
   3 -- Coriolis Structural VHDL Driver
   4 -- Generated on Oct 01, 2020, 15:11
   5 --
   6 -- Genarated with options:
   7 -- * VstUseConcat:   Use concat (&) in port map.
   8 --
   9 -- To be interoperable with Alliance, it uses it's special VHDL subset.
  10 -- ("man vhdl" under Alliance for more informations)
  11 -- =======================================================================
  12
  13 entity ls180 is
  14   port ( i2c_sda_i       : in bit
  15        ; jtag_tck        : in bit
  16        ; jtag_tdi        : in bit
  17        ; jtag_tms        : in bit
  18        ; sdcard_cmd_i    : in bit
  19        ; spimaster_miso : in bit
  20        ; spisdcard_miso  : in bit
  21        ; sys_clk         : in bit
  22        ; sys_rst         : in bit
  23        ; uart_rx         : in bit
  24        ; eint            : in bit_vector(2 downto 0)
  25        ; sys_clksel_i    : in bit_vector(1 downto 0)
  26        ; sys_pllock      : out bit
  27        ; sdcard_data_i   : in bit_vector(3 downto 0)
  28        ; gpio_i          : in bit_vector(15 downto 0)
  29        ; sdram_dq_i      : in bit_vector(15 downto 0)
  30        ; nc              : in bit_vector(23 downto 0)
  31        ; i2c_scl         : out bit
  32        ; i2c_sda_o       : out bit
  33        ; i2c_sda_oe      : out bit
  34        ; jtag_tdo        : out bit
  35        ; pwm             : in bit_vector(1 downto 0)
  36        ; sdcard_clk      : out bit
  37        ; sdcard_cmd_o    : out bit
  38        ; sdcard_cmd_oe   : out bit
  39        ; sdcard_data_oe  : out bit
  40        ; sdram_cas_n     : out bit
  41        ; sdram_cke       : out bit
  42        ; sdram_clock     : out bit
  43        ; sdram_cs_n      : out bit
  44        ; sdram_dq_oe     : out bit
  45        ; sdram_ras_n     : out bit
  46        ; sdram_we_n      : out bit
  47        ; spimaster_clk  : out bit
  48        ; spimaster_cs_n : out bit
  49        ; spimaster_mosi : out bit
  50        ; spisdcard_clk   : out bit
  51        ; spisdcard_cs_n  : out bit
  52        ; spisdcard_mosi  : out bit
  53        ; sys_pll_48_o    : out bit
  54        ; uart_tx         : out bit
  55        ; sdram_ba        : out bit_vector(1 downto 0)
  56        ; sdram_dm        : out bit_vector(1 downto 0)
  57        ; sdcard_data_o   : out bit_vector(3 downto 0)
  58        ; sdram_a         : out bit_vector(12 downto 0)
  59        ; gpio_o          : out bit_vector(15 downto 0)
  60        ; gpio_oe         : out bit_vector(15 downto 0)
  61        ; sdram_dq_o      : out bit_vector(15 downto 0)
  62        ; io_in           : out bit
  63        ; io_out          : out bit
  64        ; vdd             : linkage bit
  65        ; vss             : linkage bit
  66        );
  67 end ls180;
  68
  69 architecture structural of ls180 is
  70
  71   component inv_x1
  72     port ( i   : in bit
  73          ; nq  : out bit
  74          ; vdd : in bit
  75          ; vss : in bit
  76          );
  77   end component;
  78
  79   component zero_x0
  80     port ( nq  : out bit
  81          ; vdd : in bit
  82          ; vss : in bit
  83          );
  84   end component;
  85
  86   component one_x0
  87     port ( q  : out bit
  88          ; vdd : in bit
  89          ; vss : in bit
  90          );
  91   end component;
  92
  93 begin
  94
  95   zero_1 : zero_x0
  96   port map ( nq  => io_in
  97            , vdd => vdd
  98            , vss => vss
  99            );
 100
 101   zero_0 : zero_x0
 102   port map ( nq  => i2c_scl
 103            , vdd => vdd
 104            , vss => vss
 105            );
 106
 107   one_0 : one_x0
 108   port map ( q  => io_out
 109            , vdd => vdd
 110            , vss => vss
 111            );
 112
 113 end structural;
 114