#endif
.text
- .globl _start
+ .align 6
+user_trap_entry:
+ j trap_entry
+
+ .align 6
+supervisor_trap_entry:
+ j supervisor_trap_entry
+
+ .align 6
+hypervisor_trap_entry:
+ j hypervisor_trap_entry
+ .align 6
+machine_trap_entry:
+ j trap_entry
+
+ .align 6
+ .globl _start
_start:
li x1, 0
li x2, 0
li x30,0
li x31,0
- # initialize status, enable fp, accelerator, interrupts
- li a0, SR_S | SR_PEI | SR_EF | SR_EA
- csrw status, a0
+ li t0, MSTATUS_PRV1; csrc mstatus, t0 # run tests in user mode
+ li t0, MSTATUS_IE1; csrs mstatus, t0 # enable interrupts in user mode
+ li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU
+ li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator
-#ifdef __riscv64
- li a0, SR_U64 | SR_S64
- csrs status, a0
+#ifndef __riscv64
+ li t0, MSTATUS_UA; csrc mstatus, t0 # disable RV64 for user mode
#endif
- csrr t0, status
- and t1, t0, SR_EA
+ csrr t0, mstatus
+ li t1, MSTATUS_XS
+ and t1, t0, t1
sw t1, have_vec, t2
## if that didn't stick, we don't have a FPU, so don't initialize it
- and t1, t0, SR_EF
+ li t1, MSTATUS_FS
+ and t1, t0, t1
beqz t1, 1f
fssr x0
fmv.s.x f31,x0
1:
- la t0, trap_entry
- csrw evec, t0
-
la tp, _end + 63
and tp, tp, -64
- # get core id and number of cores
+ # get core id
csrr a0, hartid
- lw a1, 4(zero)
+ # for now, assume only 1 core
+ li a1, 1
+1:bgeu a0, a1, 1b
# give each core 128KB of stack + TLS
#define STKSHIFT 17
add sp, sp, tp
la t0, _init
- csrw epc, t0
- sret
+ csrw mepc, t0
+ mret
trap_entry:
addi sp, sp, -272
SREG x30, 240(sp)
SREG x31, 248(sp)
- csrr t0, sup0
- csrr t1, status
- SREG t0, 256(sp)
- SREG t1, 264(sp)
-
- csrr a0, cause
- csrr a1, epc
+ csrr a0, mcause
+ csrr a1, mepc
mv a2, sp
jal handle_trap
- csrw epc, a0
-
- LREG t0, 256(sp)
- LREG t1, 264(sp)
- csrw sup0, t0
- csrw status, t1
+ csrw mepc, a0
LREG x1, 8(sp)
LREG x2, 16(sp)
LREG x31, 248(sp)
addi sp, sp, 272
- sret
+ mret
.section ".tdata.begin"
.globl _tdata_begin
if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
(*(int*)epc & *csr_insn) == *csr_insn)
;
- else if (cause != CAUSE_SYSCALL)
+ else if (cause != CAUSE_SCALL)
tohost_exit(1337);
else if (regs[17] == SYS_exit)
tohost_exit(regs[10]);
OUTPUT_ARCH( "riscv" )
-/* The ENTRY command specifies the entry point (ie. first instruction
- to execute). The symbol _start should be defined in each test. */
-
-ENTRY( _start )
-
/*----------------------------------------------------------------------*/
/* Sections */
/*----------------------------------------------------------------------*/
{
/* text: test code section */
- . = 0x00002000;
+ . = 0;
.text :
{
crt.o(.text)
-Subproject commit 18e64b6ced40e97a0469b47471f2b66305264a16
+Subproject commit 3a2ed4c0966add8f9730c3962a784cc423891663
include $(isa_src_dir)/rv64ui/Makefrag
include $(isa_src_dir)/rv64uf/Makefrag
-include $(isa_src_dir)/rv64uv/Makefrag
+#include $(isa_src_dir)/rv64uv/Makefrag
include $(isa_src_dir)/rv64si/Makefrag
-include $(isa_src_dir)/rv64sv/Makefrag
+#include $(isa_src_dir)/rv64sv/Makefrag
include $(isa_src_dir)/rv32ui/Makefrag
include $(isa_src_dir)/rv32si/Makefrag
#define TEST_PASSFAIL \
bne x0, TESTNUM, pass; \
fail: \
- RVTEST_FAIL \
+ RVTEST_FAIL; \
pass: \
RVTEST_PASS \
#define TEST_PASSFAIL \
bne x0, TESTNUM, pass; \
fail: \
- RVTEST_FAIL \
+ RVTEST_FAIL; \
pass: \
RVTEST_PASS \
shamt \
ma_fetch \
illegal \
- privileged \
scall \
sbreak \
ma_addr \
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la t0, evec
- csrw evec, t0
+ la t0, stvec
+ csrw stvec, t0
li TESTNUM, 2
.word 0
TEST_PASSFAIL
-evec:
+stvec:
li t1, CAUSE_ILLEGAL_INSTRUCTION
- csrr t0, cause
+ csrr t0, scause
bne t0, t1, fail
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 8
- csrw epc, t0
+ csrw sepc, t0
sret
RVTEST_CODE_END
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la s0, evec_load
+ la s0, stvec_load
- la t0, evec_load
- csrw evec, t0
+ la t0, stvec_load
+ csrw stvec, t0
li TESTNUM, 2
lw x0, 1(s0)
lhu x0, 1(s0)
j fail
- la t0, evec_store
- csrw evec, t0
+ la t0, stvec_store
+ csrw stvec, t0
li TESTNUM, 7
sw x0, 1(s0)
TEST_PASSFAIL
-evec_load:
+stvec_load:
li t1, CAUSE_MISALIGNED_LOAD
- csrr t0, cause
+ csrr t0, scause
bne t0, t1, fail
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 8
- csrw epc, t0
+ csrw sepc, t0
sret
-evec_store:
+stvec_store:
li t1, CAUSE_MISALIGNED_STORE
- csrr t0, cause
+ csrr t0, scause
bne t0, t1, fail
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 8
- csrw epc, t0
+ csrw sepc, t0
sret
RVTEST_CODE_END
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la t0, evec
- csrw evec, t0
+ la t0, stvec
+ csrw stvec, t0
li TESTNUM, 2
la t0, 1f
TEST_PASSFAIL
-evec:
+stvec:
li t0, 3
beq TESTNUM, t0, fail
li t1, CAUSE_MISALIGNED_FETCH
- csrr t0, cause
+ csrr t0, scause
bne t0, t1, fail
li t1, 0
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 2 // skip over instruction after jalr
- csrw epc, t0
+ csrw sepc, t0
sret
RVTEST_CODE_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# privileged.S
-#-----------------------------------------------------------------------------
-#
-# Test privileged instruction trap.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32S
-RVTEST_CODE_BEGIN
-
- la t0, evec
- csrw evec, t0
-
- csrci status, 1
-
- li TESTNUM, 2
- sret
- j fail
-
- TEST_PASSFAIL
-
-evec:
- li t1, CAUSE_PRIVILEGED_INSTRUCTION
- csrr t0, cause
- bne t0, t1, fail
- j pass
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la t0, evec
- csrw evec, t0
+ la t0, stvec
+ csrw stvec, t0
li TESTNUM, 2
sbreak
TEST_PASSFAIL
-evec:
+stvec:
li t1, CAUSE_BREAKPOINT
- csrr t0, cause
+ csrr t0, scause
bne t0, t1, fail
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 8
- csrw epc, t0
+ csrw sepc, t0
sret
RVTEST_CODE_END
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la t0, evec
- csrw evec, t0
+ la t0, stvec
+ csrw stvec, t0
li TESTNUM, 2
scall
TEST_PASSFAIL
-evec:
- li t1, CAUSE_SYSCALL
- csrr t0, cause
+stvec:
+ li t1, CAUSE_SCALL
+ csrr t0, scause
bne t0, t1, fail
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 8
- csrw epc, t0
+ csrw sepc, t0
sret
RVTEST_CODE_END
RVTEST_RV32S
RVTEST_CODE_BEGIN
- la t0, evec
- csrw evec, t0
+ la t0, stvec
+ csrw stvec, t0
# Make sure slli with shamt[4] set is legal.
TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
- # Make sure slli with shamt[4] set is not legal.
+ # Make sure slli with shamt[5] set is not legal.
TEST_CASE( 3, x0, 1, slli a0, a0, 32);
TEST_PASSFAIL
-evec:
+stvec:
# Trapping on test 3 is good.
# Note that since the test didn't complete, TESTNUM is smaller by 1.
li t0, 2
bne TESTNUM, t0, fail
# Make sure CAUSE indicates an illegal instructino.
- csrr t0, cause
+ csrr t0, scause
li t1, CAUSE_ILLEGAL_INSTRUCTION
bne t0, t1, fail
j pass
RVTEST_RV32U
RVTEST_CODE_BEGIN
-# wait for all cores to boot
+# get a unique core id
la a0, coreid
li a1, 1
amoadd.w a2, a1, (a0)
-lw a3, 4(x0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
1: lw a1, (a0)
-blt a1, a3, 1b
+bltu a1, a3, 1b
# make sure that sc without a reservation fails.
TEST_CASE( 2, a4, 1, \
#-----------------------------------------------------------------------
rv64si_sc_tests = \
- coreid \
csr \
timer \
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# coreid.S
-#-----------------------------------------------------------------------------
-#
-# Test coreid.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64S
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Basic tests
- #-------------------------------------------------------------
-
- TEST_CASE( 2, x1, 0x0, li x1, 1; csrr x1, hartid );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
RVTEST_RV64S
RVTEST_CODE_BEGIN
- # Set up evec in case we trap.
- la t0, evec
- csrw evec, t0
- csrwi count, 0
-
- csrwi sup0, 3
- TEST_CASE( 2, a0, 3, csrr a0, sup0);
- TEST_CASE( 3, a1, 3, csrrci a1, sup0, 1);
- TEST_CASE( 4, a2, 2, csrrsi a2, sup0, 4);
- TEST_CASE( 5, a3, 6, csrrwi a3, sup0, 2);
- TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sup0, a0);
- TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sup0, a0);
- TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sup0, a0);
- TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sup0);
+ # Set up stvec in case we trap.
+ la t0, stvec
+ csrw stvec, t0
+ csrwi scycle, 0
+
+ csrwi sscratch, 3
+ TEST_CASE( 2, a0, 3, csrr a0, sscratch);
+ TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1);
+ TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4);
+ TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2);
+ TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
+ TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
+ TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
+ TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
# Make sure writing the cycle counter causes an exception.
TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+ # Enter user mode
+ li t0, SSTATUS_PS
+ csrc sstatus, t0
+ la t0, 1f
+ csrw sepc, t0
+ sret
+ 1:
+
# Make sure reading status in user mode causes an exception.
- csrci status, SR_S|SR_PS
- TEST_CASE(11, a0, 255, li a0, 255; csrr a0, status);
+ TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus);
# Make sure rdcycle is legal in user mode.
TEST_CASE(12, x0, 0, rdcycle a0)
# We should only fall through to this if scall failed.
TEST_PASSFAIL
-evec:
+stvec:
# Trapping on tests 10, 11, and 13 is usually good news.
# Note that since the test didn't complete, TESTNUM is smaller by 1.
li t0, 9
privileged:
# Make sure CAUSE indicates a lack of privilege.
- csrr t0, cause
- li t1, CAUSE_PRIVILEGED_INSTRUCTION
+ csrr t0, scause
+ li t1, CAUSE_ILLEGAL_INSTRUCTION
bne t0, t1, fail
# Return to user mode, but skip the trapping instruction.
- csrr t0, epc
+ csrr t0, sepc
addi t0, t0, 4
- csrw epc, t0
+ csrw sepc, t0
sret
syscall:
# Make sure CAUSE indicates a syscall.
- csrr t0, cause
- li t1, CAUSE_SYSCALL
+ csrr t0, scause
+ li t1, CAUSE_SCALL
bne t0, t1, fail
# We're done.
#include "riscv_test.h"
#include "test_macros.h"
-RVTEST_RV64S
+RVTEST_RV64M
RVTEST_CODE_BEGIN
- # clear pending IPIs then enable interrupts
- la a0, handler
- csrw evec, a0
- csrw clear_ipi, x0
- li a0, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
- csrs status, a0
+ # enable interrupts
+ csrs mstatus, MSTATUS_IE
- # wait for all cores to boot
+ # get a unique core id
la a0, coreid
li a1, 1
- amoadd.w x0, a1, 0(a0)
- lw a3, 4(x0)
- 1: lw a1, 0(a0)
- blt a1, a3, 1b
+ amoadd.w a2, a1, (a0)
+
+ # for now, only run this on core 0
+ 1:li a3, 1
+ bgeu a2, a3, 1b
+
+ # wait for all cores to boot
+ 1: lw a1, (a0)
+ bltu a1, a3, 1b
# IPI dominoes
csrr a0, hartid
csrw send_ipi, a0
1: j 1b
- handler:
+mtvec:
csrr a0, hartid
bnez a0, 2f
RVTEST_PASS
li s8, 0 # number of taken timer interrupts
li s9, 10 # how many interrupts to run for
la a0, handler
- csrw evec, a0
- csrw compare, 1
- csrw count, 0
- li a0, SR_EI | (1 << (IRQ_TIMER + SR_IM_SHIFT))
- csrs status, a0
+ csrw stvec, a0
+ csrw stimecmp, 1
+ csrw stime, 0
+ li a0, SSTATUS_IE | SSTATUS_TIE
+ csrs sstatus, a0
# advance an LFSR 1000 times
li s0, 1023
add s4, s4, 1
bltu s8, s9, 1b
- csrc status, SR_EI
+ csrc sstatus, SSTATUS_IE
# make sure the LFSR was computed correctly
li s1, 1023
handler:
li TESTNUM, 3
- csrr t0, cause
+ csrr t0, scause
bgez t0, fail
sll t0, t0, 1
addi t0, t0, -2*IRQ_TIMER
bnez t0, fail
- csrr t0, count
+ csrr t0, stime
addi t0, t0, 999
- csrw compare, t0
+ csrw stimecmp, t0
add s8, s8, 1
ldst move structural \
rv64uf_sc_vec_tests = \
- fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
+# fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \
rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
-rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
-rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
-rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
+#rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests))
+#rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
+#rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
lrsc
rv64ui_sc_vec_tests = \
- add addi addiw addw \
- and andi \
- lui \
- mul mulh mulhsu mulhu mulw \
- or ori \
- sll slli slliw sllw \
- slt slti sltiu sltu \
- sra srai sraiw sraw \
- srl srli srliw srlw \
- sub subw \
- xor xori \
+ #add addi addiw addw \
+ #and andi \
+ #lui \
+ #mul mulh mulhsu mulhu mulw \
+ #or ori \
+ #sll slli slliw sllw \
+ #slt slti sltiu sltu \
+ #sra srai sraiw sraw \
+ #srl srli srliw srlw \
+ #sub subw \
+ #xor xori \
rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests))
RVTEST_RV64U
RVTEST_CODE_BEGIN
-# wait for all cores to boot
+# get a unique core id
la a0, coreid
li a1, 1
amoadd.w a2, a1, (a0)
-lw a3, 4(x0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
1: lw a1, (a0)
-blt a1, a3, 1b
+bltu a1, a3, 1b
# make sure that sc without a reservation fails.
TEST_CASE( 2, a4, 1, \
projects / riscv-tests.git / commitdiff