add OP_SC

diff --git a/libreriscv b/libreriscv
index 22a93badbd972f3f6009ff1a2d7be2948dcb45d2..bd0a43e88d6ee58a5d331d70e182cbadca54d7b8 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 22a93badbd972f3f6009ff1a2d7be2948dcb45d2
+Subproject commit bd0a43e88d6ee58a5d331d70e182cbadca54d7b8

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 415d9e0657f0bee471ca39e84967237d487a6498..f179f2cecd97ea5fbcf2b1b6d59f0025ef2a654b 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -201,6 +201,7 @@ class InternalOp(Enum):
     OP_RFID = 70
     OP_MFMSR = 71
     OP_MTMSRD = 72
+    OP_SC = 73
 
 
 @unique