from nmigen.cli import rtlil
-from ieee754.part.test.test_partsig import TestAddMod2
+from test_partsig import TestAddMod2
import subprocess
import os
from nmigen import Signal
],
"part_sig_add")
-def run_yosys(test_name):
- liberty_file = os.getenv("HOME")+"/coriolis-2.x/src/alliance-check-toolkit/cells/nsxlib/nsxlib.lib"
- print("test_name:",test_name)
- cmd = [
- "read_ilang part_sig_add.il",
- "hierarchy -check -top part_sig_add",
- "synth -top part_sig_add",
- "dfflibmap -liberty "+liberty_file,
- "abc -liberty "+liberty_file,
- "clean",
- "write_blif test.blif"
- ]
- cmd = "; ".join(cmd)
- subprocess.call(["yosys","-p",cmd])
-
def create_ilang(dut, ports, test_name):
vl = rtlil.convert(dut, name=test_name, ports=ports)
with open("%s.il" % test_name, "w") as f:
f.write(vl)
- #run_yosys(test_name)
-
if __name__ == "__main__":
test()
--- /dev/null
+#!/usr/bin/env python3
+# SPDX-License-Identifier: LGPL-2.1-or-later
+# See Notices.txt for copyright information
+
+from nmigen import Signal, Module, Elaboratable
+from nmigen.back.pysim import Simulator, Delay
+from nmigen.cli import rtlil
+
+from ieee754.part.partsig import PartitionedSignal
+from ieee754.part_mux.part_mux import PMux
+
+
+# XXX this is for coriolis2 experimentation
+class TestAddMod2(Elaboratable):
+ def __init__(self, width, partpoints):
+ self.partpoints = partpoints
+ self.a = PartitionedSignal(partpoints, width)
+ self.b = PartitionedSignal(partpoints, width)
+ self.bsig = Signal(width)
+ self.add_output = Signal(width)
+ self.ls_output = Signal(width) # left shift
+ self.ls_scal_output = Signal(width) # left shift
+ self.sub_output = Signal(width)
+ self.eq_output = Signal(len(partpoints)+1)
+ self.gt_output = Signal(len(partpoints)+1)
+ self.ge_output = Signal(len(partpoints)+1)
+ self.ne_output = Signal(len(partpoints)+1)
+ self.lt_output = Signal(len(partpoints)+1)
+ self.le_output = Signal(len(partpoints)+1)
+ self.mux_sel = Signal(len(partpoints)+1)
+ self.mux_out = Signal(width)
+ self.carry_in = Signal(len(partpoints)+1)
+ self.add_carry_out = Signal(len(partpoints)+1)
+ self.sub_carry_out = Signal(len(partpoints)+1)
+ self.neg_output = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
+ self.a.set_module(m)
+ self.b.set_module(m)
+ # compares
+ sync += self.lt_output.eq(self.a < self.b)
+ sync += self.ne_output.eq(self.a != self.b)
+ sync += self.le_output.eq(self.a <= self.b)
+ sync += self.gt_output.eq(self.a > self.b)
+ sync += self.eq_output.eq(self.a == self.b)
+ sync += self.ge_output.eq(self.a >= self.b)
+ # add
+ add_out, add_carry = self.a.add_op(self.a, self.b,
+ self.carry_in)
+ sync += self.add_output.eq(add_out)
+ sync += self.add_carry_out.eq(add_carry)
+ # sub
+ sub_out, sub_carry = self.a.sub_op(self.a, self.b,
+ self.carry_in)
+ sync += self.sub_output.eq(sub_out)
+ sync += self.sub_carry_out.eq(sub_carry)
+ # neg
+ sync += self.neg_output.eq(-self.a)
+ # left shift
+ sync += self.ls_output.eq(self.a << self.b)
+ ppts = self.partpoints
+ sync += self.mux_out.eq(PMux(m, ppts, self.mux_sel, self.a, self.b))
+ # scalar left shift
+ comb += self.bsig.eq(self.b.sig)
+ sync += self.ls_scal_output.eq(self.a << self.bsig)
+
+ return m
+
+