whoops cant output .il at the moment

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index ee18ff2187ee504adfa161b7cc6d0cdccffb5e6b..22d2f20a025bd62d1ffd116c1b0118b8aad3f476 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -18,9 +18,11 @@ class SinCosTestCase(FHDLTestCase):
         m.submodules.dut = dut = FPCordicBasePipe(pspec)
 
         # write out module (useful for seeing what's going on)
-        vl = rtlil.convert(dut, ports=dut.ports())
-        with open("test_cordic_pipe_sin_cos.il", "w") as f:
-            f.write(vl)
+        # XXX WHOOPS can't do this at the moment, need to track down
+        # an issue in the ports
+        # vl = rtlil.convert(dut, ports=dut.ports())
+        # with open("test_cordic_pipe_sin_cos.il", "w") as f:
+        #     f.write(vl)
 
         z = Signal(dut.p.data_i.a.shape())
         z_valid = Signal()