class CacheRam(Elaboratable):
- def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False):
+ def __init__(self, ROW_BITS=16, WIDTH = 64, TRACE=True, ADD_BUF=False,
+ ram_num=0):
+ self.ram_num = ram_num # for debug reporting
self.ROW_BITS = ROW_BITS
self.WIDTH = WIDTH
self.TRACE = TRACE
with m.If(TRACE):
with m.If(self.wr_sel.bool()):
- sync += Display( "write a: %x sel: %x dat: %x",
- self.wr_addr, self.wr_sel, self.wr_data)
+ sync += Display( "write ramno %d a: %%x "
+ "sel: %%x dat: %%x" % self.ram_num,
+ self.wr_addr,
+ self.wr_sel, self.wr_data)
for i in range(WIDTH//8):
lbit = i * 8;
mbit = lbit + 8;
with m.If(self.rd_en):
sync += rd_data0.eq(ram[self.rd_addr])
if TRACE:
- sync += Display("read a: %x dat: %x",
+ sync += Display("read ramno %d a: %%x dat: %%x" % self.ram_num,
self.rd_addr, ram[self.rd_addr])
pass
wr_sel_m = Signal(ROW_SIZE)
_d_out = Signal(WB_DATA_BITS, name="dout_%d" % i) # cache_row_t
- way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True)
+ way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True, ram_num=i)
setattr(m.submodules, "cacheram_%d" % i, way)
comb += way.rd_en.eq(do_read)