add ternlogi to shiftrot

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 15a4a0d5bbb6559becf96aaaf1beaba8962857b3..b8ec704199a800c6df652524612581e07d885bb2 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -10,7 +10,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
                                         ShiftRotInputData)
-from ieee754.part.partsig import SimdSignal
+from nmutil.lut import BitwiseLut
 from openpower.decoder.power_enums import MicrOp
 from soc.fu.shift_rot.rotator import Rotator
 
@@ -36,6 +36,12 @@ class ShiftRotMainStage(PipeModBase):
         op = self.i.ctx.op
         o = self.o.o
 
+        bitwise_lut = BitwiseLut(input_count=3, width=64)
+        m.submodules.bitwise_lut = bitwise_lut
+        comb += bitwise_lut.inputs[0].eq(self.i.rb)
+        comb += bitwise_lut.inputs[1].eq(self.i.ra)
+        comb += bitwise_lut.inputs[2].eq(self.i.rc)
+
         # NOTE: the sh field immediate is read in by PowerDecode2
         # (actually DecodeRB), whereupon by way of rb "immediate" mode
         # it ends up in self.i.rb.
@@ -65,6 +71,10 @@ class ShiftRotMainStage(PipeModBase):
 
         comb += o.ok.eq(1)  # defaults to enabled
 
+        # outputs from the microwatt rotator module
+        comb += [o.data.eq(rotator.result_o),
+                 self.o.xer_ca.data.eq(Repl(rotator.carry_out_o, 2))]
+
         # instruction rotate type
         mode = Signal(4, reset_less=True)
         with m.Switch(op.insn_type):
@@ -80,6 +90,12 @@ class ShiftRotMainStage(PipeModBase):
                 comb += mode.eq(0b0100)  # clear R
             with m.Case(MicrOp.OP_EXTSWSLI):
                 comb += mode.eq(0b1000)  # L-ext
+            with m.Case(MicrOp.OP_TERNLOG):
+                # TODO: this only works for ternaryi, change to get lut value
+                # from register when we implement other variants
+                comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
+                comb += o.data.eq(bitwise_lut.output)
+                comb += self.o.xer_ca.data.eq(0)
             with m.Default():
                 comb += o.ok.eq(0)  # otherwise disable
 
@@ -88,10 +104,6 @@ class ShiftRotMainStage(PipeModBase):
                     rotator.clear_right,
                     rotator.sign_ext_rs).eq(mode)
 
-        # outputs from the microwatt rotator module
-        comb += [o.data.eq(rotator.result_o),
-                 self.o.xer_ca.data.eq(Repl(rotator.carry_out_o, 2))]
-
         ###### sticky overflow and context, both pass-through #####
 
         comb += self.o.xer_so.data.eq(self.i.xer_so)