mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi?id=450#c54

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index df9af18c05d930022a59eee04f3e355281a60aa3..7668234ae007571f9c65cd8448ab0b51d3cfc809 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -502,7 +502,7 @@ class MMU1(Elaboratable):
 #                   v.priv := l_in.priv;
                     comb += v.addr.eq(l_in.addr
                     comb += v.iside.eq(l_in.iside)
-                    comb += v.store.eq(~(l_in.load | l_in.siside))
+                    comb += v.store.eq(~(l_in.load | l_in.iside))
 #                   if l_in.tlbie = '1' then
                     with m.If(l_in.tlbie):
 #                       -- Invalidate all iTLB/dTLB entries for