| 2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
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| 2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
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commit | commitdiff | tree |
| 2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...
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| 2020-08-13 |
Cole Poirier | dcache.py add initial imports
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| 2020-08-13 |
Cole Poirier | mem_types.py add more types from common.vhdl
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| 2020-08-13 |
Cole Poirier | move memory related types from mmu.py into new file...
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| 2020-08-13 |
Cole Poirier | Initial commit of translation of microwatt dcache.vhdl...
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| 2020-08-12 |
Cole Poirier | mmu.py add skeleton sim and test functions from regfile...
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| 2020-08-12 |
Cole Poirier | Delete unnecessary mmu dir, move mmu.py out of mmu...
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| 2020-08-12 |
Cole Poirier | Revert "Remove mmu dir and associated mmu/test/ dir...
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commit | commitdiff | tree |
| 2020-08-12 |
Cole Poirier | Remove mmu dir and associated mmu/test/ dir
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| 2020-08-12 |
Cole Poirier | Remove rst signals, fix len of hex Consts, fix variable...
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| 2020-08-12 |
Cole Poirier | Create dir experiment/mmu then mmu/test with skeleton...
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| 2020-08-12 |
Cole Poirier | mmu.py add RecordObject classes from common.vhdl input...
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| 2020-08-12 |
Cole Poirier | mmu.py remove TODOs for vhdl (others => '0') as they...
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| 2020-08-12 |
Cole Poirier | mmu.py fix or(block of logic) to be (block of logic...
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| 2020-08-12 |
Cole Poirier | mmu.py fix length of hex const https://bugs.libre-soc...
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| 2020-08-12 |
Cole Poirier | mmu.py remove class AddrShifter
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commit | commitdiff | tree |
| 2020-08-12 |
Cole Poirier | Fix typo in mmu.py
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| 2020-08-11 |
Cole Poirier | mmu.py fix formatting, use Cat() where '&' in mmu.vhdl
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commit | commitdiff | tree |
| 2020-08-10 |
Cole Poirier | Fix typo in mmu.py
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commit | commitdiff | tree |
| 2020-08-10 |
Cole Poirier | Fix typo mmu.py
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| 2020-08-10 |
Cole Poirier | Global search and replace (^, |), fixes bug 450 comment...
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| 2020-08-10 |
Cole Poirier | fix bug 450 comments 8,9,10
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| 2020-08-10 |
Cole Poirier | Fix bug 450 comment 7
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| 2020-08-10 |
Cole Poirier | mmu.py add line I forgot to translate from mmu.vhdl
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| 2020-08-10 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc
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| 2020-08-10 |
Cole Poirier | mmu.vhdl translation to mmu.py 95 percent complete
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commit | commitdiff | tree |
| 2020-08-08 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc
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commit | commitdiff | tree |
| 2020-08-08 |
Cole Poirier | Update test case_mulli
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| 2020-08-07 |
Cole Poirier | Update test case_mulli
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commit | commitdiff | tree |
| 2020-08-07 |
Cole Poirier | Update test case_mulli, I think it now works correctly
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commit | commitdiff | tree |
| 2020-08-07 |
Cole Poirier | Update mulli to try to use immediates not registers
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Fix mmu.py formatting
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Fix formatting
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Initial commit of translation of microwatt mmu.vhdl...
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Update test case_all_rb_close_to_ov
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Update test case_all_rb_close_to_ov
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commit | commitdiff | tree |
| 2020-08-06 |
Cole Poirier | Add special test for case_mulli, apply autopep8
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Add test case_all_rb_close_to_ov
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Remove mulli from instrs in test case_all*, add TODO...
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| 2020-08-05 |
Cole Poirier | Add new test_values to tests case_all and case_all_rb_randint
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Add second case_all test where rb is randint
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Remove madd* isns, added madd* isns test TODO
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc
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commit | commitdiff | tree |
| 2020-08-05 |
Cole Poirier | Fix pysim deprecation warning
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| 2020-08-05 |
Cole Poirier | Add case_all to MUL unit tests, remove duplicate test...
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| 2020-07-24 |
Cole Poirier | Update libreriscv/HDL_workflow with instructions how...
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| 2020-07-23 |
Cole Poirier | Update libreriscv HDL_workflow/coriolis2
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| 2020-06-20 |
colepoirier | Add code, commented-out, for TRAP so as to not break...
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commit | commitdiff | tree |
| 2020-06-08 |
colepoirier | Fix spelling
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commit | commitdiff | tree |
| 2020-06-07 |
colepoirier | Add TrapMainStage.trap() convenience function to set...
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commit | commitdiff | tree |
| 2020-06-07 |
colepoirier | Add back test cases to cookie-cut from for fu/trap...
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commit | commitdiff | tree |
| 2020-06-07 |
colepoirier | Fix missing 'comb +='
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commit | commitdiff | tree |
| 2020-06-05 |
colepoirier | Added skeleton fu/trap/test/test_pipe_caller using
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commit | commitdiff | tree |
| 2020-06-05 |
colepoirier | Add trap_input_data.py for fu/trap, cookie-cut from
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| 2020-06-05 |
colepoirier | Made small changes to fu/trap/main_stage to bring nmigen...
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| 2020-06-04 |
colepoirier | Use a_i and b_i convenience variables instead of a...
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commit | commitdiff | tree |
| 2020-06-04 |
colepoirier | Undo damage done by deleting VHDL microwatt comments,
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commit | commitdiff | tree |
| 2020-06-03 |
colepoirier | Fixed missing nia.ok.eq(1) in OP_RFID
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commit | commitdiff | tree |
| 2020-06-03 |
colepoirier | Fixed merge conflict by using remote changes
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commit | commitdiff | tree |
| 2020-06-03 |
colepoirier | Fixed OP_RFID and OP_SC in fu/trap/main_stage
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commit | commitdiff | tree |
| 2020-06-03 |
colepoirier | Attempted to fix OP_RFID in TRAP pipeline
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commit | commitdiff | tree |
| 2020-06-02 |
colepoirier | Implement TRAP instructions OP_RFID and OP_SC
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commit | commitdiff | tree |
| 2020-05-28 |
colepoirier | Added Initial() synchronous check with draft truth
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commit | commitdiff | tree |
| 2020-05-28 |
colepoirier | Add sync Assert for _wrports 'wen' signal in proof_regfile...
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commit | commitdiff | tree |
| 2020-05-27 |
colepoirier | Derive proof_regfile Driver from regfile.Register(...
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commit | commitdiff | tree |
| 2020-05-27 |
colepoirier | Fix indentation of regfile/formal/proof_regfile.py
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commit | commitdiff | tree |
| 2020-05-27 |
colepoirier | First commit of proof of regfile, not working yet
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commit | commitdiff | tree |
| 2020-05-26 |
colepoirier | First attempt at implementing block access rd and wr...
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| 2020-05-23 |
colepoirier | Added branch and shift_rot imports to fu/compunits...
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| 2020-05-20 |
colepoirier | Added OP_BPERMD to fu/logical pipeline, with test
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| 2020-05-19 |
colepoirier | Renamed bperm files in fu/logical and fu/logical formal...
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commit | commitdiff | tree |
| 2020-05-19 |
colepoirier | Added luke's suggested code to cover all 3 assertions...
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commit | commitdiff | tree |
| 2020-05-18 |
colepoirier | Added 2nd of 3 assertions for proof_bperm.py, currently...
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commit | commitdiff | tree |
| 2020-05-17 |
colepoirier | Removed extraneous variable from 'ports=[..]' of main...
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commit | commitdiff | tree |
| 2020-05-17 |
colepoirier | Applied PEP8 formatting to bperm.py
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commit | commitdiff | tree |
| 2020-05-16 |
colepoirier | Removed from bperm.py extraneous creation of temporary...
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commit | commitdiff | tree |
| 2020-05-16 |
colepoirier | Made creation of Array of Signals in bperm.py more...
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commit | commitdiff | tree |
| 2020-05-16 |
colepoirier | Implemented luke's TODOs by adding 'reset_less' to...
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commit | commitdiff | tree |
| 2020-05-16 |
colepoirier | Added working bperm.py, but is too gate heavy, as well...
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