Skip vector test case, and add a scalar case

Even if the prefix is a no-op, it will at least test the fetch unit.

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index c8e985247d4dfd9e6366662bdedc8ee69f020e58..ad692243089e38f1f7dd08be0941b727bb1cb282 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -1,4 +1,4 @@
-from soc.fu.test.common import TestAccumulatorBase
+from soc.fu.test.common import (TestAccumulatorBase, skip_case)
 from soc.config.endian import bigendian
 from soc.simulator.program import Program
 from soc.decoder.isa.caller import SVP64State
@@ -7,6 +7,7 @@ from soc.sv.trans.svp64 import SVP64Asm
 
 class SVP64ALUTestCase(TestAccumulatorBase):
 
+    @skip_case("VL hardware loop is not yet implemented")
     def case_1_sv_add(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
@@ -14,11 +15,14 @@ class SVP64ALUTestCase(TestAccumulatorBase):
         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)
+
+        # initial values in GPR regfile
         initial_regs = [0] * 32
         initial_regs[9] = 0x1234
         initial_regs[10] = 0x1111
         initial_regs[5] = 0x4321
         initial_regs[6] = 0x2223
+        # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
         svstate.vl[0:7] = 2  # VL
         svstate.maxvl[0:7] = 2  # MAXVL
@@ -26,3 +30,23 @@ class SVP64ALUTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
+
+    def case_2_sv_add_scalar(self):
+        # adds:
+        #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
+        isa = SVP64Asm(['sv.add 1, 5, 9'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[9] = 0x1234
+        initial_regs[5] = 0x4321
+        svstate = SVP64State()
+        # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
+        svstate.vl[0:7] = 1  # VL
+        svstate.maxvl[0:7] = 1  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)