add extra (test dummy stage in trap to see if combinatorial latency is reduced

diff --git a/src/soc/fu/trap/pipeline.py b/src/soc/fu/trap/pipeline.py
index 1fa867b52b456b4e98cbbb01372a5f284b019e25..c27a0e566295ce00f5cf839db64e24b9d43c2e2f 100644 (file)
--- a/src/soc/fu/trap/pipeline.py
+++ b/src/soc/fu/trap/pipeline.py
@@ -1,6 +1,27 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
 from soc.fu.trap.main_stage import TrapMainStage
+from soc.fu.trap.pipe_data import TrapOutputData
+from nmutil.pipemodbase import PipeModBase
+from nmigen import Module
+
+# gives a 1-clock delay to stop combinatorial link between in and out
+class DummyTrapStage(PipeModBase):
+    def __init__(self, pspec): super().__init__(pspec, "dummy")
+    def ispec(self): return TrapOutputData(self.pspec)
+    def ospec(self): return TrapOutputData(self.pspec)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.o.eq(self.i) # pass-through output
+        return m
+
+
+class TrapDummyStages(PipeModBaseChain):
+    def get_chain(self):
+        dummy = DummyTrapStage(self.pspec)
+        return [dummy]
+
 
 class TrapStages(PipeModBaseChain):
     def get_chain(self):
@@ -13,10 +34,12 @@ class TrapBasePipe(ControlBase):
         ControlBase.__init__(self)
         self.pspec = pspec
         self.pipe1 = TrapStages(pspec)
-        self._eqs = self.connect([self.pipe1])
+        self.pipe2 = TrapDummyStages(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.pipe1 = self.pipe1
+        m.submodules.pipe2 = self.pipe2
         m.d.comb += self._eqs
         return m