radv: set LDS TCS size at shaders creation for GFX9+

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e598ddbabdda41ff8b5a086d1de4c8a7c0a8d3ae..bc1b1c1253b98db0ba5cf028779d47c9e6c34a66 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4054,20 +4054,11 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
 static void
 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
                             struct radv_pipeline *pipeline,
-                            struct radv_shader_variant *shader,
-                            const struct radv_tessellation_state *tess)
+                            struct radv_shader_variant *shader)
 {
        uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 
        if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
-               unsigned hs_rsrc2 = shader->config.rsrc2;
-
-               if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
-                       hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->num_lds_blocks);
-               } else {
-                       hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->num_lds_blocks);
-               }
-
                if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
                        radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
                        radeon_emit(cs, va >> 8);
@@ -4080,7 +4071,7 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
 
                radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
                radeon_emit(cs, shader->config.rsrc1);
-               radeon_emit(cs, hs_rsrc2);
+               radeon_emit(cs, shader->config.rsrc2);
        } else {
                radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
                radeon_emit(cs, va >> 8);
@@ -4136,7 +4127,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
                        radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
        }
 
-       radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
+       radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
 
        radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
                               tess->tf_param);

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 11f8fbec7cf46ea425648adeba3739f755f195b9..a055d867138429d2be53a270b62efb88899a06e7 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -813,8 +813,10 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
                         */
                        if (pdevice->rad_info.chip_class >= GFX10) {
                                vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
+                               config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
                        } else {
                                vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
+                               config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
                        }
                } else {
                        config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);