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enable HFNS in adder
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 18:27:51 +0000 (18:27 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 18:27:51 +0000 (18:27 +0000)
experiments10_verilog/freepdk_c4m45/doDesign.py patch | blob | history

diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py
index 4acedc7a4aded19247b2ea86300c9d2dfec80fc5..3de3798b48ec46ab49538157beee8437e2bc2550 100644 (file)
--- a/experiments10_verilog/freepdk_c4m45/doDesign.py
+++ b/experiments10_verilog/freepdk_c4m45/doDesign.py
@@ -84,7 +84,7 @@ def scriptMain ( **kw ):
         adderConf.editor = editor
         adderConf.useSpares = True
         adderConf.useClockTree = True
-        #adderConf.useHFNS = True
+        adderConf.useHFNS = True
         adderConf.bColumns = 2
         adderConf.bRows = 2
         adderConf.chipConf.name = 'chip'