experiments10_verilog/freepdk_c4m45/doDesign.py

   1
   2 from   __future__ import print_function
   3 import sys
   4 import traceback
   5 import CRL
   6 import helpers
   7 from   helpers.io import ErrorMessage
   8 from   helpers.io import WarningMessage
   9 from   helpers    import trace
  10 from   helpers.overlay import UpdateSession
  11 from   helpers    import l, u, n
  12 import plugins
  13 from   Hurricane  import DbU, Box
  14 from   plugins.alpha.block.block         import Block
  15 from   plugins.alpha.block.configuration import IoPin
  16 from   plugins.alpha.block.configuration import GaugeConf
  17 from   plugins.alpha.core2chip.libresocio import CoreToChip
  18 from   plugins.alpha.chip.configuration  import ChipConf
  19 from   plugins.alpha.chip.chip           import Chip
  20
  21
  22 af = CRL.AllianceFramework.get()
  23
  24 def rsetAbutmentBox ( cell, ab ):
  25     for occurrence in cell.getNonTerminalNetlistInstanceOccurrences():
  26         masterCell = occurrence.getEntity().getMasterCell()
  27         masterCell.setAbutmentBox( ab )
  28
  29
  30 def scriptMain ( **kw ):
  31     """The mandatory function to be called by Coriolis CGT/Unicorn."""
  32     global af
  33     rvalue = True
  34     coreSize   = u(3*90.0)
  35     chipBorder = u(4*214.0 + 10*13.0)
  36     try:
  37         helpers.setTraceLevel( 550 )
  38         cell, editor = plugins.kwParseMain( **kw )
  39         cell = af.getCell( 'add', CRL.Catalog.State.Logical )
  40         if cell is None:
  41             print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
  42             sys.exit( 1 )
  43         if editor: editor.setCell( cell )
  44         #     Spec:
  45         # | Side        | Pos | Instance     | Pad net   |Core net | Direction |
  46         ioPadsSpec = [
  47            (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'     )
  48          , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'     )
  49          , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
  50          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
  51          , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
  52          , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
  53          , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms'    , 'jtag_tms'      )
  54          , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo'    , 'jtag_tdo'      )
  55          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
  56          , (IoPin.EAST , None, 'p_sys_clk'  , 'sys_clk'    , 'sys_clk'      )
  57          , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck'    , 'jtag_tck'      )
  58          , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi'    , 'jtag_tdi'      )
  59          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
  60          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
  61          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
  62          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
  63          , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
  64          , (IoPin.NORTH, None, 'p_sys_rst'  , 'sys_rst'    , 'sys_rst'      )
  65          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
  66          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
  67          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
  68          , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'     )
  69          , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'     )
  70          , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'     )
  71         ]
  72         adderConf = ChipConf( cell, ioPads=ioPadsSpec )
  73         adderConf.cfg.etesian.bloat = 'nsxlib'
  74         adderConf.cfg.etesian.uniformDensity = True
  75         adderConf.cfg.etesian.aspectRatio = 1.0
  76         adderConf.cfg.etesian.spaceMargin = 0.05
  77         adderConf.cfg.anabatic.searchHalo = 2
  78         adderConf.cfg.anabatic.globalIterations = 20
  79         adderConf.cfg.anabatic.topRoutingLayer = 'METAL5'
  80         adderConf.cfg.block.spareSide = u(7*13)
  81         #adderConf.cfg.chip.padCoreSide = 'North'
  82         adderConf.cfg.chip.supplyRailWidth = u(35)
  83         adderConf.cfg.chip.supplyRailPitch = u(90)
  84         adderConf.editor = editor
  85         adderConf.useSpares = True
  86         adderConf.useClockTree = True
  87         adderConf.useHFNS = True
  88         adderConf.bColumns = 2
  89         adderConf.bRows = 2
  90         adderConf.chipConf.name = 'chip'
  91         adderConf.chipConf.ioPadGauge = 'LibreSOCIO'
  92         adderConf.coreSize = (coreSize, coreSize)
  93         adderConf.chipSize = (coreSize + chipBorder, coreSize + chipBorder)
  94         adderToChip = CoreToChip( adderConf )
  95         adderToChip.buildChip()
  96
  97         with UpdateSession():
  98             sliceHeight = adderConf.sliceHeight
  99             coreAb      = Box( 0, 0, coreSize, coreSize )
 100             rsetAbutmentBox( cell, coreAb )
 101
 102         chipBuilder = Chip( adderConf )
 103         chipBuilder.doChipFloorplan()
 104
 105         rvalue = chipBuilder.doPnR()
 106         chipBuilder.save()
 107         CRL.Gds.save(adderConf.chip)
 108
 109     except Exception, e:
 110         helpers.io.catch( e )
 111         rvalue = False
 112     sys.stdout.flush()
 113     sys.stderr.flush()
 114     return rvalue