add auto-generation of out2 column in SVP64RM

needed for PowerDecoder2 as well as microwatt svp64 vhdl generation

diff --git a/Makefile b/Makefile
index 820ca3f11dabc1f9318e4ccbe57001f6acc1c937..28b8f38b1f2e7189b4e62b4c514691424e5957d2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -16,6 +16,9 @@ install: develop mkpinmux
 pywriter:
        python3 src/soc/decoder/pseudo/pywriter.py
 
+svanalysis:
+       python3 libreriscv/openpower/sv_analysis.py
+
 develop:
        python3 setup.py develop # yes, develop, not install
        python3 src/soc/decoder/pseudo/pywriter.py

diff --git a/libreriscv b/libreriscv
index 1267f463aa6da5f0062961657fda303e8efc70f3..d36702671ee1711e7dc79dc292b400e52903ab27 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 1267f463aa6da5f0062961657fda303e8efc70f3
+Subproject commit d36702671ee1711e7dc79dc292b400e52903ab27

diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py
index bc712af20928f8284221f634a0a9d7a987b0f438..26e782b390b2bfd0c507089e66de541ea00c0bad 100644 (file)
--- a/src/soc/decoder/power_svp64.py
+++ b/src/soc/decoder/power_svp64.py
@@ -87,12 +87,16 @@ class SVP64RM:
 
         # now add the RM fields (for each instruction)
         for entry in v30b:
+            # *sigh* create extra field "out2" based on LD/ST update
+            entry['out2'] = 'NONE'
+            if entry['upd'] == '1':
+                entry['out2'] = 'RA'
             # dummy (blank) fields, first
             entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
                           'EXTRA3': '0',
                           'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
                           'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
-            for fname in ['in1', 'in2', 'in3', 'out']:
+            for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
                 entry['sv_%s' % fname] = 'NONE'
 
             # is this SVP64-augmented?
@@ -113,16 +117,16 @@ class SVP64RM:
             dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 
             # now examine in1/2/3/out, create sv_in1/2/3/out
-            for fname in ['in1', 'in2', 'in3', 'out']:
+            for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
                 regfield = entry[fname]
                 extra_index = None
                 if regfield == 'RA_OR_ZERO':
                     regfield = 'RA'
                 print (asmcode, regfield, fname, svp64_dest, svp64_src)
                 # find the reg in the SVP64 extra map
-                if (fname == 'out' and regfield in svp64_dest):
+                if (fname in ['out', 'out2'] and regfield in svp64_dest):
                     extra_index = svp64_dest[regfield]
-                if (fname != 'out' and regfield in svp64_src):
+                if (fname not in ['out', 'out2'] and regfield in svp64_src):
                     extra_index = svp64_src[regfield]
                 # ta-daa, we know in1/2/3/out's bit-offset
                 if extra_index is not None:
@@ -157,9 +161,10 @@ class SVP64RM:
 
 if __name__ == '__main__':
     isa = SVP64RM()
-    minor_30 = isa.get_svp64_csv("minor_30.csv")
-    for entry in minor_30:
-        print (entry)
+    minor_31 = isa.get_svp64_csv("minor_31.csv")
+    for entry in minor_31:
+        if entry['comment'].startswith('ldu'):
+            print ("entry", entry)
     minor_19 = isa.get_svp64_csv("minor_19.csv")
     for entry in minor_19:
         if entry['comment'].startswith('cr'):