fix more imports

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index b140aa20d300b4b837552a8e124928b2d8efd2f8..4f7eb06eacc04437c9b15bb4364973624351a252 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -1,8 +1,8 @@
-from nmigen import Elaboratable, Module, Signal, Record
+from nmigen import Elaboratable, Module, Signal, Record, Const, Mux
 from nmigen.utils import log2_int
 
 from ..cache import L1Cache
-from ..wishbone import wishbone_layout
+from ..wishbone import wishbone_layout, WishboneArbiter, Cycle
 
 
 __all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"]

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index ac2a042685744ffa2e3b191b8412f2bc3e359e7f..3469851446d7b42ae7af74520bcf40559d3e734c 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -1,10 +1,10 @@
-from nmigen import Elaboratable, Module, Signal, Record, Cat
+from nmigen import Elaboratable, Module, Signal, Record, Cat, Const, Mux
 from nmigen.utils import log2_int
 from nmigen.lib.fifo import SyncFIFO
 
 from ..cache import L1Cache
 from ..isa import Funct3
-from ..wishbone import wishbone_layout
+from ..wishbone import wishbone_layout, WishboneArbiter, Cycle
 
 
 __all__ = ["DataSelector", "LoadStoreUnitInterface", "BareLoadStoreUnit", "CachedLoadStoreUnit"]