order of XER so/ca wrong way round from regspec

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index c765af1d3d2ffa7bac0ffb490695656fcb6ea5db..22c0ee48ff21732041c1810ad930c714fe14b49c 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -92,9 +92,9 @@ def set_operand(cu, dec2, sim):
 def set_extra_cu_inputs(cu, dec2, sim):
     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-    yield from set_cu_input(cu, 2, carry | (carry32<<1))
+    yield from set_cu_input(cu, 3, carry | (carry32<<1))
     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-    yield from set_cu_input(cu, 3, so)
+    yield from set_cu_input(cu, 2, so)