syntax error

diff --git a/libreriscv b/libreriscv
index f0f302d80683c9b68fc9b13dac9f590ae1937232..1f4b308f975418595a0858cd37e7e66f2fe7244d 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit f0f302d80683c9b68fc9b13dac9f590ae1937232
+Subproject commit 1f4b308f975418595a0858cd37e7e66f2fe7244d

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index c9938fea3fc8a70b8ca30c7e29bed099059e226d..bd565b0b8b00d2234f9791f4fd975241f15c4059 100755 (executable)
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -29,7 +29,6 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
             sys_clk_freq = sys_clk_freq,
             cpu_type     = "external",
             cpu_cls      = LibreSoC,
-            cpu_variant  = "standardjtag",
             cpu_variant = "standardjtagnoirq",
             #cpu_cls      = Microwatt,
             device       = "LFE5UM",