add dedicated TrapPipeSpec

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 9141a30d2f1d8a9a8e2b1926a981dfae6d4c3516..690f60c016464a2969de1565740cd6e9890bbc75 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -62,8 +62,8 @@ class TrapMainStage(PipeModBase):
         comb += gt_u.eq(a > b)
         comb += equal.eq(a == b)
 
-        # They're in reverse bit order because POWER. Check Book 1,
-        # Appendix C.6 for chart
+        # They're in reverse bit order because POWER.
+        # Check V3.0B Book 1, Appendix C.6 for chart
         trap_bits = Signal(5)
         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
 

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 033f7bb184f1375d31aa221b4eeb55cc0493fdd4..af0e9d7a08bbbb220fd581181a1e19cf10163014 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -2,6 +2,8 @@ from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.alu.pipe_data import IntegerData
 from soc.decoder.power_decoder2 import Data
+from nmutil.dynamicpipe import SimpleHandshakeRedir
+from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 
 
 class TrapInputData(IntegerData):
@@ -52,3 +54,15 @@ class TrapOutputData(IntegerData):
         lst = super().eq(i)
         return lst + [ self.nia.eq(i.nia), self.msr.eq(i.msr),
                       self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]
+
+
+# TODO: replace CompALUOpSubset with CompTrapOpSubset
+class TrapPipeSpec:
+    regspec = (TrapInputData.regspec, TrapOutputData.regspec)
+    opsubsetkls = CompALUOpSubset
+    def __init__(self, id_wid, op_wid):
+        self.id_wid = id_wid
+        self.op_wid = op_wid
+        self.opkls = lambda _: self.opsubsetkls(name="op")
+        self.stage = None
+        self.pipekls = SimpleHandshakeRedir