update comments in issuer.py regarding a 4th FSM

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 477e81a43d9d775ceec73b2d6e1d6607b4519a2f..667347f8eb243a7c43f7bc2137791a8df94604f6 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1007,8 +1007,9 @@ class TestIssuerInternal(Elaboratable):
         # on VL==0
         is_svp64_mode = Signal()
 
-        # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
-        # these are the handshake signals between fetch and decode/execute
+        # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
+        # issue, decode/execute, now joined by "Predicate fetch/calculate".
+        # these are the handshake signals between each
 
         # fetch FSM can run as soon as the PC is valid
         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"