or ``BTE_I`` (target).
"""
- def __init__(self, *, addr_width, data_width, granularity=None, features=frozenset(),
+ def __init__(self, *, addr_width, data_width, granularity=None,
+ features=None,
alignment=0, name=None):
+ if features is None:
+ features = frozenset()
if not isinstance(addr_width, int) or addr_width < 0:
- raise ValueError("Address width must be a non-negative integer, not {!r}"
- .format(addr_width))
+ raise ValueError("Address width must be a non-negative integer, "
+ "not {!r}" .format(addr_width))
if data_width not in (8, 16, 32, 64):
raise ValueError("Data width must be one of 8, 16, 32, 64, not {!r}"
.format(data_width))
if granularity is None:
granularity = data_width
elif granularity not in (8, 16, 32, 64):
- raise ValueError("Granularity must be one of 8, 16, 32, 64, not {!r}"
- .format(granularity))
+ raise ValueError("Granularity must be one of 8, 16, 32, 64, "
+ "not {!r}" .format(granularity))
if granularity > data_width:
- raise ValueError("Granularity {} may not be greater than data width {}"
- .format(granularity, data_width))
+ raise ValueError("Granularity {} may not be greater than data "
+ "width {}" .format(granularity, data_width))
self.addr_width = addr_width
self.data_width = data_width
self.granularity = granularity
granularity_bits = log2_int(data_width // granularity)
self._alignment = alignment
- self.memory_map = MemoryMap(addr_width=max(1, addr_width + granularity_bits),
+ self.memory_map = MemoryMap(addr_width=max(1, addr_width +
+ granularity_bits),
data_width=data_width >> granularity_bits,
alignment=alignment)
@classmethod
def from_pure_record(cls, record):
- """Instantiate a :class:`wishbone.Interface` from a simple :class:`Record`
+ """Instantiate a :class:`wishbone.Interface`
+ from a simple :class:`Record`
"""
if not isinstance(record, Record):
raise TypeError("{!r} is not a Record"
if len(record.dat_w) != len(record.dat_r):
raise AttributeError("Record {!r} has {}-bit long \"dat_w\" "
"but {}-bit long \"dat_r\""
- .format(record, len(record.dat_w), len(record.dat_r)))
+ .format(record, len(record.dat_w),
+ len(record.dat_r)))
data_width = len(record.dat_w)
if data_width % len(record.sel) != 0:
- raise AttributeError("Record {!r} has invalid granularity value because "
+ raise AttributeError("Record {!r} has invalid granularity "
+ "value because "
"its data width is {}-bit long but "
"its \"sel\" is {}-bit long"
.format(record, data_width, len(record.sel)))
See :meth:`MemoryMap.add_resource` for details.
"""
if not isinstance(sub_bus, Interface):
- raise TypeError("Subordinate bus must be an instance of wishbone.Interface, not {!r}"
- .format(sub_bus))
+ raise TypeError("Subordinate bus must be an instance of "
+ "wishbone.Interface, not {!r}" .format(sub_bus))
if sub_bus.granularity > self.bus.granularity:
- raise ValueError("Subordinate bus has granularity {}, which is greater than the "
+ raise ValueError("Subordinate bus has granularity {}, "
+ "which is greater than the "
"decoder granularity {}"
.format(sub_bus.granularity, self.bus.granularity))
if not sparse:
if sub_bus.data_width != self.bus.data_width:
- raise ValueError("Subordinate bus has data width {}, which is not the same as "
- "decoder data width {} (required for dense address translation)"
- .format(sub_bus.data_width, self.bus.data_width))
+ raise ValueError("Subordinate bus has data width {}, "
+ "which is not the same as "
+ "decoder data width {} "
+ "(required for dense address translation)"
+ .format(sub_bus.data_width,
+ self.bus.data_width))
else:
if sub_bus.granularity != sub_bus.data_width:
- raise ValueError("Subordinate bus has data width {}, which is not the same as "
- "subordinate bus granularity {} (required for sparse address "
+ raise ValueError("Subordinate bus has data width {}, "
+ "which is not the same as "
+ "subordinate bus granularity {} "
+ "(required for sparse address "
"translation)"
- .format(sub_bus.data_width, sub_bus.granularity))
+ .format(sub_bus.data_width,
+ sub_bus.granularity))
for opt_output in {"err", "rty", "stall"}:
if hasattr(sub_bus, opt_output) and not hasattr(
self.bus, opt_output):
- raise ValueError("Subordinate bus has optional output {!r}, but the decoder "
+ raise ValueError("Subordinate bus has optional output "
+ "{!r}, but the decoder "
"does not have a corresponding input"
.format(opt_output))
m.d.comb += sub_bus.lock.eq(getattr(self.bus, "lock", 0))
if hasattr(sub_bus, "cti"):
m.d.comb += sub_bus.cti.eq(getattr(self.bus,
- "cti", CycleType.CLASSIC))
+ "cti",
+ CycleType.CLASSIC))
if hasattr(sub_bus, "bte"):
m.d.comb += sub_bus.bte.eq(getattr(self.bus,
- "bte", BurstTypeExt.LINEAR))
+ "bte",
+ BurstTypeExt.LINEAR))
- with m.Case(sub_pat[:-log2_int(self.bus.data_width // self.bus.granularity)]):
+ with m.Case(sub_pat[:-log2_int(self.bus.data_width //
+ self.bus.granularity)]):
m.d.comb += [
sub_bus.cyc.eq(self.bus.cyc),
self.bus.dat_r.eq(sub_bus.dat_r),
be greater than or equal to the granularity of the arbiter.
"""
if not isinstance(itor_bus, Interface):
- raise TypeError("Initiator bus must be an instance of wishbone.Interface, not {!r}"
- .format(itor_bus))
+ raise TypeError("Initiator bus must be an instance of "
+ "wishbone.Interface, not {!r}".format(itor_bus))
if itor_bus.addr_width != self.bus.addr_width:
- raise ValueError("Initiator bus has address width {}, which is not the same as "
+ raise ValueError("Initiator bus has address width {}, "
+ "which is not the same as "
"arbiter address width {}"
.format(itor_bus.addr_width, self.bus.addr_width))
if itor_bus.granularity < self.bus.granularity:
- raise ValueError("Initiator bus has granularity {}, which is lesser than the "
+ raise ValueError("Initiator bus has granularity {}, "
+ "which is lesser than the "
"arbiter granularity {}"
.format(itor_bus.granularity, self.bus.granularity))
if itor_bus.data_width != self.bus.data_width:
- raise ValueError("Initiator bus has data width {}, which is not the same as "
+ raise ValueError("Initiator bus has data width {}, "
+ "which is not the same as "
"arbiter data width {}"
.format(itor_bus.data_width, self.bus.data_width))
for opt_output in {"lock", "cti", "bte"}:
if hasattr(itor_bus, opt_output) and not hasattr(
self.bus, opt_output):
- raise ValueError("Initiator bus has optional output {!r}, but the arbiter "
+ raise ValueError("Initiator bus has optional output {!r}, "
+ "but the arbiter "
"does not have a corresponding input"
.format(opt_output))
This instantiates the following components:
(1) An arbiter (:class:`Arbiter`) controlling access of
multiple MASTERs to the shared bus; and
- (2) A decoder (:class:`Decoder`) specifying which targeted SLAVE is to be accessed
- using address translation on the shared bus.
+ (2) A decoder (:class:`Decoder`) specifying which targeted SLAVE is
+ to be accessed using address translation on the shared bus.
See Section 8.2.3 of Wishbone B4 for implemenation specifications.
if name in kwargs:
arbiter_kwargs[name] = kwargs[name]
self.arbiter = Arbiter(
- addr_width=self.addr_width, data_width=self.data_width, **arbiter_kwargs
+ addr_width=self.addr_width, data_width=self.data_width,
+ **arbiter_kwargs
)
self.arbiter.bus.name = "arbiter_shared"
for itor_bus in self._itors:
for name in ["granularity", "features", "alignment"]:
if name in kwargs:
decoder_kwargs[name] = kwargs[name]
- self.decoder = Decoder(
- addr_width=self.addr_width, data_width=self.data_width, **decoder_kwargs
- )
+ self.decoder = Decoder(addr_width=self.addr_width,
+ data_width=self.data_width,
+ **decoder_kwargs)
self.decoder.bus.name = "decoder_shared"
for item in self._targets:
if isinstance(item, Interface):
self.decoder.add(item[0], addr=item[1])
else:
raise TypeError("Target must be a Wishbone interface, "
- "or a (Wishbone interface, start address) tuple, not {!r}"
+ "or a (Wishbone interface, "
+ "start address) tuple, not {!r}"
.format(item))
def elaborate(self, platform):
projects / nmigen-soc.git / commitdiff