I/O pads reorganisation, 32 per side (except for NORTH).

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index 432213eef840cf698723d94831230f45a8fb6e19..30206b63647c64b170ac2ba3a7996231585a1f66 100644 (file)
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -140,41 +140,47 @@ def scriptMain (**kw):
    #pinmuxFile = './non_generated/litex_pinpads.json'
    #pinmuxFile = './coriolis2/ls180/litex_pinpads.json'
    #ioSpecs.loadFromPinmux( pinmuxFile )
+
    # I/O pads, East side.
     ioPadsSpec  = []
     ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_BEGIN )
+    ioPadsSpec += [ (IoPin.EAST, None, 'sdram_cas_n'   , 'sdram_cas_n'   , 'sdram_cas_n' )
+                  , (IoPin.EAST, None, 'sdram_we_n'    , 'sdram_we_n'    , 'sdram_we_n' )
+                  , (IoPin.EAST, None, 'sdram_cs_n'    , 'sdram_cs_n'    , 'sdram_cs_n' )
+                  ]
     ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_a_{}' , 'sdram_a({})' , 'sdram_a({})'), 13 )
     ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_ba_{}', 'sdram_ba({})', 'sdram_ba({})'), 2 )
-    ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_dm_{}', 'sdram_dm({})', 'sdram_dm({})'),  2 )
-    ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_dq_{}', 'sdram_dq({})', 'sdram_dq_i({})', 'sdram_dq_oe({})', 'sdram_dq_o({})'), range(0,16) )
+    ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'sdram_dm_{}', 'sdram_dm({})', 'sdram_dm({})'), 2 )
+    ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'nc_{}', 'nc({})', 'nc({})'), range(0,2) )
     ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_END )
     ioPadsSpec += [ (IoPin.EAST             , None, 'sys_pll_testout_o', 'sys_pll_testout_o', 'sys_pll_testout_o' )
                   , (IoPin.EAST|IoPin.ANALOG, None, 'sys_pll_vco_o'    , 'sys_pll_vco_o'    , 'sys_pll_vco_o' )
                   ]
-   # I/O pads, West side.
-    ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_BEGIN )
-    ioPadsSpec += doIoPinVector( (IoPin.WEST , None,   'nc_{}', '  nc({})',   'nc({})'), range(36) )
-   #ioPadsSpec += doIoPinVector( (IoPin.WEST , None,  'pwm_{}',  'pwm({})',  'pwm({})'),  2 )
-    ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'eint_{}',  'eint_{}',  'eint_{}'),  3 )
-    ioPadsSpec += [ (IoPin.WEST , None, 'spimaster_clk' , 'spimaster_clk' , 'spimaster_clk' )
-                  , (IoPin.WEST , None, 'spimaster_cs_n', 'spimaster_cs_n', 'spimaster_cs_n' )
-                  , (IoPin.WEST , None, 'spimaster_mosi', 'spimaster_mosi', 'spimaster_mosi' )
-                  , (IoPin.WEST , None, 'spimaster_miso', 'spimaster_miso', 'spimaster_miso' )
-                 #, (IoPin.WEST , None, 'sdcard_cmd'    , 'sdcard_cmd'    , 'sdcard_cmd_i', 'sdcard_cmd_oe', 'sdcard_cmd_o' )
-                 #, (IoPin.WEST , None, 'sdcard_clk'    , 'sdcard_clk'    , 'sdcard_clk' )
-                  ]
-   #ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'sdcard_data_{}', 'sdcard_data({})', 'sdcard_data_i({})', 'sdcard_data_oe', 'sdcard_data_o({})'),  4 )
-    ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_END )
+
    # I/O pads, North side.
     ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_BEGIN )
     ioPadsSpec += [ (IoPin.NORTH, None, 'jtag_tms'     , 'jtag_tms'     , 'jtag_tms' )
                   , (IoPin.NORTH, None, 'jtag_tdi'     , 'jtag_tdi'     , 'jtag_tdi' )
                   , (IoPin.NORTH, None, 'jtag_tdo'     , 'jtag_tdo'     , 'jtag_tdo' )
                   , (IoPin.NORTH, None, 'jtag_tck'     , 'jtag_tck'     , 'jtag_tck' )
-                  , (IoPin.NORTH, None, 'sys_clk'      , 'sys_clk'      , 'sys_clk' )
                   ]
+    ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'nc_{}', 'nc({})', 'nc({})'), range(2,19) )
+    ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'sdram_dq_{}', 'sdram_dq({})', 'sdram_dq_i({})', 'sdram_dq_oe({})', 'sdram_dq_o({})'), range(0,16) )
     ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'sys_clksel_i{}', 'sys_clksel_i({})', 'sys_clksel_i({})'), 2 )
+    ioPadsSpec += [ (IoPin.NORTH, None, 'sys_clk'      , 'sys_clk'      , 'sys_clk' ) ]
     ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_END )
+
+   # I/O pads, West side.
+    ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_BEGIN )
+    ioPadsSpec += doIoPinVector( (IoPin.WEST , None,   'nc_{}', '  nc({})',   'nc({})'), range(19,36) )
+    ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'eint_{}',  'eint_{}',  'eint_{}'),  3 )
+    ioPadsSpec += [ (IoPin.WEST , None, 'spimaster_clk' , 'spimaster_clk' , 'spimaster_clk' )
+                  , (IoPin.WEST , None, 'spimaster_cs_n', 'spimaster_cs_n', 'spimaster_cs_n' )
+                  , (IoPin.WEST , None, 'spimaster_mosi', 'spimaster_mosi', 'spimaster_mosi' )
+                  , (IoPin.WEST , None, 'spimaster_miso', 'spimaster_miso', 'spimaster_miso' )
+                  ]
+    ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_END )
+
    # I/O pads, South side.
     ioPadsSpec += doIoPowerCap( IoPin.SOUTH|IoPin.A_BEGIN )
     ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'gpio_{}', 'gpio({})', 'gpio_i({})', 'gpio_oe({})', 'gpio_o({})'), range(0,16) )
@@ -187,11 +193,9 @@ def scriptMain (**kw):
     ioPadsSpec += [ (IoPin.SOUTH, None, 'sdram_clock'   , 'sdram_clock'   , 'sdram_clock' )
                   , (IoPin.SOUTH, None, 'sdram_cke'     , 'sdram_cke'     , 'sdram_cke' )
                   , (IoPin.SOUTH, None, 'sdram_ras_n'   , 'sdram_ras_n'   , 'sdram_ras_n' )
-                  , (IoPin.SOUTH, None, 'sdram_cas_n'   , 'sdram_cas_n'   , 'sdram_cas_n' )
-                  , (IoPin.SOUTH, None, 'sdram_we_n'    , 'sdram_we_n'    , 'sdram_we_n' )
-                  , (IoPin.SOUTH, None, 'sdram_cs_n'    , 'sdram_cs_n'    , 'sdram_cs_n' )
                   ]
     ioPadsSpec += doIoPowerCap( IoPin.SOUTH|IoPin.A_END )
+
     try:
         cell, editor = plugins.kwParseMain( **kw )
         cell = af.getCell( 'ls180', CRL.Catalog.State.Logical )