get litex sim enabled with 32-bit wishbone bus

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 49e4bd3a022a0b90ad11980896e070700729332e..f0852aebc3abbcd502aba4e2194cadaf2c694c6c 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -5,14 +5,13 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
-CPU_VARIANTS = ["standard"]
+CPU_VARIANTS = ["standard", "standard32"]
 
 
 class LibreSoC(CPU):
     name                 = "libre_soc"
     human_name           = "Libre-SoC"
     variants             = CPU_VARIANTS
-    data_width           = 64
     endianness           = "little"
     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
     linker_output_format = "elf64-powerpcle"
@@ -44,8 +43,14 @@ class LibreSoC(CPU):
         self.variant      = variant
         self.reset        = Signal()
 
+
+        if variant == "standard32":
+            self.data_width           = 32
+            self.dbus = dbus = wishbone.Interface(data_width=32, adr_width=30)
+        else:
+            self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
+            self.data_width           = 64
         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
-        self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
 
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index d451e614d1de55f23a00e73a4a431738127acb70..e2d516bbc13b182dbc2814ce10ec214a9490111d 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -37,12 +37,21 @@ class LibreSoCSim(SoCSDRAM):
         platform     = Platform()
         sys_clk_freq = int(100e6)
 
+        cpu_data_width = 32
+        #cpu_data_width = 64
+
+        if cpu_data_width == 32:
+            variant = "standard32"
+        else:
+            variant = "standard"
+
         # SoCCore -------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
             #bus_data_width           = 64,
+            cpu_variant              = variant,
             csr_data_width            = 32,
             l2_cache_size             = 0,
             uart_name                = "sim",
@@ -201,8 +210,9 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         # limit range of pc for debug reporting
-        self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234))
+        #self.comb += active_dbg.eq((0x5108 <= pc) & (pc <= 0x5234))
         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
+        self.comb += active_dbg.eq(1)
 
         # get the MSR
         self.sync += If(active_dbg & (uptime[0:cyclewid] == 28),

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 3241e20e1c19aa2a457e572333120f103944f5f5..7476380dd6ba061da4b3511a47db65fbcce2491c 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -16,19 +16,22 @@ class LoadStoreUnitInterface:
     def __init__(self, pspec):
         self.pspec = pspec
         self.pspecslave = pspec
-        self.dbus = self.slavebus = Record(make_wb_layout(pspec))
-        print(self.dbus.sel.shape())
-        self.needs_cvt = False
         if (hasattr(pspec, "dmem_test_depth") and
                      isinstance(pspec.wb_data_wid, int) and
                     pspec.wb_data_wid != pspec.reg_wid):
+            self.dbus = Record(make_wb_layout(pspec), name="int_dbus")
             pspecslave = deepcopy(pspec)
             pspecslave.reg_wid = pspec.wb_data_wid
             mask_ratio = (pspec.reg_wid // pspec.wb_data_wid)
             pspecslave.mask_wid = pspec.mask_wid // mask_ratio
             self.pspecslave = pspecslave
-            self.slavebus = Record(make_wb_layout(pspecslave))
+            self.slavebus = Record(make_wb_layout(pspecslave), name="dbus")
             self.needs_cvt = True
+        else:
+            self.needs_cvt = False
+            self.dbus = self.slavebus = Record(make_wb_layout(pspec))
+
+        print(self.dbus.sel.shape())
         self.mask_wid = mask_wid = pspec.mask_wid
         self.addr_wid = addr_wid = pspec.addr_wid
         self.data_wid = data_wid = pspec.reg_wid
@@ -83,7 +86,7 @@ class LoadStoreUnitInterface:
         yield self.m_load_err_o
         yield self.m_store_err_o
         yield self.m_badaddr_o
-        for sig in self.dbus.fields.values():
+        for sig in self.slavebus.fields.values():
             yield sig
 
     def ports(self):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index edcb18bc336281555670534f638f781f4491519b..ad4fd0a9112680cffbe08d3aecdf94dd8e928f81 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -283,7 +283,7 @@ class TestIssuer(Elaboratable):
                                     ] + \
                 list(self.dbg.dmi.ports()) + \
                 list(self.imem.ibus.fields.values()) + \
-                list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
+                list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 
     def ports(self):
         return list(self)

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 9ba52fe628d531f1170739caf464768827d45ac7..f8f52d76949f92f473747f4cb8d8961327517677 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -25,6 +25,8 @@ if __name__ == '__main__':
                          reg_wid=64,
                          # set to 32 for instruction-memory width=32
                          imem_reg_wid=64,
+                         # set to 32 to make data wishbone bus 32-bit
+                         wb_data_wid=32,
                          units=units)
     dut = TestIssuer(pspec)
 

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index ebe810219d4ba3778c3ebc44cbca8394f8c6498a..b461c7310226c1d51bf0c131b8ad6edd8494acad 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -142,6 +142,7 @@ class TestRunner(FHDLTestCase):
                              addr_wid=48,
                              mask_wid=8,
                              imem_reg_wid=64,
+                             #wb_data_width=32,
                              reg_wid=64)
         m.submodules.issuer = issuer = TestIssuer(pspec)
         imem = issuer.imem._get_memory()