remove sram4k wishbone bte/cti in litex interconnect

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 189216e241b0ec5fbd51a3bce826edc376f11c5e..aa178c35c712eefe76cb9bbc0ea29263ea948023 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -268,7 +268,8 @@ class LibreSoC(CPU):
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
         if "sram4k" in variant or variant == 'ls180':
             for i, sram in enumerate(srams):
-                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i,
+                                                     sram, simple=True))
 
         # and set ibus advanced tags to zero (disable)
         self.cpu_params['i_ibus__cti'] = 0