add code-comments, link to in-order core

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 9be51cc3f6a9e67e309b99eda503cd6288ea8eb6..de1d2d68828a10d1788be569d5db26974e2d5323 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -17,6 +17,8 @@ the brain-dead part of this module is that even though there is no
 conflict of access, regfile read/write hazards are *not* analysed,
 and consequently it is safer to wait for the Function Unit to complete
 before allowing a new instruction to proceed.
+(update: actually this is being added now:
+https://bugs.libre-soc.org/show_bug.cgi?id=737)
 """
 
 from nmigen import (Elaboratable, Module, Signal, ResetSignal, Cat, Mux,