3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
30 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
31 from openpower
.sv
.svp64
import SVP64Rec
33 from nmutil
.picker
import PriorityPicker
34 from nmutil
.util
import treereduce
35 from nmutil
.singlepipe
import ControlBase
37 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
38 from soc
.regfile
.regfiles
import RegFiles
39 from openpower
.decoder
.power_decoder2
import get_rdflags
40 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
41 from soc
.config
.test
.test_loadstore
import TestMemPspec
42 from openpower
.decoder
.power_enums
import MicrOp
, Function
43 from soc
.simple
.core_data
import CoreInput
, CoreOutput
45 from collections
import defaultdict
, namedtuple
48 from nmutil
.util
import rising_edge
50 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
51 ByRegSpec
= namedtuple("ByRegSpec", ["rdport", "wrport", "read",
52 "write", "wid", "specs"])
54 # helper function for reducing a list of signals down to a parallel
56 def ortreereduce(tree
, attr
="o_data"):
57 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
60 def ortreereduce_sig(tree
):
61 return treereduce(tree
, operator
.or_
, lambda x
: x
)
64 # helper function to place full regs declarations first
65 def sort_fuspecs(fuspecs
):
67 for (regname
, fspec
) in fuspecs
.items():
68 if regname
.startswith("full"):
69 res
.append((regname
, fspec
))
70 for (regname
, fspec
) in fuspecs
.items():
71 if not regname
.startswith("full"):
72 res
.append((regname
, fspec
))
73 return res
# enumerate(res)
76 # derive from ControlBase rather than have a separate Stage instance,
77 # this is simpler to do
78 class NonProductionCore(ControlBase
):
79 def __init__(self
, pspec
):
82 # test is SVP64 is to be enabled
83 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
85 # test to see if regfile ports should be reduced
86 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
87 (pspec
.regreduce
== True))
89 # test to see if overlapping of instructions is allowed
90 # (not normally enabled for TestIssuer FSM but useful for checking
91 # the bitvector hazard detection, before doing In-Order)
92 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
93 (pspec
.allow_overlap
== True))
96 self
.make_hazard_vecs
= True
97 self
.core_type
= "fsm"
98 if hasattr(pspec
, "core_type"):
99 self
.core_type
= pspec
.core_type
101 super().__init
__(stage
=self
)
103 # single LD/ST funnel for memory access
104 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
107 # function units (only one each)
108 # only include mmu if enabled in pspec
109 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
111 # link LoadStore1 into MMU
112 mmu
= self
.fus
.get_fu('mmu0')
113 print ("core pspec", pspec
.ldst_ifacetype
)
114 print ("core mmu", mmu
)
116 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
117 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
119 # register files (yes plural)
120 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
122 # set up input and output: unusual requirement to set data directly
123 # (due to the way that the core is set up in a different domain,
124 # see TestIssuer.setup_peripherals
125 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
126 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
128 # actual internal input data used (captured)
129 self
.ireg
= self
.ispec()
131 # create per-FU instruction decoders (subsetted). these "satellite"
132 # decoders reduce wire fan-out from the one (main) PowerDecoder2
133 # (used directly by the trap unit) to the *twelve* (or more)
134 # Function Units. we can either have 32 wires (the instruction)
135 # to each, or we can have well over a 200 wire fan-out (to 12
136 # ALUs). it's an easy choice to make.
140 for funame
, fu
in self
.fus
.fus
.items():
141 f_name
= fu
.fnunit
.name
142 fnunit
= fu
.fnunit
.value
143 opkls
= fu
.opsubsetkls
145 # TRAP decoder is the *main* decoder
146 self
.trapunit
= funame
148 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
150 state
=self
.ireg
.state
,
151 svp64_en
=self
.svp64_en
,
152 regreduce_en
=self
.regreduce_en
)
153 self
.des
[funame
] = self
.decoders
[funame
].do
155 # share the SPR decoder with the MMU if it exists
156 if "mmu0" in self
.decoders
:
157 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
159 # next 3 functions are Stage API Compliance
160 def setup(self
, m
, i
):
164 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
169 # elaborate function to create HDL
170 def elaborate(self
, platform
):
171 m
= super().elaborate(platform
)
173 # for testing purposes, to cut down on build time in coriolis2
174 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
175 x
= Signal() # dummy signal
180 m
.submodules
.fus
= self
.fus
181 m
.submodules
.l0
= l0
= self
.l0
182 self
.regs
.elaborate_into(m
, platform
)
187 self
.connect_satellite_decoders(m
)
189 # ssh, cheat: trap uses the main decoder because of the rewriting
190 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
192 # connect up Function Units, then read/write ports, and hazard conflict
193 self
.issue_conflict
= Signal()
194 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
195 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
196 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
197 if self
.allow_overlap
:
198 comb
+= self
.issue_conflict
.eq(raw_hazard
)
200 # note if an exception happened. in a pipelined or OoO design
201 # this needs to be accompanied by "shadowing" (or stalling)
203 for exc
in self
.fus
.excs
.values():
204 el
.append(exc
.happened
)
205 if len(el
) > 0: # at least one exception
206 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
210 def connect_satellite_decoders(self
, m
):
212 for k
, v
in self
.decoders
.items():
213 # connect each satellite decoder and give it the instruction.
214 # as subset decoders this massively reduces wire fanout given
215 # the large number of ALUs
216 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
217 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
218 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
219 # sigh due to SVP64 RA_OR_ZERO detection connect these too
220 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
222 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
223 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
224 if k
!= self
.trapunit
:
225 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
226 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
227 # only the LDST PowerDecodeSubset *actually* needs to
228 # know to use the alternative decoder. this is all
230 if k
.lower().startswith("ldst"):
231 comb
+= v
.use_svp64_ldst_dec
.eq(
232 self
.ireg
.use_svp64_ldst_dec
)
234 def connect_instruction(self
, m
):
235 """connect_instruction
237 uses decoded (from PowerOp) function unit information from CSV files
238 to ascertain which Function Unit should deal with the current
241 some (such as OP_ATTN, OP_NOP) are dealt with here, including
242 ignoring it and halting the processor. OP_NOP is a bit annoying
243 because the issuer expects busy flag still to be raised then lowered.
244 (this requires a fake counter to be set).
246 comb
, sync
= m
.d
.comb
, m
.d
.sync
249 # indicate if core is busy
250 busy_o
= self
.o
.busy_o
251 any_busy_o
= self
.o
.any_busy_o
253 # connect up temporary copy of incoming instruction. the FSM will
254 # either blat the incoming instruction (if valid) into self.ireg
255 # or if the instruction could not be delivered, keep dropping the
256 # latched copy into ireg
257 ilatch
= self
.ispec()
258 self
.instr_active
= Signal()
260 # enable/busy-signals for each FU, get one bit for each FU (by name)
261 fu_enable
= Signal(len(fus
), reset_less
=True)
262 fu_busy
= Signal(len(fus
), reset_less
=True)
265 for i
, funame
in enumerate(fus
.keys()):
266 fu_bitdict
[funame
] = fu_enable
[i
]
267 fu_selected
[funame
] = fu_busy
[i
]
269 # identify function units and create a list by fnunit so that
270 # PriorityPickers can be created for selecting one of them that
271 # isn't busy at the time the incoming instruction needs passing on
272 by_fnunit
= defaultdict(list)
273 for fname
, member
in Function
.__members
__.items():
274 for funame
, fu
in fus
.items():
275 fnunit
= fu
.fnunit
.value
276 if member
.value
& fnunit
: # this FU handles this type of op
277 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
279 # ok now just print out the list of FUs by Function, because we can
280 for fname
, fu_list
in by_fnunit
.items():
281 print ("FUs by type", fname
, fu_list
)
283 # now create a PriorityPicker per FU-type such that only one
284 # non-busy FU will be picked
286 fu_found
= Signal() # take a note if no Function Unit was available
287 for fname
, fu_list
in by_fnunit
.items():
288 i_pp
= PriorityPicker(len(fu_list
))
289 m
.submodules
['i_pp_%s' % fname
] = i_pp
291 for i
, (funame
, fu
) in enumerate(fu_list
):
292 # match the decoded instruction (e.do.fn_unit) against the
293 # "capability" of this FU, gate that by whether that FU is
294 # busy, and drop that into the PriorityPicker.
295 # this will give us an output of the first available *non-busy*
296 # Function Unit (Reservation Statio) capable of handling this
298 fnunit
= fu
.fnunit
.value
299 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
300 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
301 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
303 i_l
.append(en_req
) # store in list for doing the Cat-trick
304 # picker output, gated by enable: store in fu_bitdict
305 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
306 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
307 comb
+= fu_bitdict
[funame
].eq(po
)
308 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
309 # if we don't do this, then when there are no FUs available,
310 # the "p.o_ready" signal will go back "ok we accepted this
311 # instruction" which of course isn't true.
312 with m
.If(i_pp
.en_o
):
313 comb
+= fu_found
.eq(1)
314 # for each input, Cat them together and drop them into the picker
315 comb
+= i_pp
.i
.eq(Cat(*i_l
))
317 # rdmask, which is for registers needs to come from the *main* decoder
318 for funame
, fu
in fus
.items():
319 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
320 comb
+= fu
.rdmaskn
.eq(~rdmask
)
322 # sigh - need a NOP counter
324 with m
.If(counter
!= 0):
325 sync
+= counter
.eq(counter
- 1)
328 # default to reading from incoming instruction: may be overridden
329 # by copy from latch when "waiting"
330 comb
+= self
.ireg
.eq(self
.i
)
331 # always say "ready" except if overridden
332 comb
+= self
.p
.o_ready
.eq(1)
335 with m
.State("READY"):
336 with m
.If(self
.p
.i_valid
): # run only when valid
337 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
338 # check for ATTN: halt if true
339 with m
.Case(MicrOp
.OP_ATTN
):
340 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
342 # fake NOP - this isn't really used (Issuer detects NOP)
343 with m
.Case(MicrOp
.OP_NOP
):
344 sync
+= counter
.eq(2)
348 comb
+= self
.instr_active
.eq(1)
349 comb
+= self
.p
.o_ready
.eq(0)
350 # connect instructions. only one enabled at a time
351 for funame
, fu
in fus
.items():
352 do
= self
.des
[funame
]
353 enable
= fu_bitdict
[funame
]
355 # run this FunctionUnit if enabled route op,
356 # issue, busy, read flags and mask to FU
358 # operand comes from the *local* decoder
359 comb
+= fu
.oper_i
.eq_from(do
)
360 comb
+= fu
.issue_i
.eq(1) # issue when valid
361 # instruction ok, indicate ready
362 comb
+= self
.p
.o_ready
.eq(1)
364 if self
.allow_overlap
:
365 with m
.If(~fu_found
):
366 # latch copy of instruction
367 sync
+= ilatch
.eq(self
.i
)
368 comb
+= self
.p
.o_ready
.eq(1) # accept
372 with m
.State("WAITING"):
373 comb
+= self
.instr_active
.eq(1)
374 comb
+= self
.p
.o_ready
.eq(0)
376 # using copy of instruction, keep waiting until an FU is free
377 comb
+= self
.ireg
.eq(ilatch
)
378 with m
.If(fu_found
): # wait for conflict to clear
379 # connect instructions. only one enabled at a time
380 for funame
, fu
in fus
.items():
381 do
= self
.des
[funame
]
382 enable
= fu_bitdict
[funame
]
384 # run this FunctionUnit if enabled route op,
385 # issue, busy, read flags and mask to FU
387 # operand comes from the *local* decoder
388 comb
+= fu
.oper_i
.eq_from(do
)
389 comb
+= fu
.issue_i
.eq(1) # issue when valid
390 comb
+= self
.p
.o_ready
.eq(1)
394 print ("core: overlap allowed", self
.allow_overlap
)
395 busys
= map(lambda fu
: fu
.busy_o
, fus
.values())
396 comb
+= any_busy_o
.eq(Cat(*busys
).bool())
397 if not self
.allow_overlap
:
398 # for simple non-overlap, if any instruction is busy, set
399 # busy output for core.
400 comb
+= busy_o
.eq(any_busy_o
)
402 # sigh deal with a fun situation that needs to be investigated
404 with m
.If(self
.issue_conflict
):
407 # return both the function unit "enable" dict as well as the "busy".
408 # the "busy-or-issued" can be passed in to the Read/Write port
409 # connecters to give them permission to request access to regfiles
410 return fu_bitdict
, fu_selected
412 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
413 rdpickers
, regfile
, regname
, fspec
):
414 comb
, sync
= m
.d
.comb
, m
.d
.sync
420 # select the required read port. these are pre-defined sizes
421 rfile
= regs
.rf
[regfile
.lower()]
422 rport
= rfile
.r_ports
[rpidx
]
423 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
426 # for checking if the read port has an outstanding write
427 if self
.make_hazard_vecs
:
428 wv
= regs
.wv
[regfile
.lower()]
429 wvchk
= wv
.r_ports
["issue"] # write-vec bit-level hazard check
431 # if a hazard is detected on this read port, simply blithely block
432 # every FU from reading on it. this is complete overkill but very
434 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
437 if not isinstance(fspecs
, list):
443 for i
, fspec
in enumerate(fspecs
):
444 # get the regfile specs for this regfile port
445 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
446 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
447 fspec
.wid
, fspec
.specs
)
448 print ("fpsec", i
, fspec
, len(fuspecs
))
449 ppoffs
.append(pplen
) # record offset for picker
450 pplen
+= len(fspec
.specs
)
451 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
452 rdflag
= Signal(name
=name
, reset_less
=True)
453 comb
+= rdflag
.eq(fspec
.rdport
)
454 rdflags
.append(rdflag
)
456 print ("pplen", pplen
)
458 # create a priority picker to manage this port
459 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
460 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
466 for i
, fspec
in enumerate(fspecs
):
467 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
468 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
469 fspec
.wid
, fspec
.specs
)
470 # connect up the FU req/go signals, and the reg-read to the FU
471 # and create a Read Broadcast Bus
472 for pi
, fuspec
in enumerate(fspec
.specs
):
473 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
475 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
476 fu_active
= fu_selected
[funame
]
477 fu_issued
= fu_bitdict
[funame
]
479 # get (or set up) a latched copy of read register number
480 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
481 read
= Signal
.like(_read
, name
="read_"+name
)
482 if rname
not in fu
.rd_latches
:
483 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
484 fu
.rd_latches
[rname
] = rdl
485 with m
.If(fu
.issue_i
):
486 sync
+= rdl
.eq(_read
)
488 rdl
= fu
.rd_latches
[rname
]
489 # latch to make the read immediately available on issue cycle
490 # after the read cycle, use the latched copy
491 with m
.If(fu
.issue_i
):
492 comb
+= read
.eq(_read
)
496 # connect request-read to picker input, and output to go-rd
497 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
498 pick
= Signal(name
="pick_"+name
) # picker input
499 rp
= Signal(name
="rp_"+name
) # picker output
500 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
501 rhazard
= Signal(name
="rhaz_"+name
)
503 # exclude any currently-enabled read-request (mask out active)
504 # entirely block anything hazarded from being picked
505 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
506 ~delay_pick
& ~rhazard
)
507 comb
+= rdpick
.i
[pi
].eq(pick
)
508 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
510 # if picked, select read-port "reg select" number to port
511 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
512 sync
+= delay_pick
.eq(rp
) # delayed "pick"
513 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
515 # the read-enable happens combinatorially (see mux-bus below)
516 # but it results in the data coming out on a one-cycle delay.
520 addrs
.append(addr_en
)
523 # use the *delayed* pick signal to put requested data onto bus
524 with m
.If(delay_pick
):
525 # connect regfile port to input, creating fan-out Bus
527 print("reg connect widths",
528 regfile
, regname
, pi
, funame
,
529 src
.shape(), rport
.o_data
.shape())
530 # all FUs connect to same port
531 comb
+= src
.eq(rport
.o_data
)
533 if not self
.make_hazard_vecs
:
536 # read the write-hazard bitvector (wv) for any bit that is
537 wvchk_en
= Signal(len(wvchk
.ren
), name
="wv_chk_addr_en_"+name
)
538 issue_active
= Signal(name
="rd_iactive_"+name
)
539 # XXX combinatorial loop here
540 comb
+= issue_active
.eq(fu_active
& rf
)
541 with m
.If(issue_active
):
543 comb
+= wvchk_en
.eq(read
)
545 comb
+= wvchk_en
.eq(1<<read
)
546 # if FU is busy (which doesn't get set at the same time as
547 # issue) and no hazard was detected, clear wvchk_en (i.e.
548 # stop checking for hazards). there is a loop here, but it's
549 # via a DFF, so is ok. some linters may complain, but hey.
550 with m
.If(fu
.busy_o
& ~rhazard
):
551 comb
+= wvchk_en
.eq(0)
553 # read-hazard is ANDed with (filtered by) what is actually
555 comb
+= rhazard
.eq((wvchk
.o_data
& wvchk_en
).bool())
557 wvens
.append(wvchk_en
)
559 # or-reduce the muxed read signals
561 # for unary-addressed
562 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
564 # for binary-addressed
565 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
566 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
567 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
569 if not self
.make_hazard_vecs
:
570 return Const(0) # declare "no hazards"
572 # enable the read bitvectors for this issued instruction
573 # and return whether any write-hazard bit is set
574 comb
+= wvchk
.ren
.eq(ortreereduce_sig(wvens
))
575 comb
+= hazard_detected
.eq(wvchk
.o_data
.bool())
576 return hazard_detected
578 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
579 """connect read ports
581 orders the read regspecs into a dict-of-dicts, by regfile, by
582 regport name, then connects all FUs that want that regport by
583 way of a PriorityPicker.
585 comb
, sync
= m
.d
.comb
, m
.d
.sync
590 # dictionary of lists of regfile read ports
591 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
593 # okaay, now we need a PriorityPicker per regfile per regfile port
594 # loootta pickers... peter piper picked a pack of pickled peppers...
596 for regfile
, spec
in byregfiles_rd
.items():
597 fuspecs
= byregfiles_rdspec
[regfile
]
598 rdpickers
[regfile
] = {}
600 # argh. an experiment to merge RA and RB in the INT regfile
601 # (we have too many read/write ports)
602 if self
.regreduce_en
:
604 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
605 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
606 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
607 if regfile
== 'FAST':
608 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
609 if 'fast2' in fuspecs
:
610 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
611 if 'fast3' in fuspecs
:
612 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
614 # for each named regfile port, connect up all FUs to that port
615 # also return (and collate) hazard detection)
616 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
617 print("connect rd", regname
, fspec
)
618 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
623 return Cat(*rd_hazard
).bool()
625 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
626 funame
, regname
, idx
,
627 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
629 """make_hazards: a setter and a clearer for the regfile write ports
631 setter is at issue time (using PowerDecoder2 regfile write numbers)
632 clearer is at regfile write time (when FU has said what to write to)
634 there is *one* unusual case here which has to be dealt with:
635 when the Function Unit does *NOT* request a write to the regfile
636 (has its data.ok bit CLEARED). this is perfectly legitimate.
639 comb
, sync
= m
.d
.comb
, m
.d
.sync
640 name
= "%s_%s_%d" % (funame
, regname
, idx
)
642 # connect up the bitvector write hazard. unlike the
643 # regfile writeports, a ONE must be written to the corresponding
644 # bit of the hazard bitvector (to indicate the existence of
647 # the detection of what shall be written to is based
649 print ("write vector (for regread)", regfile
, wvset
)
650 wviaddr_en
= Signal(len(wvset
.wen
), name
="wv_issue_addr_en_"+name
)
651 issue_active
= Signal(name
="iactive_"+name
)
652 comb
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
653 with m
.If(issue_active
):
655 comb
+= wviaddr_en
.eq(write
)
657 comb
+= wviaddr_en
.eq(1<<write
)
659 # deal with write vector clear: this kicks in when the regfile
660 # is written to, and clears the corresponding bitvector entry
661 print ("write vector", regfile
, wvclr
)
662 wvaddr_en
= Signal(len(wvclr
.wen
), name
="wvaddr_en_"+name
)
664 comb
+= wvaddr_en
.eq(addr_en
)
667 comb
+= wvaddr_en
.eq(1<<addr_en
)
669 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
670 # this may NOT be the case when an exception occurs
671 if isinstance(fu
, LDSTFunctionUnit
):
672 return wvaddr_en
, wviaddr_en
674 # okaaay, this is preparation for the awkward case.
675 # * latch a copy of wrflag when issue goes high.
676 # * when the fu_wrok (data.ok) flag is NOT set,
677 # but the FU is done, the FU is NEVER going to write
678 # so the bitvector has to be cleared.
679 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
680 with m
.If(~fu
.busy_o
):
681 sync
+= latch_wrflag
.eq(0)
682 with m
.If(fu
.issue_i
& fu_active
):
683 sync
+= latch_wrflag
.eq(wrflag
)
684 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
686 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
688 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
690 return wvaddr_en
, wviaddr_en
692 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
693 wrpickers
, regfile
, regname
, fspec
):
694 comb
, sync
= m
.d
.comb
, m
.d
.sync
700 # select the required write port. these are pre-defined sizes
701 rfile
= regs
.rf
[regfile
.lower()]
702 wport
= rfile
.w_ports
[rpidx
]
704 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
705 print(regfile
, regs
.rf
.keys())
707 # select the write-protection hazard vector. note that this still
708 # requires to WRITE to the hazard bitvector! read-requests need
709 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
710 if self
.make_hazard_vecs
:
711 wv
= regs
.wv
[regfile
.lower()]
712 wvset
= wv
.w_ports
["set"] # write-vec bit-level hazard ctrl
713 wvclr
= wv
.w_ports
["clr"] # write-vec bit-level hazard ctrl
716 if not isinstance(fspecs
, list):
724 for i
, fspec
in enumerate(fspecs
):
725 # get the regfile specs for this regfile port
726 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
727 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
728 fspec
.wid
, fspec
.specs
)
729 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
730 ppoffs
.append(pplen
) # record offset for picker
731 pplen
+= len(fuspecs
)
733 name
= "%s_%s_%d" % (regfile
, regname
, i
)
734 rdflag
= Signal(name
="rd_flag_"+name
)
735 wrflag
= Signal(name
="wr_flag_"+name
)
737 comb
+= rdflag
.eq(rf
)
741 comb
+= wrflag
.eq(wf
)
744 rdflags
.append(rdflag
)
745 wrflags
.append(wrflag
)
747 # create a priority picker to manage this port
748 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
749 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
757 for i
, fspec
in enumerate(fspecs
):
758 # connect up the FU req/go signals and the reg-read to the FU
759 # these are arbitrated by Data.ok signals
760 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
761 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
762 fspec
.wid
, fspec
.specs
)
763 for pi
, fuspec
in enumerate(fspec
.specs
):
764 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
766 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
767 # get (or set up) a write-latched copy of write register number
768 write
= Signal
.like(_write
, name
="write_"+name
)
769 rname
= "%s_%s_%s" % (funame
, regfile
, regname
)
770 if rname
not in fu
.wr_latches
:
771 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
772 fu
.wr_latches
[rname
] = write
773 with m
.If(fu
.issue_i
):
774 sync
+= wrl
.eq(_write
)
775 comb
+= write
.eq(_write
)
777 comb
+= write
.eq(wrl
)
779 write
= fu
.wr_latches
[rname
]
781 # write-request comes from dest.ok
782 dest
= fu
.get_out(idx
)
783 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
784 name
= "fu_wrok_%s_%s_%d" % (funame
, regname
, idx
)
785 fu_wrok
= Signal(name
=name
, reset_less
=True)
786 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
788 # connect request-write to picker input, and output to go-wr
789 fu_active
= fu_selected
[funame
]
790 pick
= fu
.wr
.rel_o
[idx
] & fu_active
791 comb
+= wrpick
.i
[pi
].eq(pick
)
792 # create a single-pulse go write from the picker output
793 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
794 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
795 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
797 # connect the regspec write "reg select" number to this port
798 # only if one FU actually requests (and is granted) the port
799 # will the write-enable be activated
800 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
801 addr_en
= Signal
.like(write
, name
=wname
)
803 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
804 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
808 addrs
.append(addr_en
)
811 # connect regfile port to input
812 print("reg connect widths",
813 regfile
, regname
, pi
, funame
,
814 dest
.shape(), wport
.i_data
.shape())
815 wsigs
.append(fu_dest_latch
)
817 # now connect up the bitvector write hazard
818 if not self
.make_hazard_vecs
:
820 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
821 funame
, regname
, idx
,
822 addr_en
, wp
, fu
, fu_active
,
823 wrflags
[i
], write
, fu_wrok
)
824 wvaddr_en
, wv_issue_en
= res
825 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
826 wvseten
.append(wv_issue_en
) # set data same as enable
827 wvsets
.append(wv_issue_en
) # because enable needs a 1
829 # here is where we create the Write Broadcast Bus. simple, eh?
830 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
832 # for unary-addressed
833 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
835 # for binary-addressed
836 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
837 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
839 if not self
.make_hazard_vecs
:
843 comb
+= wvclr
.wen
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
844 comb
+= wvset
.wen
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
845 comb
+= wvset
.i_data
.eq(ortreereduce_sig(wvsets
))
847 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
848 """connect write ports
850 orders the write regspecs into a dict-of-dicts, by regfile,
851 by regport name, then connects all FUs that want that regport
852 by way of a PriorityPicker.
854 note that the write-port wen, write-port data, and go_wr_i all need to
855 be on the exact same clock cycle. as there is a combinatorial loop bug
856 at the moment, these all use sync.
858 comb
, sync
= m
.d
.comb
, m
.d
.sync
861 # dictionary of lists of regfile write ports
862 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
864 # same for write ports.
865 # BLECH! complex code-duplication! BLECH!
867 for regfile
, spec
in byregfiles_wr
.items():
868 fuspecs
= byregfiles_wrspec
[regfile
]
869 wrpickers
[regfile
] = {}
871 if self
.regreduce_en
:
872 # argh, more port-merging
874 fuspecs
['o'] = [fuspecs
.pop('o')]
875 fuspecs
['o'].append(fuspecs
.pop('o1'))
876 if regfile
== 'FAST':
877 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
878 if 'fast2' in fuspecs
:
879 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
880 if 'fast3' in fuspecs
:
881 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
883 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
884 self
.connect_wrport(m
, fu_bitdict
, fu_selected
, wrpickers
,
885 regfile
, regname
, fspec
)
887 def get_byregfiles(self
, readmode
):
889 mode
= "read" if readmode
else "write"
892 e
= self
.ireg
.e
# decoded instruction to execute
894 # dictionary of dictionaries of lists/tuples of regfile ports.
895 # first key: regfile. second key: regfile port name
896 byregfiles
= defaultdict(lambda: defaultdict(list))
897 byregfiles_spec
= defaultdict(dict)
899 for (funame
, fu
) in fus
.items():
900 # create in each FU a receptacle for the read/write register
901 # hazard numbers. to be latched in connect_rd/write_ports
902 # XXX better that this is moved into the actual FUs, but
903 # the issue there is that this function is actually better
904 # suited at the moment
910 print("%s ports for %s" % (mode
, funame
))
911 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
912 # construct regfile specs: read uses inspec, write outspec
914 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
916 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
917 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
919 # the PowerDecoder2 (main one, not the satellites) contains
920 # the decoded regfile numbers. obtain these now
922 rdport
, read
= regspec_decode_read(e
, regfile
, regname
)
923 wrport
, write
= None, None
925 rdport
, read
= None, None
926 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
928 # construct the dictionary of regspec information by regfile
929 if regname
not in byregfiles_spec
[regfile
]:
930 byregfiles_spec
[regfile
][regname
] = \
931 ByRegSpec(rdport
, wrport
, read
, write
, wid
, [])
932 # here we start to create "lanes"
933 fuspec
= FUSpec(funame
, fu
, idx
)
934 byregfiles
[regfile
][idx
].append(fuspec
)
935 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
938 # append a latch Signal to the FU's list of latches
939 rname
= "%s_%s" % (regfile
, regname
)
941 if rname
not in fu
.rd_latches
:
942 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
943 fu
.rd_latches
[rname
] = rdl
945 if rname
not in fu
.wr_latches
:
946 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
947 fu
.wr_latches
[rname
] = wrl
949 # ok just print that all out, for convenience
950 for regfile
, spec
in byregfiles
.items():
951 print("regfile %s ports:" % mode
, regfile
)
952 fuspecs
= byregfiles_spec
[regfile
]
953 for regname
, fspec
in fuspecs
.items():
954 [rdport
, wrport
, read
, write
, wid
, fuspecs
] = fspec
955 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
956 print(" %s" % regname
, wid
, read
, write
, rdport
, wrport
)
957 for (funame
, fu
, idx
) in fuspecs
:
958 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
959 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
962 return byregfiles
, byregfiles_spec
965 yield from self
.fus
.ports()
966 yield from self
.i
.e
.ports()
967 yield from self
.l0
.ports()
974 if __name__
== '__main__':
975 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
980 dut
= NonProductionCore(pspec
)
981 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
982 with
open("test_core.il", "w") as f
: