debug radix mmu ISACaller

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index dbfb492dbd9b050efabcfd6ec7367aee728e1c12..26a10d093d5f6a0487873ffaa6165e4a53832c49 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -399,12 +399,12 @@ class ISACaller:
             initial_svstate = SVP64State(initial_svstate)
         self.svstate = initial_svstate
         self.gpr = GPR(decoder2, self, self.svstate, regfile)
+        self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         if mmu:
             self.mem = RADIX(self.mem, self)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
-        self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
         # TODO, needed here:

diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py
index c208fa09db604eb76afdf1c928449136badb651c..0f092612d265ba5fe58b538123f924a66cc12cb5 100644 (file)
--- a/src/soc/decoder/isa/radixmmu.py
+++ b/src/soc/decoder/isa/radixmmu.py
@@ -170,10 +170,10 @@ class RADIX:
         self.mem = mem
         self.caller = caller
         #TODO move to lookup
-        #self.dsisr = self.caller.spr["DSISR"]
-        #self.dar   = self.caller.spr["DAR"]
-        #self.pidr  = self.caller.spr["PIDR"]
-        #self.prtbl = self.caller.spr["PRTBL"]
+        self.dsisr = self.caller.spr["DSISR"]
+        self.dar   = self.caller.spr["DAR"]
+        self.pidr  = self.caller.spr["PIDR"]
+        self.prtbl = self.caller.spr["PRTBL"]
 
         # cached page table stuff
         self.pgtbl0 = 0
@@ -181,11 +181,10 @@ class RADIX:
         self.pgtbl3 = 0
         self.pt3_valid = False
 
-    def __call__(self,*args, **kwargs):
-        print("TODO: implement RADIX.__call__()")
-        print(args)
-        print(kwargs)
-        return None
+    def __call__(self, addr, sz):
+        val = self.ld(addr.value, sz, swap=False)
+        print("RADIX memread", addr, sz, val)
+        return SelectableInt(val, sz*8)
 
     def ld(self, address, width=8, swap=True, check_in_mem=False):
         print("RADIX: ld from addr 0x%x width %d" % (address, width))
@@ -285,8 +284,8 @@ class RADIX:
         """
         # get sprs
         print("_walk_tree")
-        pidr  = self.caller.spr[DEC_SPR.PIDR.value]
-        prtbl = self.caller.spr[DEC_SPR.PRTBL.value]
+        pidr  = self.caller.spr["PIDR"]
+        prtbl = self.caller.spr["PRTBL"]
         print(pidr)
         print(prtbl)