# Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os)
-autoidx 14844
+autoidx 14636
attribute \src "libresoc.v:5.1-335.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21209.7-21209.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 6 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:21271.7-21271.15"
wire \initial
wire \alu_alu0_alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_alu0_alu_op__zero_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_alu0_cr_a
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
wire \alu_alu0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_alu0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_alu0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_alu0_p_ready_o
wire width 64 \alu_alu0_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_alu0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_alu0_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \alu_alu0_xer_ca$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_alu0_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \alu_alu0_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \alu_alu0_xer_so$1
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 21 \cu_busy_o
wire output 40 \dest5_o
attribute \src "libresoc.v:21333.7-21333.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \src_sel$85
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 35 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 37 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 39 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $and$libresoc.v:22016$541
wire input 18 \alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 28 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 8 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 7 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 27 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 37 \p_ready_o
wire \pipe1_alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \pipe1_alu_op__zero_a$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe1_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe1_muxid
wire \pipe1_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe1_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe1_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe1_p_ready_o
wire width 64 \pipe1_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe1_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe1_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \pipe1_xer_ca$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe1_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \pipe1_xer_so$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \pipe2_alu_op__data_len
wire \pipe2_alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \pipe2_alu_op__zero_a$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe2_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe2_cr_a$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_cr_a_ok$46
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe2_muxid
wire \pipe2_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe2_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_o$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_o_ok$44
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe2_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159"
wire \pipe2_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ca$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ca_ok$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ov$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ov_ok$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so_ok$52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 32 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 33 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 29 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 35 \xer_ca$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 30 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 34 \xer_so$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 6 \xer_so_ok
attribute \module_not_derived 1
attribute \src "libresoc.v:23584.5-23587.4"
wire input 13 \br_op__lk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 20 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 15 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 18 \fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 16 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 19 \fast2$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 5 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 17 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 22 \p_ready_o
wire width 4 \pipe_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_fast1$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_fast2$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe_muxid
wire \pipe_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe_p_ready_o
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0"
attribute \generator "nMigen"
module \alu_cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 12 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 16 \cr_a$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 17 \cr_b
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 7 \cr_op__insn_type$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 output 11 \full_cr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 input 15 \full_cr$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \full_cr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 5 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 10 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 20 \p_ready_o
wire input 19 \p_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \pipe_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe_cr_a$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \pipe_cr_b
wire width 7 \pipe_cr_op__insn_type$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 \pipe_full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \pipe_full_cr$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_full_cr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe_muxid
wire \pipe_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe_p_ready_o
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0"
attribute \generator "nMigen"
module \alu_div0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 35 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 27 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 24 \logical_op__data_len
wire input 7 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 6 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 26 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 34 \p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159"
wire input 33 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe_end_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_end_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire \pipe_end_div_by_zero
wire \pipe_end_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe_end_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_end_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_end_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe_end_p_ready_o
wire width 64 \pipe_end_rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
wire width 192 \pipe_end_remainder
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe_end_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_end_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \pipe_end_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_end_xer_so$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_end_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire \pipe_middle_0_div_by_zero
wire width 64 input 30 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 31 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 28 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 32 \xer_so$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \xer_so_ok
attribute \module_not_derived 1
attribute \src "libresoc.v:26040.10-26043.4"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26289.7-26289.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26351.7-26351.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26413.7-26413.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26475.7-26475.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26537.7-26537.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26599.7-26599.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26661.7-26661.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26723.7-26723.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26785.7-26785.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:26847.7-26847.15"
wire \initial
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0"
attribute \generator "nMigen"
module \alu_logical0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 22 \logical_op__data_len
wire input 15 \logical_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \logical_op__zero_a$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \logical_pipe1_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe1_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \logical_pipe1_logical_op__data_len
wire \logical_pipe1_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \logical_pipe1_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \logical_pipe1_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe1_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \logical_pipe1_p_ready_o
wire width 64 \logical_pipe1_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \logical_pipe1_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe1_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \logical_pipe1_xer_so$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe1_xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \logical_pipe2_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \logical_pipe2_cr_a$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_cr_a_ok$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \logical_pipe2_logical_op__data_len
wire \logical_pipe2_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \logical_pipe2_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \logical_pipe2_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \logical_pipe2_o$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_o_ok$41
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \logical_pipe2_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159"
wire \logical_pipe2_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \logical_pipe2_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 5 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 4 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 24 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 30 \p_ready_o
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0"
attribute \generator "nMigen"
module \alu_mul0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 21 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \cr_a_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \mul_pipe2_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \mul_pipe2_xer_so$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \mul_pipe3_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul_pipe3_cr_a_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \mul_pipe3_neg_res32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 129 \mul_pipe3_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \mul_pipe3_o$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul_pipe3_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \mul_pipe3_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159"
wire \mul_pipe3_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \mul_pipe3_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul_pipe3_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \mul_pipe3_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul_pipe3_xer_so$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul_pipe3_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 7 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 6 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 20 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 28 \p_ready_o
wire width 64 input 24 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 25 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 22 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 26 \xer_so$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \xer_so_ok
attribute \module_not_derived 1
attribute \src "libresoc.v:28970.13-29011.4"
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0"
attribute \generator "nMigen"
module \alu_shift_rot0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 5 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 24 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 33 \p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159"
wire input 32 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe1_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe1_muxid
wire \pipe1_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe1_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe1_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe1_p_ready_o
wire \pipe1_sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \pipe1_sr_op__write_cr0$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe1_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \pipe1_xer_ca$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \pipe1_xer_so$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe1_xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe2_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \pipe2_cr_a$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_cr_a_ok$43
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe2_muxid
wire \pipe2_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe2_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_o$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_o_ok$41
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe2_p_ready_o
wire \pipe2_sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \pipe2_sr_op__write_cr0$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe2_xer_ca$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_ca_ok$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 27 \ra
wire input 15 \sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \sr_op__write_cr0$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 26 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 31 \xer_ca$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 30 \xer_so
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0"
attribute \generator "nMigen"
module \alu_spr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 28 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 16 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 22 \fast1$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 6 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 9 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 8 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 14 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 27 \p_ready_o
wire input 26 \p_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_fast1$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe_muxid
wire \pipe_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe_p_ready_o
wire width 64 \pipe_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe_spr1$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_spr1_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \pipe_spr_op__is_32bit$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \pipe_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe_xer_ca$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \pipe_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \pipe_xer_ov$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \pipe_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_xer_so$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 20 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 15 \spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 21 \spr1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 7 \spr1_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire input 13 \spr_op__is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \spr_op__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 19 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 25 \xer_ca$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 18 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 24 \xer_ov$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 17 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 23 \xer_so$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \xer_so_ok
attribute \module_not_derived 1
attribute \src "libresoc.v:30676.10-30679.4"
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0"
attribute \generator "nMigen"
module \alu_trap0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 29 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 19 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 25 \fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 20 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 26 \fast2$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 22 \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 6 \msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \muxid
wire input 8 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 7 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 21 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 18 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 28 \p_ready_o
wire width 8 \pipe1_trap_op__traptype$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe2_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_fast1$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \pipe2_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_fast2$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \pipe2_muxid
wire \pipe2_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \pipe2_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pipe2_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pipe2_o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \pipe2_p_ready_o
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31623.7-31623.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31685.7-31685.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31747.7-31747.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31809.7-31809.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31871.7-31871.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31933.7-31933.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:31995.7-31995.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:32057.7-32057.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:32119.7-32119.15"
wire \initial
wire \alu_branch0_br_op__lk$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \alu_branch0_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_branch0_fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_branch0_fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_branch0_fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_branch0_fast2$2
wire \alu_branch0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_branch0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_branch0_nia
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_branch0_p_ready_o
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 11 \cu_busy_o
wire width 64 output 23 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 64 output 25 \dest3_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 18 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 21 \fast2_ok
attribute \src "libresoc.v:33529.7-33529.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 24 \nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:34588.7-34588.15"
wire \initial
wire width 64 output 8 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 7 \cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 input 42 \core_core_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 input 61 \core_core_cr_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 62 \core_core_cr_rd_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 input 63 \core_core_cr_wr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire input 52 \core_core_exc_$signal
attribute \enum_value_00100000000000 "MMU"
attribute \enum_value_01000000000000 "SV"
attribute \enum_value_10000000000000 "VL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 input 45 \core_core_fn_unit
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 input 50 \core_core_input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 input 43 \core_core_insn
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \enum_value_1001100 "OP_SETVL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 input 44 \core_core_insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire input 64 \core_core_is_32bit
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wire width 64 input 41 \core_core_msr
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wire input 48 \core_core_oe
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wire input 49 \core_core_oe_ok
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wire input 46 \core_core_rc
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wire input 47 \core_core_rc_ok
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wire width 13 input 60 \core_core_trapaddr
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wire width 8 input 51 \core_core_traptype
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wire width 7 input 34 \core_cr_in1
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wire input 35 \core_cr_in1_ok
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wire width 7 input 36 \core_cr_in2
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wire width 7 input 38 \core_cr_in2$1
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wire input 37 \core_cr_in2_ok
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wire input 39 \core_cr_in2_ok$2
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wire width 7 input 40 \core_cr_out
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wire input 29 \core_fast1_ok
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wire input 31 \core_fast2_ok
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire width 64 input 65 \core_pc
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wire width 7 input 18 \core_reg1
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wire input 19 \core_reg1_ok
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wire input 21 \core_reg2_ok
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wire width 7 input 22 \core_reg3
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wire input 23 \core_reg3_ok
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attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
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wire width 10 input 25 \core_spr1
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wire input 26 \core_spr1_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
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wire width 10 input 24 \core_spro
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
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wire \core_terminate_o$next
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wire width 3 input 27 \core_xer_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
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wire input 97 \coresync_clk
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wire input 1 \coresync_rst
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wire \dec_ALU_sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
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wire \dec_DIV_sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 \dec_LDST_raw_opcode_in
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wire \dec_LDST_sv_a_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 \dec_LOGICAL_raw_opcode_in
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wire \dec_LOGICAL_sv_a_nz
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282"
wire \dp_XER_xer_so_spr0_2$next
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wire \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187"
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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
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wire \fus_cr_a_ok
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wire \fus_cr_a_ok$122
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wire \fus_cr_a_ok$123
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wire \fus_cr_a_ok$124
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wire \fus_cr_a_ok$125
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wire \fus_cr_a_ok$126
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire \fus_cu_busy_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 2 \fus_dest6_o
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wire width 64 \fus_ea
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wire \fus_fast1_ok
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wire \fus_fast1_ok$150
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wire \fus_fast1_ok$151
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wire \fus_fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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wire \fus_fast2_ok$152
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wire \fus_full_cr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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wire width 96 \fus_ldst_port0_addr_i
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wire \fus_ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire \fus_ldst_port0_addr_ok_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire \fus_ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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wire width 64 \fus_ldst_port0_ld_data_o
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wire \fus_ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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wire \fus_ldst_port0_st_data_i_ok
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wire \fus_msr_ok
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wire \fus_nia_ok
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wire \fus_nia_ok$158
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wire width 64 \fus_o
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wire \fus_o_ok
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wire \fus_o_ok$101
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wire \fus_o_ok$104
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wire \fus_o_ok$107
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wire \fus_o_ok$110
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wire \fus_o_ok$92
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wire \fus_o_ok$95
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wire width 4 \fus_oper_i_alu_alu0__data_len
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wire \fus_spr1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 4 \fus_src6_i$85
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wire \fus_xer_ca_ok
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wire \fus_xer_ca_ok$132
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wire \fus_xer_ca_ok$133
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wire \fus_xer_ov_ok
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wire \fus_xer_ov_ok$136
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wire \fus_xer_ov_ok$137
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wire \fus_xer_ov_ok$138
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wire \fus_xer_so_ok
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wire \fus_xer_so_ok$141
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fus_xer_so_ok$142
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fus_xer_so_ok$143
attribute \src "libresoc.v:36262.7-36262.15"
wire \initial
wire width 64 output 15 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 13 \msr__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:280"
wire \pick_CR_cr_a_branch0_1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
wire \rp_XER_xer_so_spr0_2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 7 \spr_spr1__addr
+ wire width 4 \spr_spr1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 7 \spr_spr1__addr$175
+ wire width 4 \spr_spr1__addr$175
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \spr_spr1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 9 \sv__ren
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93"
wire input 68 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \sv_a_nz$176
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \sv_a_nz$177
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \sv_a_nz$178
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \sv_a_nz$179
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \sv_a_nz$180
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94"
wire input 87 \wb_dcache_en
connect \o_ok 1'0
connect \ea_ok 1'0
connect \spr_spr1__wen \wp$1811
- connect \spr_spr1__addr$175 \addr_en$1814 [6:0]
+ connect \spr_spr1__addr$175 \addr_en$1814 [3:0]
connect \spr_spr1__data_i \fus_dest2_o$162
connect \addr_en$1814 \$1815
connect \wp$1811 \$1812
connect \wrpick_INT_o_i [0] \$950
connect \wrflag_alu0_o_0 \$948
connect \spr_spr1__ren \$946
- connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0]
+ connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [3:0]
connect \addr_en_SPR_spr1_spr0_0 \$944
connect \rp_SPR_spr1_spr0_0 \$942
connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 14 \data_i
wire \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \all_rd_rise
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_cr0_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \alu_cr0_cr_a$2
wire width 7 \alu_cr0_cr_op__insn_type
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 7 \alu_cr0_cr_op__insn_type$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \alu_cr0_full_cr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 \alu_cr0_full_cr$1
wire \alu_cr0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_cr0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_cr0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_cr0_p_ready_o
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 24 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 22 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 6 \cu_busy_o
wire width 32 output 21 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 4 output 23 \dest3_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 20 \full_cr_ok
attribute \src "libresoc.v:49763.7-49763.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 16 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:50824.7-50824.15"
wire \initial
wire \$97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226"
wire \$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 30 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 input 13 \core_dbg_core_dbg_dststep
wire width 64 \log_dmi_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120"
wire width 32 \log_write_addr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135"
wire width 64 \stat_reg
wire width 7 $pos$libresoc.v:78974$3671_Y
attribute \src "libresoc.v:78975.18-78975.121"
wire width 7 $pos$libresoc.v:78975$3673_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218"
wire \$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
wire \$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
wire \$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226"
wire \$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249"
wire \$114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250"
wire \$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251"
wire \$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252"
wire \$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \$98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101"
wire width 8 output 5 \asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire input 1 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 output 39 \cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 30 \cr_in1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \cr_in1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 32 \cr_in2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 34 \cr_in2$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \cr_in2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 35 \cr_in2_ok$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 36 \cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 37 \cr_out_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 output 59 \cr_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 60 \cr_rd_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 output 61 \cr_wr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 62 \cr_wr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire width 64 input 64 \cur_dec
wire width 3 \dec_X_BF
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 3 \dec_X_BFA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_a_fast_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_a_fast_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 \dec_a_reg_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_a_reg_a_ok
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
wire width 3 \dec_a_sel_in
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \dec_a_spr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_a_spr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116"
wire \dec_a_sv_nz
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 8 \dec_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_b_fast_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_b_fast_b_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec_b_reg_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_b_reg_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
wire width 4 \dec_b_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 \dec_c_reg_c
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_c_reg_c_ok
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
wire width 2 \dec_c_sel_in
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_111 "CR1"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 3 \dec_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_cr_in_cr_bitfield
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_cr_in_cr_bitfield_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_in_cr_bitfield_b_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_cr_in_cr_bitfield_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_in_cr_bitfield_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_in_cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \dec_cr_in_cr_fxm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_in_cr_fxm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543"
wire width 32 \dec_cr_in_insn_in
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \enum_value_111 "CR1"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542"
wire width 3 \dec_cr_in_sel_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_101 "CR1"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 3 \dec_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_cr_out_cr_bitfield
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_out_cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \dec_cr_out_cr_fxm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_cr_out_cr_fxm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618"
wire width 32 \dec_cr_out_insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616"
wire \dec_cr_out_rc_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \enum_value_101 "CR1"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617"
wire width 3 \dec_cr_out_sel_in
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 \dec_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244"
wire \dec_irq_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198"
wire \dec_is_32b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198"
wire \dec_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_o2_fast_o2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_o2_fast_o2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
wire \dec_o2_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 \dec_o2_reg_o2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_o2_reg_o2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec_o_fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_o_fast_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 \dec_o_reg_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_o_reg_o_ok
attribute \enum_base_type "OutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RT_OR_ZERO"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351"
wire width 3 \dec_o_sel_in
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \dec_o_spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_o_spr_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
attribute \enum_value_100 "RT_OR_ZERO"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 3 \dec_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \enum_base_type "LDSTMode"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 \dec_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 8 \ea
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 9 \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire output 50 \exc_$signal
wire output 56 \exc_$signal$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire output 57 \exc_$signal$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1214"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243"
wire \ext_irq_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 22 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 24 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 26 \fasto1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \fasto1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 28 \fasto2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \fasto2_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \enum_value_00100000000000 "MMU"
attribute \enum_value_01000000000000 "SV"
attribute \enum_value_10000000000000 "VL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 output 42 \fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246"
wire \illeg_ok
attribute \src "libresoc.v:77233.7-77233.15"
wire \initial
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 output 48 \input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 output 40 \insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
wire width 32 \insn_in$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
wire width 32 \insn_in$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
wire width 32 \insn_in$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352"
wire width 32 \insn_in$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
wire width 32 \insn_in$89
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \enum_value_1001100 "OP_SETVL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 output 41 \insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire output 63 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53"
wire \is_priv_insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
wire output 43 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
wire width 64 output 38 \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 46 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 47 \oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245"
wire \priv_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 4 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 44 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 45 \rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 10 \reg1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 11 \reg1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 12 \reg2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 13 \reg2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 14 \reg3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 15 \reg3_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 6 \rego
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 7 \rego_ok
attribute \enum_base_type "OutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RT_OR_ZERO"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415"
wire width 3 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 18 \spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 19 \spr1_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 16 \spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 17 \spro_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire input 65 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101"
wire width 8 \tmp_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_cr_in1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_cr_in1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_cr_in2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_cr_in2$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_cr_in2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_cr_in2_ok$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_cr_out_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_ea
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_ea_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \tmp_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \tmp_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \tmp_fasto1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_fasto1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \tmp_fasto2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_fasto2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_reg1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_reg1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_reg2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_reg2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_reg3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_reg3_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \tmp_rego
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_rego_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \tmp_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_spr1_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \tmp_spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_spro_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 \tmp_tmp_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \tmp_tmp_cr_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_cr_rd_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \tmp_tmp_cr_wr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_cr_wr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \tmp_tmp_exc_$signal
attribute \enum_value_00100000000000 "MMU"
attribute \enum_value_01000000000000 "SV"
attribute \enum_value_10000000000000 "VL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 \tmp_tmp_fn_unit
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 \tmp_tmp_input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 \tmp_tmp_insn
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \enum_value_1001100 "OP_SETVL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 \tmp_tmp_insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire \tmp_tmp_is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
wire \tmp_tmp_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
wire width 64 \tmp_tmp_msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \tmp_tmp_rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
wire width 13 \tmp_tmp_trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
wire width 8 \tmp_tmp_traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111"
wire width 3 \tmp_xer_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112"
wire \tmp_xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
wire width 13 output 58 \trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
wire width 8 output 49 \traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111"
wire width 3 output 20 \xer_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112"
wire output 21 \xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249"
cell $and $and$libresoc.v:78939$3632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \cur_msr [15]
connect \Y $and$libresoc.v:78939$3632_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250"
cell $and $and$libresoc.v:78940$3633
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \cur_msr [15]
connect \Y $and$libresoc.v:78940$3633_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251"
cell $and $and$libresoc.v:78941$3634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \cur_msr [14]
connect \Y $and$libresoc.v:78941$3634_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:78948$3641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$37
connect \Y $and$libresoc.v:78948$3641_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:78949$3642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:78949$3642_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:78951$3644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$43
connect \Y $and$libresoc.v:78951$3644_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:78953$3646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$47
connect \Y $and$libresoc.v:78953$3646_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:78965$3658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$71
connect \Y $and$libresoc.v:78965$3658_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:78966$3659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:78966$3659_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:78968$3661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$77
connect \Y $and$libresoc.v:78968$3661_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:78970$3663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$81
connect \Y $and$libresoc.v:78970$3663_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218"
cell $eq $eq$libresoc.v:78935$3628
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:78935$3628_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
cell $eq $eq$libresoc.v:78936$3629
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001010
connect \Y $eq$libresoc.v:78936$3629_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
cell $eq $eq$libresoc.v:78937$3630
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:78937$3630_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226"
cell $eq $eq$libresoc.v:78938$3631
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0111111
connect \Y $eq$libresoc.v:78938$3631_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252"
cell $eq $eq$libresoc.v:78942$3635
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000000
connect \Y $eq$libresoc.v:78942$3635_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300"
cell $eq $eq$libresoc.v:78943$3636
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0111111
connect \Y $eq$libresoc.v:78943$3636_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301"
cell $eq $eq$libresoc.v:78944$3637
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'1001001
connect \Y $eq$libresoc.v:78944$3637_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310"
cell $eq $eq$libresoc.v:78946$3639
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'1000110
connect \Y $eq$libresoc.v:78946$3639_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:78947$3640
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:78947$3640_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:78950$3643
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:78950$3643_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:78954$3647
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:78954$3647_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:78955$3648
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:78955$3648_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:78957$3650
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:78957$3650_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:78958$3651
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:78958$3651_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:78960$3653
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:78960$3653_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:78962$3655
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:78962$3655_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:78964$3657
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:78964$3657_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:78967$3660
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:78967$3660_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78932$3622
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \dec_cr_in_cr_bitfield_b
connect \Y $extend$libresoc.v:78932$3622_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78933$3624
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \dec_cr_in_cr_bitfield_o
connect \Y $extend$libresoc.v:78933$3624_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78934$3626
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \dec_cr_out_cr_bitfield
connect \Y $extend$libresoc.v:78934$3626_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78971$3664
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \dec_a_reg_a
connect \Y $extend$libresoc.v:78971$3664_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78972$3666
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \dec_c_reg_c
connect \Y $extend$libresoc.v:78972$3666_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78973$3668
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \dec_o_reg_o
connect \Y $extend$libresoc.v:78973$3668_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78974$3670
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \dec_o2_reg_o2
connect \Y $extend$libresoc.v:78974$3670_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:78975$3672
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \dec_cr_in_cr_bitfield
connect \Y $extend$libresoc.v:78975$3672_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:78952$3645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:78952$3645_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:78969$3662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:78969$3662_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301"
cell $or $or$libresoc.v:78945$3638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$30
connect \Y $or$libresoc.v:78945$3638_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:78956$3649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$53
connect \Y $or$libresoc.v:78956$3649_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:78959$3652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$59
connect \Y $or$libresoc.v:78959$3652_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:78961$3654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$63
connect \Y $or$libresoc.v:78961$3654_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:78963$3656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$67
connect \Y $or$libresoc.v:78963$3656_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78932$3623
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78932$3622_Y
connect \Y $pos$libresoc.v:78932$3623_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78933$3625
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78933$3624_Y
connect \Y $pos$libresoc.v:78933$3625_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78934$3627
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78934$3626_Y
connect \Y $pos$libresoc.v:78934$3627_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78971$3665
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78971$3664_Y
connect \Y $pos$libresoc.v:78971$3665_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78972$3667
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78972$3666_Y
connect \Y $pos$libresoc.v:78972$3667_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78973$3669
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78973$3668_Y
connect \Y $pos$libresoc.v:78973$3669_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78974$3671
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A $extend$libresoc.v:78974$3670_Y
connect \Y $pos$libresoc.v:78974$3671_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:78975$3673
parameter \A_SIGNED 0
parameter \A_WIDTH 7
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$83 \$75 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898"
switch \dec_lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$49 \$41 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218"
switch \$106
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\tmp_xer_in[2:0] 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220"
switch \$108
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222"
switch \$110
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226"
switch \$112
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
switch \dec_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110
case 7'0101110 , 7'0110001
assign { } { }
assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
switch \tmp_tmp_insn [20]
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256"
switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal }
attribute \src "libresoc.v:0.0-0.0"
case 5'----1
assign $1\traptype[7:0] $2\traptype[7:0]
assign $1\xer_in[2:0] $2\xer_in[2:0]
assign $1\xer_out[0:0] $2\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1228"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257"
switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign $2\traptype[7:0] $3\traptype[7:0]
assign $2\xer_in[2:0] $3\xer_in[2:0]
assign $2\xer_out[0:0] $3\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260"
switch \dec2_exc_$signal$14
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $2\traptype[7:0] $4\traptype[7:0]
assign $2\xer_in[2:0] $4\xer_in[2:0]
assign $2\xer_out[0:0] $4\xer_out[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1237"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266"
switch \dec2_exc_$signal$14
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode }
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301"
switch \$32
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $5\fasto2[2:0] $1\fasto2[2:0]
assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310"
switch \$34
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $or$libresoc.v:121317$4526_Y
attribute \src "libresoc.v:121319.18-121319.110"
wire $or$libresoc.v:121319$4528_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 19 \ALU__data_len
wire \dec_ALU_sgn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_ALU_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire \dec_ai_immz_out
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 \dec_ai_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire \dec_ai_sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:120873.7-120873.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 21 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire input 2 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121306$4515
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:121306$4515_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121308$4517
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:121308$4517_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121321$4530
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:121321$4530_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121322$4531
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:121322$4531_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121324$4533
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:121324$4533_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121326$4535
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:121326$4535_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121327$4536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:121327$4536_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121328$4537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:121328$4537_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:121309$4518
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:121309$4518_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:121310$4519
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:121310$4519_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121312$4521
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:121312$4521_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121313$4522
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:121313$4522_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121315$4524
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:121315$4524_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:121316$4525
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:121316$4525_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:121318$4527
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:121318$4527_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:121320$4529
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:121320$4529_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:121323$4532
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:121323$4532_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:121329$4538
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:121329$4538_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:121307$4516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:121307$4516_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:121325$4534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:121325$4534_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:121311$4520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:121311$4520_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:121314$4523
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:121314$4523_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:121317$4526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:121317$4526_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:121319$4528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879"
switch \dec_ALU_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:121832$4554_Y
attribute \src "libresoc.v:121834.18-121834.110"
wire $or$libresoc.v:121834$4556_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 64 output 3 \BRANCH__cia
wire width 2 \dec_BRANCH_rc_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_BRANCH_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:121460.7-121460.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 1 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121821$4543
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:121821$4543_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121823$4545
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:121823$4545_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121836$4558
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:121836$4558_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121837$4559
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:121837$4559_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121839$4561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:121839$4561_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:121841$4563
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:121841$4563_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121842$4564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:121842$4564_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:121843$4565
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:121843$4565_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:121824$4546
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:121824$4546_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:121825$4547
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:121825$4547_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121827$4549
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:121827$4549_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121828$4550
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:121828$4550_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:121830$4552
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:121830$4552_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:121831$4553
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:121831$4553_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:121833$4555
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:121833$4555_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:121835$4557
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:121835$4557_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:121838$4560
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:121838$4560_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:121844$4566
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:121844$4566_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:121822$4544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:121822$4544_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:121840$4562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:121840$4562_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:121826$4548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:121826$4548_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:121829$4551
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:121829$4551_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:121832$4554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:121832$4554_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:121834$4556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:870"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898"
switch \dec_BRANCH_lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:122245$4582_Y
attribute \src "libresoc.v:122247.18-122247.110"
wire $or$libresoc.v:122247$4584_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:121944.7-121944.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 5 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122234$4571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:122234$4571_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122236$4573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:122236$4573_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122249$4586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:122249$4586_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122250$4587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:122250$4587_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122252$4589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:122252$4589_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122254$4591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:122254$4591_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122255$4592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:122255$4592_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122256$4593
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:122256$4593_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:122237$4574
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:122237$4574_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:122238$4575
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:122238$4575_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122240$4577
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:122240$4577_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122241$4578
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:122241$4578_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122243$4580
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:122243$4580_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:122244$4581
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:122244$4581_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:122246$4583
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:122246$4583_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:122248$4585
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:122248$4585_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:122251$4588
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:122251$4588_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:122257$4594
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:122257$4594_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:122235$4572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:122235$4572_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:122253$4590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:122253$4590_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:122239$4576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:122239$4576_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:122242$4579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:122242$4579_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:122245$4582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:122245$4582_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:122247$4584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:122764$4609_Y
attribute \src "libresoc.v:122766.18-122766.110"
wire $or$libresoc.v:122766$4611_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 19 \DIV__data_len
wire \dec_DIV_sgn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_DIV_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire \dec_ai_immz_out
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 \dec_ai_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire \dec_ai_sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:122320.7-122320.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 21 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire input 2 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122753$4598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:122753$4598_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122755$4600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:122755$4600_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122768$4613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:122768$4613_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122769$4614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:122769$4614_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122771$4616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:122771$4616_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:122773$4618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:122773$4618_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122774$4619
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:122774$4619_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:122775$4620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:122775$4620_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:122756$4601
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:122756$4601_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:122757$4602
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:122757$4602_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122759$4604
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:122759$4604_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122760$4605
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:122760$4605_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:122762$4607
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:122762$4607_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:122763$4608
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:122763$4608_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:122765$4610
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:122765$4610_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:122767$4612
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:122767$4612_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:122770$4615
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:122770$4615_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:122776$4621
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:122776$4621_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:122754$4599
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:122754$4599_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:122772$4617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:122772$4617_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:122758$4603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:122758$4603_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:122761$4606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:122761$4606_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:122764$4609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:122764$4609_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:122766$4611
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879"
switch \dec_DIV_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:123346$4637_Y
attribute \src "libresoc.v:123348.18-123348.110"
wire $or$libresoc.v:123348$4639_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire output 15 \LDST__byte_reverse
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 \dec_LDST_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire \dec_ai_immz_out
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 \dec_ai_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire \dec_ai_sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:122907.7-122907.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 19 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire input 2 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123335$4626
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:123335$4626_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123337$4628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:123337$4628_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123350$4641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:123350$4641_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123351$4642
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:123351$4642_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123353$4644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:123353$4644_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123355$4646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:123355$4646_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123356$4647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:123356$4647_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123357$4648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:123357$4648_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:123338$4629
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:123338$4629_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:123339$4630
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:123339$4630_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123341$4632
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:123341$4632_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123342$4633
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:123342$4633_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123344$4635
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:123344$4635_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:123345$4636
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:123345$4636_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:123347$4638
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:123347$4638_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:123349$4640
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:123349$4640_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:123352$4643
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:123352$4643_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:123358$4649
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:123358$4649_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:123336$4627
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:123336$4627_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:123354$4645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:123354$4645_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:123340$4631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:123340$4631_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:123343$4634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:123343$4634_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:123346$4637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:123346$4637_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:123348$4639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:123916$4664_Y
attribute \src "libresoc.v:123918.18-123918.110"
wire $or$libresoc.v:123918$4666_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 output 19 \LOGICAL__data_len
wire \dec_LOGICAL_sgn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_LOGICAL_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire \dec_ai_immz_out
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 \dec_ai_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire \dec_ai_sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:123472.7-123472.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 21 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire input 2 \sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123905$4653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:123905$4653_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123907$4655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:123907$4655_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123920$4668
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:123920$4668_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123921$4669
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:123921$4669_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123923$4671
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:123923$4671_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:123925$4673
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:123925$4673_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123926$4674
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:123926$4674_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:123927$4675
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:123927$4675_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:123908$4656
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:123908$4656_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:123909$4657
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:123909$4657_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123911$4659
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:123911$4659_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123912$4660
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:123912$4660_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:123914$4662
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:123914$4662_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:123915$4663
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:123915$4663_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:123917$4665
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:123917$4665_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:123919$4667
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:123919$4667_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:123922$4670
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:123922$4670_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:123928$4676
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:123928$4676_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:123906$4654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:123906$4654_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:123924$4672
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:123924$4672_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:123910$4658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:123910$4658_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:123913$4661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:123913$4661_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:123916$4664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:123916$4664_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:123918$4666
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879"
switch \dec_LOGICAL_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:124443$4692_Y
attribute \src "libresoc.v:124445.18-124445.110"
wire $or$libresoc.v:124445$4694_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \dec_MUL_sgn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_MUL_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:124059.7-124059.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 14 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124432$4681
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:124432$4681_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124434$4683
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:124434$4683_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124447$4696
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:124447$4696_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124448$4697
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:124448$4697_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124450$4699
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:124450$4699_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124452$4701
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:124452$4701_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124453$4702
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:124453$4702_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124454$4703
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:124454$4703_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:124435$4684
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:124435$4684_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:124436$4685
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:124436$4685_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124438$4687
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:124438$4687_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124439$4688
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:124439$4688_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124441$4690
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:124441$4690_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:124442$4691
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:124442$4691_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:124444$4693
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:124444$4693_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:124446$4695
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:124446$4695_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:124449$4698
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:124449$4698_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:124455$4704
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:124455$4704_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:124433$4682
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:124433$4682_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:124451$4700
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:124451$4700_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:124437$4686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:124437$4686_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:124440$4689
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:124440$4689_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:124443$4692
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:124443$4692_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:124445$4694
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879"
switch \dec_MUL_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:124984$4720_Y
attribute \src "libresoc.v:124986.18-124986.110"
wire $or$libresoc.v:124986$4722_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \dec_SHIFT_ROT_sgn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 \dec_SHIFT_ROT_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \dec_bi_imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_bi_imm_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 \dec_bi_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_oe_oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec_rc_rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:124565.7-124565.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 19 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124973$4709
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:124973$4709_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124975$4711
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:124975$4711_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124988$4724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:124988$4724_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124989$4725
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:124989$4725_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124991$4727
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:124991$4727_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:124993$4729
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:124993$4729_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124994$4730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:124994$4730_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:124995$4731
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:124995$4731_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:124976$4712
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:124976$4712_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:124977$4713
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:124977$4713_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124979$4715
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:124979$4715_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124980$4716
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:124980$4716_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:124982$4718
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:124982$4718_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:124983$4719
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:124983$4719_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:124985$4721
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:124985$4721_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:124987$4723
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:124987$4723_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:124990$4726
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:124990$4726_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:124996$4732
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:124996$4732_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:124974$4710
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:124974$4710_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:124992$4728
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:124992$4728_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:124978$4714
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:124978$4714_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:124981$4717
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:124981$4717_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:124984$4720
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:124984$4720_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:124986$4722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:851"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879"
switch \dec_SHIFT_ROT_cr_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001 , 3'101
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:125420$4748_Y
attribute \src "libresoc.v:125422.18-125422.110"
wire $or$libresoc.v:125422$4750_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
wire \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
wire \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
wire \$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
wire \$8
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305"
wire width 32 \dec_opcode_in
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 \dec_rc_sel_in
attribute \src "libresoc.v:125115.7-125115.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
wire width 32 \insn_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:479"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
wire width 32 \insn_in$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842"
wire \is_mmu_spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:813"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841"
wire \is_spr_mv
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 input 6 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836"
wire width 10 \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:125409$4737
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$8
connect \Y $and$libresoc.v:125409$4737_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:125411$4739
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$12
connect \Y $and$libresoc.v:125411$4739_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:125424$4752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$36
connect \Y $and$libresoc.v:125424$4752_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:125425$4753
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:125425$4753_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:125427$4755
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$42
connect \Y $and$libresoc.v:125427$4755_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $and $and$libresoc.v:125429$4757
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$46
connect \Y $and$libresoc.v:125429$4757_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:125430$4758
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$2
connect \Y $and$libresoc.v:125430$4758_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $and $and$libresoc.v:125431$4759
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_mmu_spr
connect \Y $and$libresoc.v:125431$4759_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843"
cell $eq $eq$libresoc.v:125412$4740
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:125412$4740_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $eq $eq$libresoc.v:125413$4741
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101110
connect \Y $eq$libresoc.v:125413$4741_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:125415$4743
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10010
connect \Y $eq$libresoc.v:125415$4743_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:125416$4744
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 5'10011
connect \Y $eq$libresoc.v:125416$4744_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $eq $eq$libresoc.v:125418$4746
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'1011010000
connect \Y $eq$libresoc.v:125418$4746_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:125419$4747
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:125419$4747_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $eq $eq$libresoc.v:125421$4749
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 6'110000
connect \Y $eq$libresoc.v:125421$4749_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
cell $eq $eq$libresoc.v:125423$4751
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00010000000000
connect \Y $eq$libresoc.v:125423$4751_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:125426$4754
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:125426$4754_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $eq $eq$libresoc.v:125432$4760
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 14'00100000000000
connect \Y $eq$libresoc.v:125432$4760_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:125410$4738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:125410$4738_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854"
cell $not $not$libresoc.v:125428$4756
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_mmu_spr
connect \Y $not$libresoc.v:125428$4756_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844"
cell $or $or$libresoc.v:125414$4742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$18
connect \Y $or$libresoc.v:125414$4742_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:125417$4745
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$24
connect \Y $or$libresoc.v:125417$4745_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847"
cell $or $or$libresoc.v:125420$4748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$28
connect \Y $or$libresoc.v:125420$4748_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848"
cell $or $or$libresoc.v:125422$4750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$14 \$6 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850"
switch { \$48 \$40 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire $or$libresoc.v:125904$4773_Y
attribute \src "libresoc.v:125906.18-125906.110"
wire $or$libresoc.v:125906$4775_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
wire \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
wire \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
wire \$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
wire \$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
wire \$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
wire \$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 12 \BO
wire width 10 input 1 \SPR
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 10 input 13 \XL_XO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 8 \fast_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 9 \fast_a_ok
attribute \src "libresoc.v:125497.7-125497.15"
wire \initial
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 14 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
wire width 5 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 output 4 \reg_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \reg_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
wire width 5 \rs
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
wire width 3 input 3 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 10 \spr
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 6 \spr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 7 \spr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \sprmap_fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \sprmap_fast_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
wire width 10 \sprmap_spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \sprmap_spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \sprmap_spr_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116"
wire input 2 \sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $and $and$libresoc.v:125896$4765
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$9
connect \Y $and$libresoc.v:125896$4765_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $and $and$libresoc.v:125905$4774
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$25
connect \Y $and$libresoc.v:125905$4774_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
cell $and $and$libresoc.v:125910$4779
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$35
connect \Y $and$libresoc.v:125910$4779_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
cell $eq $eq$libresoc.v:125898$4767
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'100
connect \Y $eq$libresoc.v:125898$4767_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
cell $eq $eq$libresoc.v:125899$4768
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $eq$libresoc.v:125899$4768_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
cell $eq $eq$libresoc.v:125900$4769
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $eq$libresoc.v:125900$4769_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
cell $eq $eq$libresoc.v:125901$4770
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:125901$4770_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
cell $eq $eq$libresoc.v:125907$4776
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'100
connect \Y $eq$libresoc.v:125907$4776_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
cell $eq $eq$libresoc.v:125911$4780
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:125911$4780_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $ne $ne$libresoc.v:125902$4771
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $ne$libresoc.v:125902$4771_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $ne $ne$libresoc.v:125903$4772
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'0
connect \Y $ne$libresoc.v:125903$4772_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $ne $ne$libresoc.v:125912$4781
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $ne$libresoc.v:125912$4781_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $ne $ne$libresoc.v:125913$4782
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'0
connect \Y $ne$libresoc.v:125913$4782_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
cell $not $not$libresoc.v:125908$4777
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \BO [2]
connect \Y $not$libresoc.v:125908$4777_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
cell $not $not$libresoc.v:125909$4778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \XL_XO [5]
connect \Y $not$libresoc.v:125909$4778_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $or $or$libresoc.v:125895$4764
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$7
connect \Y $or$libresoc.v:125895$4764_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $or $or$libresoc.v:125897$4766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$11
connect \Y $or$libresoc.v:125897$4766_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $or $or$libresoc.v:125904$4773
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$23
connect \Y $or$libresoc.v:125904$4773_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
cell $or $or$libresoc.v:125906$4775
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
switch \$13
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\reg_a[4:0] 5'00000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
switch \$15
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
switch \$29
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\reg_a_ok[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
switch \$31
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111
assign { } { }
assign $1\fast_a[2:0] $2\fast_a[2:0]
assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
switch \$33
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fast_a[2:0] $3\fast_a[2:0]
assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
switch \$37
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111
wire $eq$libresoc.v:126084$4792_Y
attribute \src "libresoc.v:126086.17-126086.110"
wire $eq$libresoc.v:126086$4794_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 3 \ALU_RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire output 2 \immz_out
attribute \src "libresoc.v:126054.7-126054.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
wire width 5 \ra
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 input 1 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire input 4 \sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $and $and$libresoc.v:126082$4790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$7
connect \Y $and$libresoc.v:126082$4790_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $and $and$libresoc.v:126085$4793
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$3
connect \Y $and$libresoc.v:126085$4793_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126083$4791
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:126083$4791_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126084$4792
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $eq$libresoc.v:126084$4792_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $eq $eq$libresoc.v:126086$4794
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:126133$4799_Y
attribute \src "libresoc.v:126135.17-126135.110"
wire $eq$libresoc.v:126135$4801_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 3 \LOGICAL_RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire output 2 \immz_out
attribute \src "libresoc.v:126103.7-126103.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
wire width 5 \ra
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 input 1 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire input 4 \sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $and $and$libresoc.v:126131$4797
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$7
connect \Y $and$libresoc.v:126131$4797_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $and $and$libresoc.v:126134$4800
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$3
connect \Y $and$libresoc.v:126134$4800_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126132$4798
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:126132$4798_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126133$4799
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $eq$libresoc.v:126133$4799_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $eq $eq$libresoc.v:126135$4801
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:126182$4806_Y
attribute \src "libresoc.v:126184.17-126184.110"
wire $eq$libresoc.v:126184$4808_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 3 \DIV_RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire output 2 \immz_out
attribute \src "libresoc.v:126152.7-126152.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
wire width 5 \ra
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 input 1 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire input 4 \sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $and $and$libresoc.v:126180$4804
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$7
connect \Y $and$libresoc.v:126180$4804_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $and $and$libresoc.v:126183$4807
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$3
connect \Y $and$libresoc.v:126183$4807_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126181$4805
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:126181$4805_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126182$4806
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $eq$libresoc.v:126182$4806_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $eq $eq$libresoc.v:126184$4808
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:126231$4813_Y
attribute \src "libresoc.v:126233.17-126233.110"
wire $eq$libresoc.v:126233$4815_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 3 \LDST_RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire output 2 \immz_out
attribute \src "libresoc.v:126201.7-126201.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
wire width 5 \ra
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179"
wire width 3 input 1 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
wire input 4 \sv_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $and $and$libresoc.v:126229$4811
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$7
connect \Y $and$libresoc.v:126229$4811_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $and $and$libresoc.v:126232$4814
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \$3
connect \Y $and$libresoc.v:126232$4814_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126230$4812
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $eq$libresoc.v:126230$4812_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
cell $eq $eq$libresoc.v:126231$4813
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $eq$libresoc.v:126231$4813_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
cell $eq $eq$libresoc.v:126233$4815
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire width 7 $pos$libresoc.v:126378$4823_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 7 \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
wire \$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 7 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
wire \$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
wire \$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 7 \RB
wire width 5 input 6 \RS
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 10 input 8 \XL_XO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 4 \fast_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \fast_b_ok
attribute \src "libresoc.v:126250.7-126250.15"
wire \initial
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 9 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 output 2 \reg_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \reg_b_ok
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
wire width 4 input 1 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
cell $eq $eq$libresoc.v:126375$4818
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $eq$libresoc.v:126375$4818_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
cell $eq $eq$libresoc.v:126379$4824
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A \RS
connect \Y $extend$libresoc.v:126378$4822_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
cell $not $not$libresoc.v:126376$4819
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \XL_XO [9]
connect \Y $not$libresoc.v:126376$4819_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
cell $not $not$libresoc.v:126380$4825
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
switch \$5
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fast_b[2:0] $2\fast_b[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
switch { \XL_XO [5] \$7 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234"
switch \$9
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237"
switch { \XL_XO [5] \$11 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \ALU_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \ALU_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
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wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
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wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
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wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:126452.7-126452.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
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wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
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wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:126530$4831
connect \A \ALU_UI
connect \Y $extend$libresoc.v:126534$4837_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:126538$4842
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:126534$4837_Y
connect \Y $pos$libresoc.v:126534$4838_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:126538$4843
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:126538$4842_Y
connect \Y $pos$libresoc.v:126538$4843_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:126532$4835
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:126532$4835_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:126533$4836
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:126533$4836_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:126535$4839
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:126535$4839_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:126536$4840
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:126536$4840_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:126537$4841
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \BRANCH_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \BRANCH_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
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wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:126793.7-126793.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:126871$4853
connect \A \BRANCH_UI
connect \Y $extend$libresoc.v:126875$4859_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:126879$4864
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:126875$4859_Y
connect \Y $pos$libresoc.v:126875$4860_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:126879$4865
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:126879$4864_Y
connect \Y $pos$libresoc.v:126879$4865_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:126873$4857
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:126873$4857_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:126874$4858
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:126874$4858_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:126876$4861
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:126876$4861_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:126877$4862
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:126877$4862_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:126878$4863
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \LOGICAL_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \LOGICAL_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:127134.7-127134.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:127212$4875
connect \A \LOGICAL_UI
connect \Y $extend$libresoc.v:127216$4881_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:127220$4886
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:127216$4881_Y
connect \Y $pos$libresoc.v:127216$4882_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:127220$4887
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:127220$4886_Y
connect \Y $pos$libresoc.v:127220$4887_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:127214$4879
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:127214$4879_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:127215$4880
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:127215$4880_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:127217$4883
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127217$4883_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:127218$4884
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127218$4884_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:127219$4885
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \DIV_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \DIV_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:127475.7-127475.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:127553$4897
connect \A \DIV_UI
connect \Y $extend$libresoc.v:127557$4903_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:127561$4908
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:127557$4903_Y
connect \Y $pos$libresoc.v:127557$4904_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:127561$4909
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:127561$4908_Y
connect \Y $pos$libresoc.v:127561$4909_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:127555$4901
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:127555$4901_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:127556$4902
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:127556$4902_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:127558$4905
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127558$4905_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:127559$4906
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127559$4906_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:127560$4907
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \MUL_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \MUL_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:127816.7-127816.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:127894$4919
connect \A \MUL_UI
connect \Y $extend$libresoc.v:127898$4925_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:127902$4930
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:127898$4925_Y
connect \Y $pos$libresoc.v:127898$4926_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:127902$4931
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:127902$4930_Y
connect \Y $pos$libresoc.v:127902$4931_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:127896$4923
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:127896$4923_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:127897$4924
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:127897$4924_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:127899$4927
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127899$4927_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:127900$4928
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:127900$4928_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:127901$4929
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \SHIFT_ROT_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \SHIFT_ROT_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:128157.7-128157.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:128235$4941
connect \A \SHIFT_ROT_UI
connect \Y $extend$libresoc.v:128239$4947_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:128243$4952
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:128239$4947_Y
connect \Y $pos$libresoc.v:128239$4948_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:128243$4953
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:128243$4952_Y
connect \Y $pos$libresoc.v:128243$4953_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:128237$4945
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:128237$4945_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:128238$4946
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:128238$4946_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:128240$4949
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:128240$4949_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:128241$4950
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:128241$4950_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:128242$4951
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 64 \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 47 \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
wire width 27 \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
wire width 17 \$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 17 \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 64 \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
wire width 47 \$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 64 \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 64 \$9
wire width 16 input 4 \LDST_UI
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 6 input 6 \LDST_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
wire width 16 \bd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
wire width 16 \ds
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 1 \imm_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \imm_b_ok
attribute \src "libresoc.v:128498.7-128498.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280"
wire width 26 \li
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
wire width 4 input 10 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
wire width 16 \si
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 32 \si_hi
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
wire width 16 \ui
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
cell $pos $extend$libresoc.v:128576$4963
connect \A \LDST_UI
connect \Y $extend$libresoc.v:128580$4969_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $extend$libresoc.v:128584$4974
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $extend$libresoc.v:128580$4969_Y
connect \Y $pos$libresoc.v:128580$4970_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $pos $pos$libresoc.v:128584$4975
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:128584$4974_Y
connect \Y $pos$libresoc.v:128584$4975_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $sshl $sshl$libresoc.v:128578$4967
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $sshl$libresoc.v:128578$4967_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281"
cell $sshl $sshl$libresoc.v:128579$4968
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $sshl$libresoc.v:128579$4968_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
cell $sshl $sshl$libresoc.v:128581$4971
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:128581$4971_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
cell $sshl $sshl$libresoc.v:128582$4972
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $sshl$libresoc.v:128582$4972_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
cell $sshl $sshl$libresoc.v:128583$4973
parameter \A_SIGNED 0
parameter \A_WIDTH 16
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
wire width 5 input 3 \RS
attribute \src "libresoc.v:128839.7-128839.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 output 1 \reg_c
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \reg_c_ok
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:128839.7-128839.20"
process $proc$libresoc.v:128839$4987
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire $eq$libresoc.v:129036$4988_Y
attribute \src "libresoc.v:129038.17-129038.117"
wire $eq$libresoc.v:129038$4990_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
wire \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 12 \BA
wire width 8 input 14 \FXM
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 3 input 17 \X_BFA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 5 \cr_bitfield
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 7 \cr_bitfield_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 8 \cr_bitfield_b_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 9 \cr_bitfield_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 10 \cr_bitfield_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 6 \cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 output 3 \cr_fxm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \cr_fxm_ok
attribute \src "libresoc.v:128891.7-128891.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543"
wire width 32 input 1 \insn_in
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 18 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594"
wire \move_one
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 8 \ppick_i
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \enum_value_111 "CR1"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542"
wire width 3 input 2 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548"
wire width 2 \sv_override
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
cell $and $and$libresoc.v:129037$4989
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \move_one
connect \Y $and$libresoc.v:129037$4989_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
cell $and $and$libresoc.v:129039$4991
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \move_one
connect \Y $and$libresoc.v:129039$4991_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
cell $eq $eq$libresoc.v:129036$4988
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0101101
connect \Y $eq$libresoc.v:129036$4988_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
cell $eq $eq$libresoc.v:129038$4990
parameter \A_SIGNED 0
parameter \A_WIDTH 7
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'110
assign { } { }
assign $1\cr_fxm[7:0] $2\cr_fxm[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
switch \$7
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'110
assign { } { }
assign $1\ppick_i[7:0] $2\ppick_i[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:129554$5004_Y
attribute \src "libresoc.v:129555.17-129555.117"
wire $eq$libresoc.v:129555$5005_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 8 input 8 \FXM
wire width 5 input 10 \XL_BT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483"
wire width 3 input 9 \X_BF
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 6 \cr_bitfield
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 7 \cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 output 4 \cr_fxm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \cr_fxm_ok
attribute \src "libresoc.v:129431.7-129431.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618"
wire width 32 input 1 \insn_in
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 11 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:638"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659"
wire \move_one
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47"
wire \ppick_en_o
wire width 8 \ppick_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46"
wire width 8 \ppick_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616"
wire input 3 \rc_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \enum_value_101 "CR1"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617"
wire width 3 input 2 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621"
wire width 2 \sv_override
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
cell $eq $eq$libresoc.v:129554$5004
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110000
connect \Y $eq$libresoc.v:129554$5004_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
cell $eq $eq$libresoc.v:129555$5005
parameter \A_SIGNED 0
parameter \A_WIDTH 7
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'100
assign { } { }
assign $1\ppick_i[7:0] $2\ppick_i[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\ppick_i[7:0] $3\ppick_i[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662"
switch \move_one
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'100
assign { } { }
assign $1\cr_fxm[7:0] $2\cr_fxm[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\cr_fxm[7:0] $3\cr_fxm[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:641"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662"
switch \move_one
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $3\cr_fxm[7:0] $4\cr_fxm[7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:644"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
switch \ppick_en_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:130159$5016_Y
attribute \src "libresoc.v:130160.17-130160.104"
wire $not$libresoc.v:130160$5017_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
wire \$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
wire \$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386"
wire \$7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 11 \BO
wire width 5 input 9 \RT
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 10 input 1 \SPR
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 7 \fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 8 \fast_o_ok
attribute \src "libresoc.v:129797.7-129797.15"
wire \initial
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 12 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 output 3 \reg_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \reg_o_ok
attribute \enum_base_type "OutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RT_OR_ZERO"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351"
wire width 3 input 2 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
wire width 10 \spr
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 5 \spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 6 \spr_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \sprmap_fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \sprmap_fast_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
wire width 10 \sprmap_spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \sprmap_spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \sprmap_spr_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
cell $eq $eq$libresoc.v:130157$5014
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:130157$5014_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
cell $eq $eq$libresoc.v:130158$5015
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:130158$5015_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
cell $eq $eq$libresoc.v:130159$5016
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $eq$libresoc.v:130159$5016_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386"
cell $not $not$libresoc.v:130160$5017
parameter \A_SIGNED 0
parameter \A_WIDTH 1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
case 3'011
assign { } { }
assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign $1\spr_o[9:0] $2\spr_o[9:0]
assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign $1\fast_o[2:0] $2\fast_o[2:0]
assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376"
switch \$5
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $1\fast_o[2:0] 3'000
assign $1\fast_o_ok[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111 , 7'0001000
assign { } { }
assign $3\fast_o[2:0] $4\fast_o[2:0]
assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386"
switch \$7
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire $eq$libresoc.v:130423$5025_Y
attribute \src "libresoc.v:130424.17-130424.108"
wire $eq$libresoc.v:130424$5026_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
wire \$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
wire \$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470"
wire width 5 input 7 \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 4 \fast_o2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 5 \fast_o2_ok
attribute \src "libresoc.v:130318.7-130318.15"
wire \initial
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 8 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
wire input 1 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 5 output 2 \reg_o2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \reg_o2_ok
attribute \enum_base_type "LDSTMode"
attribute \enum_value_00 "NONE"
attribute \enum_value_11 "cx"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 2 input 6 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
cell $eq $eq$libresoc.v:130423$5025
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B 2'01
connect \Y $eq$libresoc.v:130423$5025_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
cell $eq $eq$libresoc.v:130424$5026
parameter \A_SIGNED 0
parameter \A_WIDTH 2
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
switch \$1
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
switch \$3
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111 , 7'0000110 , 7'0001000
assign { } { }
assign $1\fast_o2[2:0] $2\fast_o2[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
switch \lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0000111 , 7'0000110 , 7'0001000
assign { } { }
assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:421"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
switch \lk
attribute \src "libresoc.v:0.0-0.0"
case 1'1
wire width 7 input 1 \ALU_internal_op
attribute \src "libresoc.v:130490.7-130490.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:130490.7-130490.20"
process $proc$libresoc.v:130490$5034
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \ALU_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \ALU_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \CR_internal_op
attribute \src "libresoc.v:130629.7-130629.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 3 \sel_in
attribute \src "libresoc.v:130629.7-130629.20"
process $proc$libresoc.v:130629$5037
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \CR_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \CR_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \BRANCH_internal_op
attribute \src "libresoc.v:130766.7-130766.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 3 \sel_in
attribute \src "libresoc.v:130766.7-130766.20"
process $proc$libresoc.v:130766$5040
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \BRANCH_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \BRANCH_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \LOGICAL_internal_op
attribute \src "libresoc.v:130903.7-130903.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:130903.7-130903.20"
process $proc$libresoc.v:130903$5043
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \LOGICAL_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \LOGICAL_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \SPR_internal_op
attribute \src "libresoc.v:131042.7-131042.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 3 \sel_in
attribute \src "libresoc.v:131042.7-131042.20"
process $proc$libresoc.v:131042$5046
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \SPR_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \SPR_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \DIV_internal_op
attribute \src "libresoc.v:131179.7-131179.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:131179.7-131179.20"
process $proc$libresoc.v:131179$5049
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \DIV_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \DIV_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \MUL_internal_op
attribute \src "libresoc.v:131318.7-131318.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:131318.7-131318.20"
process $proc$libresoc.v:131318$5052
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \MUL_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \MUL_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \SHIFT_ROT_internal_op
attribute \src "libresoc.v:131457.7-131457.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:131457.7-131457.20"
process $proc$libresoc.v:131457$5055
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \SHIFT_ROT_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \SHIFT_ROT_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire width 7 input 1 \LDST_internal_op
attribute \src "libresoc.v:131596.7-131596.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:131596.7-131596.20"
process $proc$libresoc.v:131596$5058
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \LDST_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \LDST_internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
attribute \enum_value_1001100 "OP_SETVL"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189"
wire width 7 input 1 \internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 3 \oe_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
wire width 2 input 5 \sel_in
attribute \src "libresoc.v:131735.7-131735.20"
process $proc$libresoc.v:131735$5061
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe[0:0] $2\oe[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:487"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
switch \internal_op
attribute \src "libresoc.v:0.0-0.0"
case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000
case
assign { } { }
assign $1\oe_ok[0:0] $2\oe_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \ALU_Rc
attribute \src "libresoc.v:131874.7-131874.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:131874.7-131874.20"
process $proc$libresoc.v:131874$5064
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 1 \CR_Rc
attribute \src "libresoc.v:131932.7-131932.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 2 \sel_in
attribute \src "libresoc.v:131932.7-131932.20"
process $proc$libresoc.v:131932$5067
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 1 \BRANCH_Rc
attribute \src "libresoc.v:131988.7-131988.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 2 \sel_in
attribute \src "libresoc.v:131988.7-131988.20"
process $proc$libresoc.v:131988$5070
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \LOGICAL_Rc
attribute \src "libresoc.v:132044.7-132044.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132044.7-132044.20"
process $proc$libresoc.v:132044$5073
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 1 \SPR_Rc
attribute \src "libresoc.v:132102.7-132102.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 2 \sel_in
attribute \src "libresoc.v:132102.7-132102.20"
process $proc$libresoc.v:132102$5076
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \DIV_Rc
attribute \src "libresoc.v:132158.7-132158.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132158.7-132158.20"
process $proc$libresoc.v:132158$5079
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \MUL_Rc
attribute \src "libresoc.v:132216.7-132216.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132216.7-132216.20"
process $proc$libresoc.v:132216$5082
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \SHIFT_ROT_Rc
attribute \src "libresoc.v:132274.7-132274.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132274.7-132274.20"
process $proc$libresoc.v:132274$5085
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \LDST_Rc
attribute \src "libresoc.v:132332.7-132332.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132332.7-132332.20"
process $proc$libresoc.v:132332$5088
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire input 3 \Rc
attribute \src "libresoc.v:132390.7-132390.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 1 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \rc_ok
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 2 input 4 \sel_in
attribute \src "libresoc.v:132390.7-132390.20"
process $proc$libresoc.v:132390$5091
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
attribute \src "libresoc.v:0.0-0.0"
case 2'10
wire \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \all_rd_rise
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_div0_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \alu_div0_logical_op__data_len
wire \alu_div0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_div0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_div0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_div0_p_ready_o
wire width 64 \alu_div0_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_div0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_div0_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \alu_div0_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \alu_div0_xer_so$1
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 38 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 21 \cu_busy_o
wire output 37 \dest4_o
attribute \src "libresoc.v:132448.7-132448.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \src_sel$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 34 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 36 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
cell $and $and$libresoc.v:133101$5094
wire width 3 \_0_
attribute \src "libresoc.v:134113.13-134113.16"
wire width 3 \_1_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 14 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 12 \dest1__addr
attribute \nmigen.hierarchy "test_issuer.ti.core.fus"
attribute \generator "nMigen"
module \fus
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 330 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 257 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 258 \cr_a_ok$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 259 \cr_a_ok$111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 260 \cr_a_ok$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 261 \cr_a_ok$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 262 \cr_a_ok$114
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire input 3 \cu_ad__go_i
wire width 64 output 308 \dest5_o$149
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 2 output 273 \dest6_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 254 \ea
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 291 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 294 \fast1_ok$138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 295 \fast1_ok$139
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 296 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 297 \fast2_ok$140
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 255 \full_cr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 96 output 315 \ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 316 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire input 325 \ldst_port0_addr_ok_o
wire output 312 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire output 313 \ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 326 \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 327 \ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 328 \ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 329 \ldst_port0_st_data_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 307 \msr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 303 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 304 \nia_ok$146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 253 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 219 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 222 \o_ok$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 225 \o_ok$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 228 \o_ok$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 231 \o_ok$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 234 \o_ok$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 237 \o_ok$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 240 \o_ok$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 input 22 \oper_i_alu_alu0__data_len
wire input 153 \oper_i_ldst_ldst0__sign_extend
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire input 144 \oper_i_ldst_ldst0__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 309 \spr1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 185 \src1_i
wire width 2 input 203 \src6_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 4 input 212 \src6_i$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 269 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 270 \xer_ca_ok$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 271 \xer_ca_ok$121
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 275 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 276 \xer_ov_ok$124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 277 \xer_ov_ok$125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 278 \xer_ov_ok$126
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 283 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 284 \xer_so_ok$129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 285 \xer_so_ok$130
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 286 \xer_so_ok$131
attribute \module_not_derived 1
attribute \src "libresoc.v:135758.8-135800.4"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:136131.7-136131.15"
wire \initial
wire \a_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
wire input 3 \a_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 15 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
wire width 45 \f_badaddr_o
wire width 64 \ibus_rdata$next
attribute \src "libresoc.v:136193.7-136193.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire input 7 \wb_icache_en
wire width 5 \_0_
attribute \src "libresoc.v:138196.13-138196.16"
wire width 5 \_1_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 11 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 5 input 9 \dest1__addr
wire width 4 \_irblock_ir
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
wire \_irblock_tdo
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 282 \clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire input 6 \dmi0__ack_o
wire \posjtag_clk
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
wire \posjtag_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 94 \sdr_a_0__core__o
attribute \nmigen.hierarchy "test_issuer.ti.core.l0"
attribute \generator "nMigen"
module \l0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 23 \dbus__ack
wire output 25 \dbus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire output 29 \dbus__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 96 input 6 \ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 7 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire output 16 \ldst_port0_addr_ok_o
wire input 3 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire input 4 \ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 17 \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 18 \ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 19 \ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 20 \ldst_port0_st_data_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 48 \pimem_ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pimem_ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire \pimem_ldst_port0_addr_ok_o
wire \pimem_ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire \pimem_ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pimem_ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pimem_ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \pimem_ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \pimem_ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69"
wire width 64 \pimem_m_ld_data_o
wire width 96 \$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136"
wire width 96 \$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
wire \idx_l$23
wire \idx_l_s_idx_l
attribute \src "libresoc.v:141023.7-141023.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 96 input 6 \ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 48 output 25 \ldst_port0_addr_i$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 7 \ldst_port0_addr_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \ldst_port0_addr_i_ok$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire output 16 \ldst_port0_addr_ok_o
wire input 4 \ldst_port0_is_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire output 22 \ldst_port0_is_st_i$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 17 \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 28 \ldst_port0_ld_data_o$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 18 \ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 29 \ldst_port0_ld_data_o_ok$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126"
wire \ldst_port0_ldst_error
wire \ldst_port0_mmu_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
wire \ldst_port0_mmu_done$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 19 \ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 31 \ldst_port0_st_data_i$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 20 \ldst_port0_st_data_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \ldst_port0_st_data_i_ok$17
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
wire \pick_i
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:141435.7-141435.15"
wire \initial
wire \alu_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
wire \alu_valid
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34"
wire input 3 \cu_ad__go_i
wire width 64 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 64 \dest2_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 33 \ea
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
wire width 64 \ea_r
wire width 64 \ldo_r
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46"
wire width 64 \ldo_r$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 96 output 38 \ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 96 \ldst_port0_addr_i$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 39 \ldst_port0_addr_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \ldst_port0_addr_i_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire input 48 \ldst_port0_addr_ok_o
wire output 35 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire output 36 \ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 49 \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 50 \ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 51 \ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 52 \ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114"
wire \load_mem_o
wire \lsd_l_r_lsd$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \lsd_l_s_lsd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 32 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266"
wire \op_is_ld
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:143488.7-143488.15"
wire \initial
wire \alu_l_r_alu$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alu_l_s_alu
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_logical0_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \alu_logical0_logical_op__data_len
wire \alu_logical0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_logical0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_logical0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_logical0_p_ready_o
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 21 \cu_busy_o
wire width 4 output 33 \dest2_o
attribute \src "libresoc.v:143550.7-143550.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire $and$libresoc.v:145758$6791_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 53 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "libresoc.v:144674.7-144674.15"
wire \initial
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_ra
wire width 64 \main_rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \main_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_xer_so$62
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 4 \muxid
wire input 3 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 2 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 23 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 24 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 30 \p_ready_o
wire width 64 input 50 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 51 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 52 \xer_so$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:145758$6791
wire $and$libresoc.v:146871$6913_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 54 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 52 \cr_a$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$22$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 26 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 53 \cr_a_ok$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$23$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$73
attribute \src "libresoc.v:146069.7-146069.15"
wire \initial
wire input 30 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 29 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 23 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 50 \o$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 24 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 51 \o_ok$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$21$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \output_logical_op__data_len
wire width 2 \output_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire \r_busy$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 27 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 28 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$47
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:146871$6913
wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
attribute \src "ls180.v:4193.1-4298.4"
wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
- attribute \src "ls180.v:138.5-138.64"
+ attribute \src "ls180.v:134.5-134.64"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
- attribute \src "ls180.v:140.5-140.65"
+ attribute \src "ls180.v:136.5-136.65"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
- attribute \src "ls180.v:139.5-139.65"
+ attribute \src "ls180.v:135.5-135.65"
wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
- attribute \src "ls180.v:118.5-118.58"
+ attribute \src "ls180.v:121.5-121.58"
wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
attribute \src "ls180.v:4300.1-5506.4"
wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0]
attribute \src "ls180.v:1320.11-1320.55"
wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0]
- attribute \src "ls180.v:120.12-120.65"
+ attribute \src "ls180.v:118.12-118.65"
wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
- attribute \src "ls180.v:121.12-121.66"
+ attribute \src "ls180.v:119.12-119.66"
wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
attribute \src "ls180.v:122.12-122.66"
wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
attribute \src "ls180.v:126.5-126.61"
wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
- attribute \src "ls180.v:117.5-117.58"
+ attribute \src "ls180.v:120.5-120.58"
wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
attribute \src "ls180.v:55.12-55.50"
wire width 16 $1\libresocsim_libresoc_interrupt[15:0]
wire width 2 \dfi_p0_wrdata_mask
attribute \src "ls180.v:998.12-998.17"
wire width 36 \dummy
- attribute \src "ls180.v:30.13-30.19"
- wire input 26 \eint_0
- attribute \src "ls180.v:31.13-31.19"
- wire input 27 \eint_1
- attribute \src "ls180.v:32.13-32.19"
- wire input 28 \eint_2
+ attribute \src "ls180.v:26.13-26.19"
+ wire input 22 \eint_0
+ attribute \src "ls180.v:27.13-27.19"
+ wire input 23 \eint_1
+ attribute \src "ls180.v:28.13-28.19"
+ wire input 24 \eint_2
attribute \src "ls180.v:996.11-996.19"
wire width 3 \eint_tmp
attribute \src "ls180.v:884.12-884.34"
wire width 8 \gpio1_status
attribute \src "ls180.v:990.6-990.14"
wire \gpio1_we
- attribute \src "ls180.v:7.20-7.26"
- wire width 16 input 3 \gpio_i
- attribute \src "ls180.v:8.21-8.27"
- wire width 16 output 4 \gpio_o
- attribute \src "ls180.v:9.21-9.28"
- wire width 16 output 5 \gpio_oe
+ attribute \src "ls180.v:5.20-5.26"
+ wire width 16 input 1 \gpio_i
+ attribute \src "ls180.v:6.21-6.27"
+ wire width 16 output 2 \gpio_o
+ attribute \src "ls180.v:7.21-7.28"
+ wire width 16 output 3 \gpio_oe
attribute \src "ls180.v:1000.6-1000.12"
wire \i2c_oe
attribute \src "ls180.v:1003.5-1003.11"
wire \i2c_re
- attribute \src "ls180.v:22.14-22.21"
- wire output 18 \i2c_scl
+ attribute \src "ls180.v:29.14-29.21"
+ wire output 25 \i2c_scl
attribute \src "ls180.v:999.6-999.15"
wire \i2c_scl_1
attribute \src "ls180.v:1001.6-1001.14"
wire \i2c_sda0
attribute \src "ls180.v:1004.6-1004.14"
wire \i2c_sda1
- attribute \src "ls180.v:23.13-23.22"
- wire input 19 \i2c_sda_i
- attribute \src "ls180.v:24.14-24.23"
- wire output 20 \i2c_sda_o
- attribute \src "ls180.v:25.14-25.24"
- wire output 21 \i2c_sda_oe
+ attribute \src "ls180.v:30.13-30.22"
+ wire input 26 \i2c_sda_i
+ attribute \src "ls180.v:31.14-31.23"
+ wire output 27 \i2c_sda_o
+ attribute \src "ls180.v:32.14-32.24"
+ wire output 28 \i2c_sda_oe
attribute \src "ls180.v:1005.6-1005.16"
wire \i2c_status
attribute \src "ls180.v:1002.11-1002.22"
wire width 64 \libresocsim_libresoc2
attribute \src "ls180.v:115.12-115.40"
wire width 2 \libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:142.6-142.51"
+ attribute \src "ls180.v:138.6-138.51"
wire \libresocsim_libresoc_constraintmanager_eint_0
- attribute \src "ls180.v:143.6-143.51"
+ attribute \src "ls180.v:139.6-139.51"
wire \libresocsim_libresoc_constraintmanager_eint_1
- attribute \src "ls180.v:144.6-144.51"
+ attribute \src "ls180.v:140.6-140.51"
wire \libresocsim_libresoc_constraintmanager_eint_2
- attribute \src "ls180.v:119.13-119.58"
+ attribute \src "ls180.v:117.13-117.58"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i
- attribute \src "ls180.v:120.12-120.57"
+ attribute \src "ls180.v:118.12-118.57"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o
- attribute \src "ls180.v:121.12-121.58"
+ attribute \src "ls180.v:119.12-119.58"
wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe
- attribute \src "ls180.v:134.6-134.52"
+ attribute \src "ls180.v:141.6-141.52"
wire \libresocsim_libresoc_constraintmanager_i2c_scl
- attribute \src "ls180.v:135.6-135.54"
+ attribute \src "ls180.v:142.6-142.54"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_i
- attribute \src "ls180.v:136.6-136.54"
+ attribute \src "ls180.v:143.6-143.54"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_o
- attribute \src "ls180.v:137.6-137.55"
+ attribute \src "ls180.v:144.6-144.55"
wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe
attribute \src "ls180.v:122.12-122.58"
wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a
wire \libresocsim_libresoc_constraintmanager_sdram_ras_n
attribute \src "ls180.v:126.5-126.54"
wire \libresocsim_libresoc_constraintmanager_sdram_we_n
- attribute \src "ls180.v:138.5-138.57"
+ attribute \src "ls180.v:134.5-134.57"
wire \libresocsim_libresoc_constraintmanager_spimaster_clk
- attribute \src "ls180.v:140.5-140.58"
+ attribute \src "ls180.v:136.5-136.58"
wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n
- attribute \src "ls180.v:141.6-141.59"
+ attribute \src "ls180.v:137.6-137.59"
wire \libresocsim_libresoc_constraintmanager_spimaster_miso
- attribute \src "ls180.v:139.5-139.58"
+ attribute \src "ls180.v:135.5-135.58"
wire \libresocsim_libresoc_constraintmanager_spimaster_mosi
- attribute \src "ls180.v:118.5-118.51"
+ attribute \src "ls180.v:121.5-121.51"
wire \libresocsim_libresoc_constraintmanager_uart_rx
- attribute \src "ls180.v:117.5-117.51"
+ attribute \src "ls180.v:120.5-120.51"
wire \libresocsim_libresoc_constraintmanager_uart_tx
attribute \src "ls180.v:62.6-62.35"
wire \libresocsim_libresoc_dbus_ack
wire \socbushandler_reset
attribute \src "ls180.v:815.5-815.23"
wire \socbushandler_skip
- attribute \src "ls180.v:26.14-26.27"
- wire output 22 \spimaster_clk
- attribute \src "ls180.v:28.14-28.28"
- wire output 24 \spimaster_cs_n
- attribute \src "ls180.v:29.13-29.27"
- wire input 25 \spimaster_miso
- attribute \src "ls180.v:27.14-27.28"
- wire output 23 \spimaster_mosi
+ attribute \src "ls180.v:22.14-22.27"
+ wire output 18 \spimaster_clk
+ attribute \src "ls180.v:24.14-24.28"
+ wire output 20 \spimaster_cs_n
+ attribute \src "ls180.v:25.13-25.27"
+ wire input 21 \spimaster_miso
+ attribute \src "ls180.v:23.14-23.28"
+ wire output 19 \spimaster_mosi
attribute \src "ls180.v:1022.11-1022.47"
wire width 3 \subfragments_bankmachine0_next_state
attribute \src "ls180.v:1021.11-1021.42"
wire \uart_phy_uart_clk_rxen
attribute \src "ls180.v:843.5-843.27"
wire \uart_phy_uart_clk_txen
- attribute \src "ls180.v:6.13-6.20"
- wire input 2 \uart_rx
+ attribute \src "ls180.v:9.13-9.20"
+ wire input 5 \uart_rx
attribute \src "ls180.v:895.6-895.21"
wire \uart_sink_first
attribute \src "ls180.v:896.6-896.20"
wire \uart_source_ready
attribute \src "ls180.v:898.6-898.23"
wire \uart_source_valid
- attribute \src "ls180.v:5.13-5.20"
- wire input 1 \uart_tx
+ attribute \src "ls180.v:8.13-8.20"
+ wire input 4 \uart_tx
attribute \src "ls180.v:802.5-802.17"
wire \wb_sdram_ack
attribute \src "ls180.v:796.12-796.24"
sync init
update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:117.5-117.58"
- process $proc$ls180.v:117$1651
- assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
- sync always
- sync init
- update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
- end
attribute \src "ls180.v:1176.11-1176.55"
process $proc$ls180.v:1176$2084
assign { } { }
sync init
update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:118.5-118.58"
- process $proc$ls180.v:118$1652
+ attribute \src "ls180.v:118.12-118.65"
+ process $proc$ls180.v:118$1651
assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
sync always
- update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
sync init
+ update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
end
attribute \src "ls180.v:1189.11-1189.55"
process $proc$ls180.v:1189$2085
sync init
update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
end
- attribute \src "ls180.v:120.12-120.65"
+ attribute \src "ls180.v:119.12-119.66"
+ process $proc$ls180.v:119$1652
+ assign { } { }
+ assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+ sync always
+ sync init
+ update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+ end
+ attribute \src "ls180.v:120.5-120.58"
process $proc$ls180.v:120$1653
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
+ assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
sync always
sync init
- update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+ update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
end
- attribute \src "ls180.v:121.12-121.66"
+ attribute \src "ls180.v:121.5-121.58"
process $proc$ls180.v:121$1654
assign { } { }
- assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+ assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
sync always
+ update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
sync init
- update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
end
attribute \src "ls180.v:122.12-122.66"
process $proc$ls180.v:122$1655
sync init
update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
end
+ attribute \src "ls180.v:134.5-134.64"
+ process $proc$ls180.v:134$1666
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
+ sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
+ sync init
+ end
attribute \src "ls180.v:1342.11-1342.35"
process $proc$ls180.v:1342$2089
assign { } { }
sync init
update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0]
end
+ attribute \src "ls180.v:135.5-135.65"
+ process $proc$ls180.v:135$1667
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
+ sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
+ sync init
+ end
attribute \src "ls180.v:1350.5-1350.28"
process $proc$ls180.v:1350$2097
assign { } { }
sync init
update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0]
end
+ attribute \src "ls180.v:136.5-136.65"
+ process $proc$ls180.v:136$1668
+ assign { } { }
+ assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
+ sync always
+ update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
+ sync init
+ end
attribute \src "ls180.v:1360.12-1360.36"
process $proc$ls180.v:1360$2107
assign { } { }
sync init
update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0]
end
- attribute \src "ls180.v:138.5-138.64"
- process $proc$ls180.v:138$1666
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
- sync init
- end
attribute \src "ls180.v:1380.12-1380.37"
process $proc$ls180.v:1380$2127
assign { } { }
sync init
update \array_muxed1 $1\array_muxed1[12:0]
end
- attribute \src "ls180.v:139.5-139.65"
- process $proc$ls180.v:139$1667
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
- sync init
- end
attribute \src "ls180.v:1390.5-1390.24"
process $proc$ls180.v:1390$2137
assign { } { }
sync init
update \array_muxed6 $1\array_muxed6[0:0]
end
- attribute \src "ls180.v:140.5-140.65"
- process $proc$ls180.v:140$1668
- assign { } { }
- assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
- sync always
- update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
- sync init
- end
attribute \src "ls180.v:1451.32-1451.44"
process $proc$ls180.v:1451$2142
assign { } { }
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:147106.7-147106.15"
wire \initial
wire \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154"
wire \$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 21 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 13 \dbus__ack
wire \carry_32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101"
wire \carry_64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 44 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 45 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178"
wire width 8 \eqs
wire width 2 input 51 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 23 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 42 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 43 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156"
wire width 2 \ov
wire width 5 \tval
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 22 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 46 \xer_ca$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 47 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 48 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 49 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 21 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 50 \xer_so$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103"
wire \zerohi
wire width 2 input 44 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 22 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 40 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 41 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 18 \ra
wire input 9 \sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire output 31 \sr_op__write_cr0$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 43 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 21 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 42 \xer_so$19
attribute \module_not_derived 1
attribute \src "libresoc.v:149057.11-149072.4"
wire \ctr_zero_bo1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 9 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 21 \fast1$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 22 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 10 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 23 \fast2$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 24 \fast2_ok
attribute \src "libresoc.v:149161.7-149161.15"
wire \initial
wire width 2 input 27 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 12 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 25 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95"
cell $add $add$libresoc.v:149466$7306
wire \equal
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 12 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 26 \fast1$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 13 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 28 \fast2$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
wire \gt_s
wire \lt_s
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
wire \lt_u
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 32 \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 34 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 14 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 30 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 24 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 10 \ra
wire width 2 input 44 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 22 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 41 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 42 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84"
wire \par0
wire width 64 input 20 \rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 21 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 43 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
cell $and $and$libresoc.v:151167$7489
wire width 2 \bt
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 7 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 18 \cr_a$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 19 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 8 \cr_b
wire width 7 output 11 \cr_op__insn_type$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 input 6 \full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 output 16 \full_cr$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 17 \full_cr_ok
attribute \src "libresoc.v:151652.7-151652.15"
wire \initial
wire width 2 input 20 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 10 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 14 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 15 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 4 \ra
wire \alu_l_r_alu$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alu_l_s_alu
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_mul0_cr_a
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \alu_mul0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_mul0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_mul0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_mul0_p_ready_o
wire width 64 \alu_mul0_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_mul0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_mul0_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \alu_mul0_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \alu_mul0_xer_so$1
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 15 \cu_busy_o
wire output 31 \dest4_o
attribute \src "libresoc.v:152259.7-152259.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 22 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
cell $and $and$libresoc.v:152856$7573
wire input 15 \neg_res
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 129 input 13 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 29 \o$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 31 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 14 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \xer_so$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 34 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65"
cell $and $and$libresoc.v:154321$7857
wire $and$libresoc.v:155386$7872_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:154441.7-154441.15"
wire \initial
wire $and$libresoc.v:156362$7965_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 41 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:155662.7-155662.15"
wire \initial
wire $and$libresoc.v:157582$8085_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 44 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 38 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 39 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "libresoc.v:156586.7-156586.15"
wire \initial
wire \mul3_neg_res
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 129 \mul3_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \mul3_o$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul3_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \mul3_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul3_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \mul3_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul3_xer_so$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \mul3_xer_so_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \neg_res32$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 129 input 17 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 36 \o$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$14$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 37 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_cr_a_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire width 2 \output_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire \r_busy$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 40 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 41 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 18 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 42 \xer_so$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$15$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 43 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:157582$8085
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158276.7-158276.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158338.7-158338.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158400.7-158400.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158462.7-158462.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158524.7-158524.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158586.7-158586.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158648.7-158648.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158710.7-158710.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158772.7-158772.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:158834.7-158834.15"
wire \initial
wire width 65 \$29
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 64 \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 65 \$33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire \$35
wire output 35 \alu_op__zero_a$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 21 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 46 \cr_a$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 47 \cr_a_ok
attribute \src "libresoc.v:158896.7-158896.15"
wire \initial
wire width 2 input 54 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 25 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 19 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 44 \o$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38"
wire width 65 \o$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 20 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 45 \o_ok$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28"
wire \oe
wire \so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 22 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 48 \xer_ca$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 49 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 23 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 50 \xer_ov$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 51 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 24 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 52 \xer_so$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 53 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
cell $and $and$libresoc.v:159247$8389
connect \A \$30
connect \Y $extend$libresoc.v:159249$8391_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:159250$8393
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:159249$8391_Y
connect \Y $pos$libresoc.v:159249$8392_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:159250$8394
parameter \A_SIGNED 0
parameter \A_WIDTH 65
wire $reduce_or$libresoc.v:159671$8423_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 65 \$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire \$24
wire \$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 15 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 33 \cr_a$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 34 \cr_a_ok
attribute \src "libresoc.v:159358.7-159358.15"
wire \initial
wire width 2 input 39 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 18 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 13 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 31 \o$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38"
wire width 65 \o$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 14 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \o_ok$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28"
wire \oe
wire \so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 16 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 35 \xer_ov$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 36 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 17 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 37 \xer_so$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 38 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
cell $and $and$libresoc.v:159667$8418
connect \B 7'0001100
connect \Y $eq$libresoc.v:159670$8422_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:159668$8419
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \xer_ov [0]
connect \Y $or$libresoc.v:159677$8429_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:159668$8420
parameter \A_SIGNED 0
parameter \A_WIDTH 65
wire width 65 $pos$libresoc.v:160080$8442_Y
attribute \src "libresoc.v:160083.18-160083.105"
wire $reduce_or$libresoc.v:160083$8445_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire \$26
wire \$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 20 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 43 \cr_a$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 44 \cr_a_ok
attribute \src "libresoc.v:159763.7-159763.15"
wire \initial
wire width 2 input 47 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 23 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 18 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 41 \o$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38"
wire width 65 \o$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 19 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 42 \o_ok$20
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire output 32 \sr_op__write_cr0$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 22 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 45 \xer_ca$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 46 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 21 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
cell $and $and$libresoc.v:160085$8447
connect \B 7'0001100
connect \Y $eq$libresoc.v:160082$8444_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:160080$8441
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \is_cmp
connect \Y $or$libresoc.v:160086$8448_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:160080$8442
parameter \A_SIGNED 0
parameter \A_WIDTH 65
wire width 65 \$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 64 \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 65 \$28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire \$30
wire \$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 21 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 44 \cr_a$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 45 \cr_a_ok
attribute \src "libresoc.v:160121.7-160121.15"
wire \initial
wire width 2 input 46 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 23 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 19 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 42 \o$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38"
wire width 65 \o$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 20 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 43 \o_ok$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 22 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83"
cell $and $and$libresoc.v:160447$8461
connect \A \$25
connect \Y $extend$libresoc.v:160441$8453_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:160442$8455
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:160441$8453_Y
connect \Y $pos$libresoc.v:160441$8454_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:160442$8456
parameter \A_SIGNED 0
parameter \A_WIDTH 65
wire width 65 \$28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 64 \$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 65 \$32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
wire \$34
wire \$51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 21 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 45 \cr_a$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 46 \cr_a_ok
attribute \src "libresoc.v:160492.7-160492.15"
wire \initial
wire width 2 input 51 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 24 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 19 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 43 \o$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38"
wire width 65 \o$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 20 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 44 \o_ok$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28"
wire \oe
wire \so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 22 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 47 \xer_ov$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 48 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 23 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 49 \xer_so$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 50 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
cell $and $and$libresoc.v:160837$8469
connect \A \$29
connect \Y $extend$libresoc.v:160839$8471_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $extend$libresoc.v:160840$8473
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $extend$libresoc.v:160839$8471_Y
connect \Y $pos$libresoc.v:160839$8472_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
cell $pos $pos$libresoc.v:160840$8474
parameter \A_SIGNED 0
parameter \A_WIDTH 65
wire width 2 input 51 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 27 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 46 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 47 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75"
wire \ov
wire width 32 \remainder_s32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99"
wire width 64 \remainder_s32_as_s64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 48 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 49 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 19 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 50 \xer_so$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
cell $and $and$libresoc.v:161299$8511
wire \busy_l_r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \busy_l_s_busy
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 23 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \cyc_l_q_cyc
wire \lds_dly$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61"
wire \lds_rise
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 48 input 6 \ldst_port0_addr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 7 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109"
wire output 10 \ldst_port0_addr_ok_o
wire input 2 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire input 3 \ldst_port0_is_st_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 12 \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 13 \ldst_port0_ld_data_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 15 \ldst_port0_st_data_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 14 \ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
wire width 4 \lenexp_addr_i
wire $and$libresoc.v:163272$8663_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 26 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 11 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 24 \cr_a$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 12 \cr_b
wire width 7 \cr_op__insn_type$2$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 input 10 \full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \full_cr$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 output 22 \full_cr$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \full_cr$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \full_cr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \full_cr_ok$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \full_cr_ok$next
attribute \src "libresoc.v:162667.7-162667.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \main_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \main_cr_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 \main_cr_b
wire width 7 \main_cr_op__insn_type$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 32 \main_full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \main_full_cr$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_full_cr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_ra
wire input 15 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 14 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 20 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 21 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire output 25 \br_op__lk$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \br_op__lk$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 33 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 4 input 15 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 13 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 27 \fast1$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 14 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 29 \fast2$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast2$11$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast2$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast2_ok$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast2_ok$next
attribute \src "libresoc.v:163451.7-163451.15"
wire \initial
wire width 4 \main_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_fast1$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_fast2$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
wire input 17 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 16 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 31 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \nia$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \nia$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \nia_ok$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \nia_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire $and$libresoc.v:164987$8831_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 11 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 26 \fast1$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$next
attribute \src "libresoc.v:164315.7-164315.15"
wire \initial
wire input 16 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 15 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 22 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire width 64 input 9 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 10 \spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \spr1$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 24 \spr1$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \spr1$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \spr1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr1_ok$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr1_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \spr_main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \spr_main_fast1$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \spr_main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \spr_main_muxid$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \spr_main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \spr_main_ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \spr_main_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \spr_main_spr1$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_spr1_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \spr_main_spr_op__is_32bit$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \spr_main_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \spr_main_xer_ca$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \spr_main_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \spr_main_xer_ov$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \spr_main_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_xer_so$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \spr_main_xer_so_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \spr_op__is_32bit$5$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 14 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 32 \xer_ca$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 13 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 30 \xer_ov$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$9$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 12 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \xer_so$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:164987$8831
wire \alu_op__zero_a$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "libresoc.v:165249.7-165249.15"
wire \initial
wire \main_alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \main_alu_op__zero_a$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \main_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_ra
wire width 64 \main_rb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \main_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \main_xer_ca$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \main_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \main_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_xer_so$65
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 4 \muxid
wire input 3 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 2 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 23 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 24 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 34 \p_ready_o
wire width 64 input 54 \ra
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 55 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 27 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 57 \xer_ca$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 29 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 56 \xer_so$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 32 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:166377$8941
wire $and$libresoc.v:167846$9083_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 55 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 24 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "libresoc.v:166745.7-166745.15"
wire \initial
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_ra
wire \main_sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \main_sr_op__write_cr0$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \main_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \main_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_xer_so$62
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 4 \muxid
wire input 3 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 2 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 22 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 31 \p_ready_o
wire \sr_op__write_cr0$76
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \sr_op__write_cr0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 28 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 54 \xer_ca$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \xer_ca$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 26 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 53 \xer_so$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:167846$9083
wire $and$libresoc.v:168842$9211_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 34 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \dummy_fast1
wire \alu_op__zero_a$11$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_op__zero_a$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 64 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 25 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 56 \cr_a$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$22$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 26 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 57 \cr_a_ok$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$23$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$84
attribute \src "libresoc.v:169037.7-169037.15"
wire \initial
wire input 34 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 33 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 23 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 54 \o$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 24 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 55 \o_ok$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$21$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \output_alu_op__data_len
wire \output_alu_op__zero_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \output_alu_op__zero_a$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ca$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire \r_busy$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 27 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 58 \xer_ca$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$24$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 28 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 59 \xer_ca_ok$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$25$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 29 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 60 \xer_ov$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$26$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 30 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 61 \xer_ov_ok$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$27$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 31 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 62 \xer_so$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$28$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 32 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 63 \xer_so_ok$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$29$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$90
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:169909$9281
wire $and$libresoc.v:171041$9481_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 56 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 input 24 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 52 \cr_a$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$21$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 25 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 53 \cr_a_ok$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$22$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$74
attribute \src "libresoc.v:170226.7-170226.15"
wire \initial
wire input 31 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 30 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 22 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 50 \o$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$19$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 23 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 51 \o_ok$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok$44
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire \output_sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \output_sr_op__write_cr0$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ca$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire \sr_op__write_cr0$10$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \sr_op__write_cr0$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 input 28 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 54 \xer_ca$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$23$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ca$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 29 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 55 \xer_ca_ok$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$24$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ca_ok$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 26 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 27 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$48
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:171041$9481
wire $and$libresoc.v:172010$9647_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 40 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 16 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 32 \fast1$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$11$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast1$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 17 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 34 \fast2$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast2$12$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \fast2$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 35 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast2_ok$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \fast2_ok$next
attribute \src "libresoc.v:171299.7-171299.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_fast1$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_fast2$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \main_muxid$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \main_ra
wire width 8 \main_trap_op__traptype
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 8 \main_trap_op__traptype$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 38 \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \msr$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \msr$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 39 \msr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \msr_ok$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \msr_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 4 \muxid
wire input 19 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 18 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 36 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \nia$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \nia$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 37 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \nia_ok$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \nia_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 30 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 31 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire $and$libresoc.v:173417$9771_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 62 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 output 56 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 57 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire input 30 \div_by_zero
wire input 34 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire output 33 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 54 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 55 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \o_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \output_cr_a$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire width 4 \output_logical_op__data_len
wire width 2 \output_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_muxid$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_o$60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_o_ok$61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire \output_stage_div_by_zero
wire width 2 \output_stage_muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 \output_stage_muxid$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \output_stage_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_stage_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
wire width 64 \output_stage_quotient_root
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
wire width 192 \output_stage_remainder
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_stage_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_stage_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \output_stage_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_stage_xer_so$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \output_xer_ov$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \output_xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire output 3 \p_ready_o
wire width 64 \rb$66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
wire width 192 input 32 \remainder
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 58 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \xer_ov$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 59 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 25 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 60 \xer_so$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 61 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
cell $and $and$libresoc.v:173417$9771
wire \$63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 65 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire input 30 \div_by_zero
wire $and$libresoc.v:175894$10201_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 58 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
wire output 30 \div_by_zero
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest10__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest10__data_i
wire width 64 \cia0__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia0__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr10__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest11__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest11__data_i
wire width 64 \cia1__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia1__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr11__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest12__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 9 \dest12__data_i
wire width 64 \cia2__data_o$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 2 \cia2__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 15 \d_wr12__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest13__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest14__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest15__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest16__data_i
wire \$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 18 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 4 input 9 \dest17__data_i
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:183910.7-183910.15"
wire \initial
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:183972.7-183972.15"
wire \initial
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184034.7-184034.15"
wire \initial
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184096.7-184096.15"
wire \initial
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184158.7-184158.15"
wire \initial
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184220.7-184220.15"
wire \initial
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184282.7-184282.15"
wire \initial
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184344.7-184344.15"
wire \initial
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184406.7-184406.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184468.7-184468.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:184521.7-184521.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185165.7-185165.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185227.7-185227.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185289.7-185289.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185351.7-185351.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185413.7-185413.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185475.7-185475.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185537.7-185537.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185599.7-185599.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:185661.7-185661.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186105.7-186105.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186167.7-186167.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186229.7-186229.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186291.7-186291.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186353.7-186353.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186415.7-186415.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186477.7-186477.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186539.7-186539.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186601.7-186601.15"
wire \initial
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 4 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:186663.7-186663.15"
wire \initial
wire \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \alu_pulsem
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 4 \alu_shift_rot0_cr_a
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
wire \alu_shift_rot0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_shift_rot0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_shift_rot0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_shift_rot0_p_ready_o
wire \alu_shift_rot0_sr_op__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_shift_rot0_sr_op__write_cr0$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_shift_rot0_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \alu_shift_rot0_xer_ca$1
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 37 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 33 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 20 \cu_busy_o
wire width 2 output 36 \dest3_o
attribute \src "libresoc.v:187138.7-187138.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 35 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
cell $and $and$libresoc.v:187773$12257
connect \all_rd_dly$next \all_rd
connect \all_rd \$10
end
-attribute \src "libresoc.v:188348.1-188528.10"
+attribute \src "libresoc.v:188348.1-188424.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.spr"
attribute \generator "nMigen"
module \spr
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 7 $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 64 $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 64 $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 7 $0\_0_[6:0]
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 4 $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 64 $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 4 $0\_0_[3:0]
attribute \src "libresoc.v:188349.7-188349.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:188505.3-188513.6"
- wire $0\ren_delay$next[0:0]$12649
- attribute \src "libresoc.v:188503.3-188504.35"
+ attribute \src "libresoc.v:188401.3-188409.6"
+ wire $0\ren_delay$next[0:0]$12545
+ attribute \src "libresoc.v:188399.3-188400.35"
wire $0\ren_delay[0:0]
- attribute \src "libresoc.v:188514.3-188523.6"
+ attribute \src "libresoc.v:188410.3-188419.6"
wire width 64 $0\spr1__data_o[63:0]
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 7 $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 64 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644
- attribute \src "libresoc.v:188498.3-188501.6"
- wire width 64 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645
- attribute \src "libresoc.v:188505.3-188513.6"
- wire $1\ren_delay$next[0:0]$12650
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 4 $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540
+ attribute \src "libresoc.v:188394.3-188397.6"
+ wire width 64 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541
+ attribute \src "libresoc.v:188401.3-188409.6"
+ wire $1\ren_delay$next[0:0]$12546
attribute \src "libresoc.v:188365.7-188365.23"
wire $1\ren_delay[0:0]
- attribute \src "libresoc.v:188514.3-188523.6"
+ attribute \src "libresoc.v:188410.3-188419.6"
wire width 64 $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:188502.26-188502.32"
- wire width 64 $memrd$\memory$libresoc.v:188502$12646_DATA
+ attribute \src "libresoc.v:188398.26-188398.32"
+ wire width 64 $memrd$\memory$libresoc.v:188398$12542_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 7 $memwr$\memory$libresoc.v:188500$12638_ADDR
+ wire width 4 $memwr$\memory$libresoc.v:188396$12534_ADDR
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:188500$12638_DATA
+ wire width 64 $memwr$\memory$libresoc.v:188396$12534_DATA
attribute \src "libresoc.v:0.0-0.0"
- wire width 64 $memwr$\memory$libresoc.v:188500$12638_EN
- attribute \src "libresoc.v:188497.13-188497.16"
- wire width 7 \_0_
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ wire width 64 $memwr$\memory$libresoc.v:188396$12534_EN
+ attribute \src "libresoc.v:188393.13-188393.16"
+ wire width 4 \_0_
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 8 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "libresoc.v:188349.7-188349.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
- wire width 7 \memory_r_addr
+ wire width 4 \memory_r_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210"
wire width 64 \memory_r_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
- wire width 7 \memory_w_addr
+ wire width 4 \memory_w_addr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
wire width 64 \memory_w_data
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243"
wire \ren_delay$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 7 input 3 \spr1__addr
+ wire width 4 input 3 \spr1__addr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- wire width 7 input 6 \spr1__addr$1
+ wire width 4 input 6 \spr1__addr$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 5 \spr1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire input 7 \spr1__wen
attribute \src "libresoc.v:188381.14-188381.20"
- memory width 64 size 113 \memory
+ memory width 64 size 9 \memory
attribute \src "libresoc.v:188383.5-188383.37"
- cell $meminit $meminit$\memory$libresoc.v:188383$12652
+ cell $meminit $meminit$\memory$libresoc.v:188383$12548
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12548
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 0
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188384.5-188384.37"
- cell $meminit $meminit$\memory$libresoc.v:188384$12653
+ cell $meminit $meminit$\memory$libresoc.v:188384$12549
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12549
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 1
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188385.5-188385.37"
- cell $meminit $meminit$\memory$libresoc.v:188385$12654
+ cell $meminit $meminit$\memory$libresoc.v:188385$12550
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12550
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 2
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188386.5-188386.37"
- cell $meminit $meminit$\memory$libresoc.v:188386$12655
+ cell $meminit $meminit$\memory$libresoc.v:188386$12551
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12551
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 3
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188387.5-188387.37"
- cell $meminit $meminit$\memory$libresoc.v:188387$12656
+ cell $meminit $meminit$\memory$libresoc.v:188387$12552
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12552
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 4
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188388.5-188388.37"
- cell $meminit $meminit$\memory$libresoc.v:188388$12657
+ cell $meminit $meminit$\memory$libresoc.v:188388$12553
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12553
parameter \WIDTH 64
parameter \WORDS 1
connect \ADDR 5
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188389.5-188389.37"
- cell $meminit $meminit$\memory$libresoc.v:188389$12658
+ cell $meminit $meminit$\memory$libresoc.v:188389$12554
parameter \ABITS 32
parameter \MEMID "\\memory"
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+ parameter \PRIORITY 12554
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connect \ADDR 6
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188390.5-188390.37"
- cell $meminit $meminit$\memory$libresoc.v:188390$12659
+ cell $meminit $meminit$\memory$libresoc.v:188390$12555
parameter \ABITS 32
parameter \MEMID "\\memory"
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connect \ADDR 7
connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \src "libresoc.v:188391.5-188391.37"
- cell $meminit $meminit$\memory$libresoc.v:188391$12660
+ cell $meminit $meminit$\memory$libresoc.v:188391$12556
parameter \ABITS 32
parameter \MEMID "\\memory"
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parameter \WORDS 1
connect \ADDR 8
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- parameter \PRIORITY 12711
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 59
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188443.5-188443.38"
- cell $meminit $meminit$\memory$libresoc.v:188443$12712
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12712
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 60
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188444.5-188444.38"
- cell $meminit $meminit$\memory$libresoc.v:188444$12713
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12713
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 61
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188445.5-188445.38"
- cell $meminit $meminit$\memory$libresoc.v:188445$12714
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12714
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 62
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188446.5-188446.38"
- cell $meminit $meminit$\memory$libresoc.v:188446$12715
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12715
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 63
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188447.5-188447.38"
- cell $meminit $meminit$\memory$libresoc.v:188447$12716
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12716
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 64
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188448.5-188448.38"
- cell $meminit $meminit$\memory$libresoc.v:188448$12717
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12717
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 65
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188449.5-188449.38"
- cell $meminit $meminit$\memory$libresoc.v:188449$12718
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12718
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 66
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188450.5-188450.38"
- cell $meminit $meminit$\memory$libresoc.v:188450$12719
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12719
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 67
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188451.5-188451.38"
- cell $meminit $meminit$\memory$libresoc.v:188451$12720
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12720
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 68
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188452.5-188452.38"
- cell $meminit $meminit$\memory$libresoc.v:188452$12721
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12721
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 69
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188453.5-188453.38"
- cell $meminit $meminit$\memory$libresoc.v:188453$12722
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12722
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 70
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188454.5-188454.38"
- cell $meminit $meminit$\memory$libresoc.v:188454$12723
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12723
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 71
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188455.5-188455.38"
- cell $meminit $meminit$\memory$libresoc.v:188455$12724
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12724
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 72
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188456.5-188456.38"
- cell $meminit $meminit$\memory$libresoc.v:188456$12725
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12725
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 73
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188457.5-188457.38"
- cell $meminit $meminit$\memory$libresoc.v:188457$12726
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12726
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 74
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188458.5-188458.38"
- cell $meminit $meminit$\memory$libresoc.v:188458$12727
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12727
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 75
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188459.5-188459.38"
- cell $meminit $meminit$\memory$libresoc.v:188459$12728
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12728
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 76
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188460.5-188460.38"
- cell $meminit $meminit$\memory$libresoc.v:188460$12729
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12729
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 77
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188461.5-188461.38"
- cell $meminit $meminit$\memory$libresoc.v:188461$12730
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12730
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 78
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188462.5-188462.38"
- cell $meminit $meminit$\memory$libresoc.v:188462$12731
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12731
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 79
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188463.5-188463.38"
- cell $meminit $meminit$\memory$libresoc.v:188463$12732
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12732
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 80
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188464.5-188464.38"
- cell $meminit $meminit$\memory$libresoc.v:188464$12733
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12733
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 81
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188465.5-188465.38"
- cell $meminit $meminit$\memory$libresoc.v:188465$12734
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12734
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 82
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188466.5-188466.38"
- cell $meminit $meminit$\memory$libresoc.v:188466$12735
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12735
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 83
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188467.5-188467.38"
- cell $meminit $meminit$\memory$libresoc.v:188467$12736
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12736
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 84
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188468.5-188468.38"
- cell $meminit $meminit$\memory$libresoc.v:188468$12737
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12737
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 85
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188469.5-188469.38"
- cell $meminit $meminit$\memory$libresoc.v:188469$12738
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12738
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 86
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188470.5-188470.38"
- cell $meminit $meminit$\memory$libresoc.v:188470$12739
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12739
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 87
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188471.5-188471.38"
- cell $meminit $meminit$\memory$libresoc.v:188471$12740
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12740
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 88
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188472.5-188472.38"
- cell $meminit $meminit$\memory$libresoc.v:188472$12741
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12741
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 89
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188473.5-188473.38"
- cell $meminit $meminit$\memory$libresoc.v:188473$12742
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12742
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 90
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188474.5-188474.38"
- cell $meminit $meminit$\memory$libresoc.v:188474$12743
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12743
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 91
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188475.5-188475.38"
- cell $meminit $meminit$\memory$libresoc.v:188475$12744
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12744
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 92
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188476.5-188476.38"
- cell $meminit $meminit$\memory$libresoc.v:188476$12745
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12745
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 93
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188477.5-188477.38"
- cell $meminit $meminit$\memory$libresoc.v:188477$12746
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12746
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 94
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188478.5-188478.38"
- cell $meminit $meminit$\memory$libresoc.v:188478$12747
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12747
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 95
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188479.5-188479.38"
- cell $meminit $meminit$\memory$libresoc.v:188479$12748
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12748
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 96
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188480.5-188480.38"
- cell $meminit $meminit$\memory$libresoc.v:188480$12749
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12749
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 97
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188481.5-188481.38"
- cell $meminit $meminit$\memory$libresoc.v:188481$12750
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12750
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 98
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188482.5-188482.38"
- cell $meminit $meminit$\memory$libresoc.v:188482$12751
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12751
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 99
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188483.5-188483.39"
- cell $meminit $meminit$\memory$libresoc.v:188483$12752
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12752
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 100
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188484.5-188484.39"
- cell $meminit $meminit$\memory$libresoc.v:188484$12753
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12753
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 101
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188485.5-188485.39"
- cell $meminit $meminit$\memory$libresoc.v:188485$12754
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12754
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 102
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188486.5-188486.39"
- cell $meminit $meminit$\memory$libresoc.v:188486$12755
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12755
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 103
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188487.5-188487.39"
- cell $meminit $meminit$\memory$libresoc.v:188487$12756
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12756
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 104
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188488.5-188488.39"
- cell $meminit $meminit$\memory$libresoc.v:188488$12757
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12757
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 105
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188489.5-188489.39"
- cell $meminit $meminit$\memory$libresoc.v:188489$12758
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12758
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 106
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188490.5-188490.39"
- cell $meminit $meminit$\memory$libresoc.v:188490$12759
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12759
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 107
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188491.5-188491.39"
- cell $meminit $meminit$\memory$libresoc.v:188491$12760
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12760
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 108
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188492.5-188492.39"
- cell $meminit $meminit$\memory$libresoc.v:188492$12761
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12761
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 109
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188493.5-188493.39"
- cell $meminit $meminit$\memory$libresoc.v:188493$12762
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12762
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 110
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188494.5-188494.39"
- cell $meminit $meminit$\memory$libresoc.v:188494$12763
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12763
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 111
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188495.5-188495.39"
- cell $meminit $meminit$\memory$libresoc.v:188495$12764
- parameter \ABITS 32
- parameter \MEMID "\\memory"
- parameter \PRIORITY 12764
- parameter \WIDTH 64
- parameter \WORDS 1
- connect \ADDR 112
- connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- attribute \src "libresoc.v:188502.26-188502.32"
- cell $memrd $memrd$\memory$libresoc.v:188502$12646
- parameter \ABITS 7
+ attribute \src "libresoc.v:188398.26-188398.32"
+ cell $memrd $memrd$\memory$libresoc.v:188398$12542
+ parameter \ABITS 4
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\memory"
parameter \WIDTH 64
connect \ADDR \_0_
connect \CLK 1'x
- connect \DATA $memrd$\memory$libresoc.v:188502$12646_DATA
+ connect \DATA $memrd$\memory$libresoc.v:188398$12542_DATA
connect \EN 1'x
end
attribute \src "libresoc.v:0.0-0.0"
- process $proc$libresoc.v:0$12767
+ process $proc$libresoc.v:0$12559
sync always
sync init
end
attribute \src "libresoc.v:188349.7-188349.20"
- process $proc$libresoc.v:188349$12765
+ process $proc$libresoc.v:188349$12557
assign { } { }
assign $0\initial[0:0] 1'0
sync always
sync init
end
attribute \src "libresoc.v:188365.7-188365.23"
- process $proc$libresoc.v:188365$12766
+ process $proc$libresoc.v:188365$12558
assign { } { }
assign $1\ren_delay[0:0] 1'0
sync always
sync init
update \ren_delay $1\ren_delay[0:0]
end
- attribute \src "libresoc.v:188498.3-188501.6"
- process $proc$libresoc.v:188498$12639
+ attribute \src "libresoc.v:188394.3-188397.6"
+ process $proc$libresoc.v:188394$12535
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\_0_[6:0] \memory_r_addr
- assign $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640 $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643
- assign $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644
- assign $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645
- attribute \src "libresoc.v:188500.5-188500.61"
+ assign $0\_0_[3:0] \memory_r_addr
+ assign $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536 $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539
+ assign $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540
+ assign $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541
+ attribute \src "libresoc.v:188396.5-188396.61"
switch \memory_w_en
- attribute \src "libresoc.v:188500.9-188500.20"
+ attribute \src "libresoc.v:188396.9-188396.20"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 \memory_w_addr
- assign $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 \memory_w_data
- assign $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 64'1111111111111111111111111111111111111111111111111111111111111111
+ assign $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 \memory_w_addr
+ assign $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 \memory_w_data
+ assign $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 64'1111111111111111111111111111111111111111111111111111111111111111
case
- assign $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 7'xxxxxxx
- assign $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
- assign $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 4'xxxx
+ assign $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ assign $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync posedge \coresync_clk
- update \_0_ $0\_0_[6:0]
- update $memwr$\memory$libresoc.v:188500$12638_ADDR $0$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12640
- update $memwr$\memory$libresoc.v:188500$12638_DATA $0$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12641
- update $memwr$\memory$libresoc.v:188500$12638_EN $0$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12642
- attribute \src "libresoc.v:188500.22-188500.60"
- memwr \memory $1$memwr$\memory$libresoc.v:188500$12638_ADDR[6:0]$12643 $1$memwr$\memory$libresoc.v:188500$12638_DATA[63:0]$12644 $1$memwr$\memory$libresoc.v:188500$12638_EN[63:0]$12645 0'
+ update \_0_ $0\_0_[3:0]
+ update $memwr$\memory$libresoc.v:188396$12534_ADDR $0$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12536
+ update $memwr$\memory$libresoc.v:188396$12534_DATA $0$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12537
+ update $memwr$\memory$libresoc.v:188396$12534_EN $0$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12538
+ attribute \src "libresoc.v:188396.22-188396.60"
+ memwr \memory $1$memwr$\memory$libresoc.v:188396$12534_ADDR[3:0]$12539 $1$memwr$\memory$libresoc.v:188396$12534_DATA[63:0]$12540 $1$memwr$\memory$libresoc.v:188396$12534_EN[63:0]$12541 0'
end
- attribute \src "libresoc.v:188503.3-188504.35"
- process $proc$libresoc.v:188503$12647
+ attribute \src "libresoc.v:188399.3-188400.35"
+ process $proc$libresoc.v:188399$12543
assign { } { }
assign $0\ren_delay[0:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[0:0]
end
- attribute \src "libresoc.v:188505.3-188513.6"
- process $proc$libresoc.v:188505$12648
+ attribute \src "libresoc.v:188401.3-188409.6"
+ process $proc$libresoc.v:188401$12544
assign { } { }
assign { } { }
- assign $0\ren_delay$next[0:0]$12649 $1\ren_delay$next[0:0]$12650
- attribute \src "libresoc.v:188506.5-188506.29"
+ assign $0\ren_delay$next[0:0]$12545 $1\ren_delay$next[0:0]$12546
+ attribute \src "libresoc.v:188402.5-188402.29"
switch \initial
- attribute \src "libresoc.v:188506.9-188506.17"
+ attribute \src "libresoc.v:188402.9-188402.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[0:0]$12650 1'0
+ assign $1\ren_delay$next[0:0]$12546 1'0
case
- assign $1\ren_delay$next[0:0]$12650 \spr1__ren
+ assign $1\ren_delay$next[0:0]$12546 \spr1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[0:0]$12649
+ update \ren_delay$next $0\ren_delay$next[0:0]$12545
end
- attribute \src "libresoc.v:188514.3-188523.6"
- process $proc$libresoc.v:188514$12651
+ attribute \src "libresoc.v:188410.3-188419.6"
+ process $proc$libresoc.v:188410$12547
assign { } { }
assign { } { }
assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0]
- attribute \src "libresoc.v:188515.5-188515.29"
+ attribute \src "libresoc.v:188411.5-188411.29"
switch \initial
- attribute \src "libresoc.v:188515.9-188515.17"
+ attribute \src "libresoc.v:188411.9-188411.17"
case 1'1
case
end
sync always
update \spr1__data_o $0\spr1__data_o[63:0]
end
- connect \memory_r_data $memrd$\memory$libresoc.v:188502$12646_DATA
+ connect \memory_r_data $memrd$\memory$libresoc.v:188398$12542_DATA
connect \memory_w_data \spr1__data_i
connect \memory_w_en \spr1__wen
connect \memory_w_addr \spr1__addr$1
connect \memory_r_addr \spr1__addr
end
-attribute \src "libresoc.v:188532.1-189785.10"
+attribute \src "libresoc.v:188428.1-189681.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0"
attribute \generator "nMigen"
module \spr0
- attribute \src "libresoc.v:189282.3-189283.25"
+ attribute \src "libresoc.v:189178.3-189179.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:189280.3-189281.40"
+ attribute \src "libresoc.v:189176.3-189177.40"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:189676.3-189684.6"
- wire $0\alu_l_r_alu$next[0:0]$12981
- attribute \src "libresoc.v:189210.3-189211.39"
+ attribute \src "libresoc.v:189572.3-189580.6"
+ wire $0\alu_l_r_alu$next[0:0]$12773
+ attribute \src "libresoc.v:189106.3-189107.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903
- attribute \src "libresoc.v:189252.3-189253.65"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695
+ attribute \src "libresoc.v:189148.3-189149.65"
wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12904
- attribute \src "libresoc.v:189254.3-189255.59"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12696
+ attribute \src "libresoc.v:189150.3-189151.59"
wire width 32 $0\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12905
- attribute \src "libresoc.v:189250.3-189251.69"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12697
+ attribute \src "libresoc.v:189146.3-189147.69"
wire width 7 $0\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906
- attribute \src "libresoc.v:189256.3-189257.67"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698
+ attribute \src "libresoc.v:189152.3-189153.67"
wire $0\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:189667.3-189675.6"
- wire $0\alui_l_r_alui$next[0:0]$12978
- attribute \src "libresoc.v:189212.3-189213.43"
+ attribute \src "libresoc.v:189563.3-189571.6"
+ wire $0\alui_l_r_alui$next[0:0]$12770
+ attribute \src "libresoc.v:189108.3-189109.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:189475.3-189496.6"
- wire width 64 $0\data_r0__o$next[63:0]$12912
- attribute \src "libresoc.v:189246.3-189247.37"
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire width 64 $0\data_r0__o$next[63:0]$12704
+ attribute \src "libresoc.v:189142.3-189143.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:189475.3-189496.6"
- wire $0\data_r0__o_ok$next[0:0]$12913
- attribute \src "libresoc.v:189248.3-189249.43"
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire $0\data_r0__o_ok$next[0:0]$12705
+ attribute \src "libresoc.v:189144.3-189145.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:189497.3-189518.6"
- wire width 64 $0\data_r1__spr1$next[63:0]$12920
- attribute \src "libresoc.v:189242.3-189243.43"
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire width 64 $0\data_r1__spr1$next[63:0]$12712
+ attribute \src "libresoc.v:189138.3-189139.43"
wire width 64 $0\data_r1__spr1[63:0]
- attribute \src "libresoc.v:189497.3-189518.6"
- wire $0\data_r1__spr1_ok$next[0:0]$12921
- attribute \src "libresoc.v:189244.3-189245.49"
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire $0\data_r1__spr1_ok$next[0:0]$12713
+ attribute \src "libresoc.v:189140.3-189141.49"
wire $0\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:189519.3-189540.6"
- wire width 64 $0\data_r2__fast1$next[63:0]$12928
- attribute \src "libresoc.v:189238.3-189239.45"
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire width 64 $0\data_r2__fast1$next[63:0]$12720
+ attribute \src "libresoc.v:189134.3-189135.45"
wire width 64 $0\data_r2__fast1[63:0]
- attribute \src "libresoc.v:189519.3-189540.6"
- wire $0\data_r2__fast1_ok$next[0:0]$12929
- attribute \src "libresoc.v:189240.3-189241.51"
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire $0\data_r2__fast1_ok$next[0:0]$12721
+ attribute \src "libresoc.v:189136.3-189137.51"
wire $0\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $0\data_r3__xer_so$next[0:0]$12936
- attribute \src "libresoc.v:189234.3-189235.47"
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $0\data_r3__xer_so$next[0:0]$12728
+ attribute \src "libresoc.v:189130.3-189131.47"
wire $0\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $0\data_r3__xer_so_ok$next[0:0]$12937
- attribute \src "libresoc.v:189236.3-189237.53"
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $0\data_r3__xer_so_ok$next[0:0]$12729
+ attribute \src "libresoc.v:189132.3-189133.53"
wire $0\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:189563.3-189584.6"
- wire width 2 $0\data_r4__xer_ov$next[1:0]$12944
- attribute \src "libresoc.v:189230.3-189231.47"
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire width 2 $0\data_r4__xer_ov$next[1:0]$12736
+ attribute \src "libresoc.v:189126.3-189127.47"
wire width 2 $0\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:189563.3-189584.6"
- wire $0\data_r4__xer_ov_ok$next[0:0]$12945
- attribute \src "libresoc.v:189232.3-189233.53"
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire $0\data_r4__xer_ov_ok$next[0:0]$12737
+ attribute \src "libresoc.v:189128.3-189129.53"
wire $0\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:189585.3-189606.6"
- wire width 2 $0\data_r5__xer_ca$next[1:0]$12952
- attribute \src "libresoc.v:189226.3-189227.47"
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire width 2 $0\data_r5__xer_ca$next[1:0]$12744
+ attribute \src "libresoc.v:189122.3-189123.47"
wire width 2 $0\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:189585.3-189606.6"
- wire $0\data_r5__xer_ca_ok$next[0:0]$12953
- attribute \src "libresoc.v:189228.3-189229.53"
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire $0\data_r5__xer_ca_ok$next[0:0]$12745
+ attribute \src "libresoc.v:189124.3-189125.53"
wire $0\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:189685.3-189694.6"
+ attribute \src "libresoc.v:189581.3-189590.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:189695.3-189704.6"
+ attribute \src "libresoc.v:189591.3-189600.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:189705.3-189714.6"
+ attribute \src "libresoc.v:189601.3-189610.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:189715.3-189724.6"
+ attribute \src "libresoc.v:189611.3-189620.6"
wire $0\dest4_o[0:0]
- attribute \src "libresoc.v:189725.3-189734.6"
+ attribute \src "libresoc.v:189621.3-189630.6"
wire width 2 $0\dest5_o[1:0]
- attribute \src "libresoc.v:189735.3-189744.6"
+ attribute \src "libresoc.v:189631.3-189640.6"
wire width 2 $0\dest6_o[1:0]
- attribute \src "libresoc.v:188533.7-188533.20"
+ attribute \src "libresoc.v:188429.7-188429.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:189417.3-189425.6"
- wire $0\opc_l_r_opc$next[0:0]$12888
- attribute \src "libresoc.v:189266.3-189267.39"
+ attribute \src "libresoc.v:189313.3-189321.6"
+ wire $0\opc_l_r_opc$next[0:0]$12680
+ attribute \src "libresoc.v:189162.3-189163.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:189408.3-189416.6"
- wire $0\opc_l_s_opc$next[0:0]$12885
- attribute \src "libresoc.v:189268.3-189269.39"
+ attribute \src "libresoc.v:189304.3-189312.6"
+ wire $0\opc_l_s_opc$next[0:0]$12677
+ attribute \src "libresoc.v:189164.3-189165.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:189745.3-189753.6"
- wire width 6 $0\prev_wr_go$next[5:0]$12990
- attribute \src "libresoc.v:189278.3-189279.37"
+ attribute \src "libresoc.v:189641.3-189649.6"
+ wire width 6 $0\prev_wr_go$next[5:0]$12782
+ attribute \src "libresoc.v:189174.3-189175.37"
wire width 6 $0\prev_wr_go[5:0]
- attribute \src "libresoc.v:189362.3-189371.6"
+ attribute \src "libresoc.v:189258.3-189267.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:189453.3-189461.6"
- wire width 6 $0\req_l_r_req$next[5:0]$12900
- attribute \src "libresoc.v:189258.3-189259.39"
+ attribute \src "libresoc.v:189349.3-189357.6"
+ wire width 6 $0\req_l_r_req$next[5:0]$12692
+ attribute \src "libresoc.v:189154.3-189155.39"
wire width 6 $0\req_l_r_req[5:0]
- attribute \src "libresoc.v:189444.3-189452.6"
- wire width 6 $0\req_l_s_req$next[5:0]$12897
- attribute \src "libresoc.v:189260.3-189261.39"
+ attribute \src "libresoc.v:189340.3-189348.6"
+ wire width 6 $0\req_l_s_req$next[5:0]$12689
+ attribute \src "libresoc.v:189156.3-189157.39"
wire width 6 $0\req_l_s_req[5:0]
- attribute \src "libresoc.v:189381.3-189389.6"
- wire $0\rok_l_r_rdok$next[0:0]$12876
- attribute \src "libresoc.v:189274.3-189275.41"
+ attribute \src "libresoc.v:189277.3-189285.6"
+ wire $0\rok_l_r_rdok$next[0:0]$12668
+ attribute \src "libresoc.v:189170.3-189171.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:189372.3-189380.6"
- wire $0\rok_l_s_rdok$next[0:0]$12873
- attribute \src "libresoc.v:189276.3-189277.41"
+ attribute \src "libresoc.v:189268.3-189276.6"
+ wire $0\rok_l_s_rdok$next[0:0]$12665
+ attribute \src "libresoc.v:189172.3-189173.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:189399.3-189407.6"
- wire $0\rst_l_r_rst$next[0:0]$12882
- attribute \src "libresoc.v:189270.3-189271.39"
+ attribute \src "libresoc.v:189295.3-189303.6"
+ wire $0\rst_l_r_rst$next[0:0]$12674
+ attribute \src "libresoc.v:189166.3-189167.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:189390.3-189398.6"
- wire $0\rst_l_s_rst$next[0:0]$12879
- attribute \src "libresoc.v:189272.3-189273.39"
+ attribute \src "libresoc.v:189286.3-189294.6"
+ wire $0\rst_l_s_rst$next[0:0]$12671
+ attribute \src "libresoc.v:189168.3-189169.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:189435.3-189443.6"
- wire width 6 $0\src_l_r_src$next[5:0]$12894
- attribute \src "libresoc.v:189262.3-189263.39"
+ attribute \src "libresoc.v:189331.3-189339.6"
+ wire width 6 $0\src_l_r_src$next[5:0]$12686
+ attribute \src "libresoc.v:189158.3-189159.39"
wire width 6 $0\src_l_r_src[5:0]
- attribute \src "libresoc.v:189426.3-189434.6"
- wire width 6 $0\src_l_s_src$next[5:0]$12891
- attribute \src "libresoc.v:189264.3-189265.39"
+ attribute \src "libresoc.v:189322.3-189330.6"
+ wire width 6 $0\src_l_s_src$next[5:0]$12683
+ attribute \src "libresoc.v:189160.3-189161.39"
wire width 6 $0\src_l_s_src[5:0]
- attribute \src "libresoc.v:189607.3-189616.6"
- wire width 64 $0\src_r0$next[63:0]$12960
- attribute \src "libresoc.v:189224.3-189225.29"
+ attribute \src "libresoc.v:189503.3-189512.6"
+ wire width 64 $0\src_r0$next[63:0]$12752
+ attribute \src "libresoc.v:189120.3-189121.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:189617.3-189626.6"
- wire width 64 $0\src_r1$next[63:0]$12963
- attribute \src "libresoc.v:189222.3-189223.29"
+ attribute \src "libresoc.v:189513.3-189522.6"
+ wire width 64 $0\src_r1$next[63:0]$12755
+ attribute \src "libresoc.v:189118.3-189119.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:189627.3-189636.6"
- wire width 64 $0\src_r2$next[63:0]$12966
- attribute \src "libresoc.v:189220.3-189221.29"
+ attribute \src "libresoc.v:189523.3-189532.6"
+ wire width 64 $0\src_r2$next[63:0]$12758
+ attribute \src "libresoc.v:189116.3-189117.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:189637.3-189646.6"
- wire $0\src_r3$next[0:0]$12969
- attribute \src "libresoc.v:189218.3-189219.29"
+ attribute \src "libresoc.v:189533.3-189542.6"
+ wire $0\src_r3$next[0:0]$12761
+ attribute \src "libresoc.v:189114.3-189115.29"
wire $0\src_r3[0:0]
- attribute \src "libresoc.v:189647.3-189656.6"
- wire width 2 $0\src_r4$next[1:0]$12972
- attribute \src "libresoc.v:189216.3-189217.29"
+ attribute \src "libresoc.v:189543.3-189552.6"
+ wire width 2 $0\src_r4$next[1:0]$12764
+ attribute \src "libresoc.v:189112.3-189113.29"
wire width 2 $0\src_r4[1:0]
- attribute \src "libresoc.v:189657.3-189666.6"
- wire width 2 $0\src_r5$next[1:0]$12975
- attribute \src "libresoc.v:189214.3-189215.29"
+ attribute \src "libresoc.v:189553.3-189562.6"
+ wire width 2 $0\src_r5$next[1:0]$12767
+ attribute \src "libresoc.v:189110.3-189111.29"
wire width 2 $0\src_r5[1:0]
- attribute \src "libresoc.v:188669.7-188669.24"
+ attribute \src "libresoc.v:188565.7-188565.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:188679.7-188679.26"
+ attribute \src "libresoc.v:188575.7-188575.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:189676.3-189684.6"
- wire $1\alu_l_r_alu$next[0:0]$12982
- attribute \src "libresoc.v:188687.7-188687.25"
+ attribute \src "libresoc.v:189572.3-189580.6"
+ wire $1\alu_l_r_alu$next[0:0]$12774
+ attribute \src "libresoc.v:188583.7-188583.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907
- attribute \src "libresoc.v:188732.14-188732.49"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699
+ attribute \src "libresoc.v:188628.14-188628.49"
wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12908
- attribute \src "libresoc.v:188736.14-188736.43"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12700
+ attribute \src "libresoc.v:188632.14-188632.43"
wire width 32 $1\alu_spr0_spr_op__insn[31:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909
- attribute \src "libresoc.v:188815.13-188815.47"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701
+ attribute \src "libresoc.v:188711.13-188711.47"
wire width 7 $1\alu_spr0_spr_op__insn_type[6:0]
- attribute \src "libresoc.v:189462.3-189474.6"
- wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910
- attribute \src "libresoc.v:188819.7-188819.39"
+ attribute \src "libresoc.v:189358.3-189370.6"
+ wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702
+ attribute \src "libresoc.v:188715.7-188715.39"
wire $1\alu_spr0_spr_op__is_32bit[0:0]
- attribute \src "libresoc.v:189667.3-189675.6"
- wire $1\alui_l_r_alui$next[0:0]$12979
- attribute \src "libresoc.v:188837.7-188837.27"
+ attribute \src "libresoc.v:189563.3-189571.6"
+ wire $1\alui_l_r_alui$next[0:0]$12771
+ attribute \src "libresoc.v:188733.7-188733.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:189475.3-189496.6"
- wire width 64 $1\data_r0__o$next[63:0]$12914
- attribute \src "libresoc.v:188869.14-188869.47"
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire width 64 $1\data_r0__o$next[63:0]$12706
+ attribute \src "libresoc.v:188765.14-188765.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:189475.3-189496.6"
- wire $1\data_r0__o_ok$next[0:0]$12915
- attribute \src "libresoc.v:188873.7-188873.27"
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire $1\data_r0__o_ok$next[0:0]$12707
+ attribute \src "libresoc.v:188769.7-188769.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:189497.3-189518.6"
- wire width 64 $1\data_r1__spr1$next[63:0]$12922
- attribute \src "libresoc.v:188877.14-188877.50"
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire width 64 $1\data_r1__spr1$next[63:0]$12714
+ attribute \src "libresoc.v:188773.14-188773.50"
wire width 64 $1\data_r1__spr1[63:0]
- attribute \src "libresoc.v:189497.3-189518.6"
- wire $1\data_r1__spr1_ok$next[0:0]$12923
- attribute \src "libresoc.v:188881.7-188881.30"
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire $1\data_r1__spr1_ok$next[0:0]$12715
+ attribute \src "libresoc.v:188777.7-188777.30"
wire $1\data_r1__spr1_ok[0:0]
- attribute \src "libresoc.v:189519.3-189540.6"
- wire width 64 $1\data_r2__fast1$next[63:0]$12930
- attribute \src "libresoc.v:188885.14-188885.51"
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire width 64 $1\data_r2__fast1$next[63:0]$12722
+ attribute \src "libresoc.v:188781.14-188781.51"
wire width 64 $1\data_r2__fast1[63:0]
- attribute \src "libresoc.v:189519.3-189540.6"
- wire $1\data_r2__fast1_ok$next[0:0]$12931
- attribute \src "libresoc.v:188889.7-188889.31"
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire $1\data_r2__fast1_ok$next[0:0]$12723
+ attribute \src "libresoc.v:188785.7-188785.31"
wire $1\data_r2__fast1_ok[0:0]
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $1\data_r3__xer_so$next[0:0]$12938
- attribute \src "libresoc.v:188893.7-188893.29"
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $1\data_r3__xer_so$next[0:0]$12730
+ attribute \src "libresoc.v:188789.7-188789.29"
wire $1\data_r3__xer_so[0:0]
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $1\data_r3__xer_so_ok$next[0:0]$12939
- attribute \src "libresoc.v:188897.7-188897.32"
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $1\data_r3__xer_so_ok$next[0:0]$12731
+ attribute \src "libresoc.v:188793.7-188793.32"
wire $1\data_r3__xer_so_ok[0:0]
- attribute \src "libresoc.v:189563.3-189584.6"
- wire width 2 $1\data_r4__xer_ov$next[1:0]$12946
- attribute \src "libresoc.v:188901.13-188901.35"
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire width 2 $1\data_r4__xer_ov$next[1:0]$12738
+ attribute \src "libresoc.v:188797.13-188797.35"
wire width 2 $1\data_r4__xer_ov[1:0]
- attribute \src "libresoc.v:189563.3-189584.6"
- wire $1\data_r4__xer_ov_ok$next[0:0]$12947
- attribute \src "libresoc.v:188905.7-188905.32"
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire $1\data_r4__xer_ov_ok$next[0:0]$12739
+ attribute \src "libresoc.v:188801.7-188801.32"
wire $1\data_r4__xer_ov_ok[0:0]
- attribute \src "libresoc.v:189585.3-189606.6"
- wire width 2 $1\data_r5__xer_ca$next[1:0]$12954
- attribute \src "libresoc.v:188909.13-188909.35"
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire width 2 $1\data_r5__xer_ca$next[1:0]$12746
+ attribute \src "libresoc.v:188805.13-188805.35"
wire width 2 $1\data_r5__xer_ca[1:0]
- attribute \src "libresoc.v:189585.3-189606.6"
- wire $1\data_r5__xer_ca_ok$next[0:0]$12955
- attribute \src "libresoc.v:188913.7-188913.32"
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire $1\data_r5__xer_ca_ok$next[0:0]$12747
+ attribute \src "libresoc.v:188809.7-188809.32"
wire $1\data_r5__xer_ca_ok[0:0]
- attribute \src "libresoc.v:189685.3-189694.6"
+ attribute \src "libresoc.v:189581.3-189590.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:189695.3-189704.6"
+ attribute \src "libresoc.v:189591.3-189600.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:189705.3-189714.6"
+ attribute \src "libresoc.v:189601.3-189610.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:189715.3-189724.6"
+ attribute \src "libresoc.v:189611.3-189620.6"
wire $1\dest4_o[0:0]
- attribute \src "libresoc.v:189725.3-189734.6"
+ attribute \src "libresoc.v:189621.3-189630.6"
wire width 2 $1\dest5_o[1:0]
- attribute \src "libresoc.v:189735.3-189744.6"
+ attribute \src "libresoc.v:189631.3-189640.6"
wire width 2 $1\dest6_o[1:0]
- attribute \src "libresoc.v:189417.3-189425.6"
- wire $1\opc_l_r_opc$next[0:0]$12889
- attribute \src "libresoc.v:188941.7-188941.25"
+ attribute \src "libresoc.v:189313.3-189321.6"
+ wire $1\opc_l_r_opc$next[0:0]$12681
+ attribute \src "libresoc.v:188837.7-188837.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:189408.3-189416.6"
- wire $1\opc_l_s_opc$next[0:0]$12886
- attribute \src "libresoc.v:188945.7-188945.25"
+ attribute \src "libresoc.v:189304.3-189312.6"
+ wire $1\opc_l_s_opc$next[0:0]$12678
+ attribute \src "libresoc.v:188841.7-188841.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:189745.3-189753.6"
- wire width 6 $1\prev_wr_go$next[5:0]$12991
- attribute \src "libresoc.v:189047.13-189047.31"
+ attribute \src "libresoc.v:189641.3-189649.6"
+ wire width 6 $1\prev_wr_go$next[5:0]$12783
+ attribute \src "libresoc.v:188943.13-188943.31"
wire width 6 $1\prev_wr_go[5:0]
- attribute \src "libresoc.v:189362.3-189371.6"
+ attribute \src "libresoc.v:189258.3-189267.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:189453.3-189461.6"
- wire width 6 $1\req_l_r_req$next[5:0]$12901
- attribute \src "libresoc.v:189055.13-189055.32"
+ attribute \src "libresoc.v:189349.3-189357.6"
+ wire width 6 $1\req_l_r_req$next[5:0]$12693
+ attribute \src "libresoc.v:188951.13-188951.32"
wire width 6 $1\req_l_r_req[5:0]
- attribute \src "libresoc.v:189444.3-189452.6"
- wire width 6 $1\req_l_s_req$next[5:0]$12898
- attribute \src "libresoc.v:189059.13-189059.32"
+ attribute \src "libresoc.v:189340.3-189348.6"
+ wire width 6 $1\req_l_s_req$next[5:0]$12690
+ attribute \src "libresoc.v:188955.13-188955.32"
wire width 6 $1\req_l_s_req[5:0]
- attribute \src "libresoc.v:189381.3-189389.6"
- wire $1\rok_l_r_rdok$next[0:0]$12877
- attribute \src "libresoc.v:189071.7-189071.26"
+ attribute \src "libresoc.v:189277.3-189285.6"
+ wire $1\rok_l_r_rdok$next[0:0]$12669
+ attribute \src "libresoc.v:188967.7-188967.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:189372.3-189380.6"
- wire $1\rok_l_s_rdok$next[0:0]$12874
- attribute \src "libresoc.v:189075.7-189075.26"
+ attribute \src "libresoc.v:189268.3-189276.6"
+ wire $1\rok_l_s_rdok$next[0:0]$12666
+ attribute \src "libresoc.v:188971.7-188971.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:189399.3-189407.6"
- wire $1\rst_l_r_rst$next[0:0]$12883
- attribute \src "libresoc.v:189079.7-189079.25"
+ attribute \src "libresoc.v:189295.3-189303.6"
+ wire $1\rst_l_r_rst$next[0:0]$12675
+ attribute \src "libresoc.v:188975.7-188975.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:189390.3-189398.6"
- wire $1\rst_l_s_rst$next[0:0]$12880
- attribute \src "libresoc.v:189083.7-189083.25"
+ attribute \src "libresoc.v:189286.3-189294.6"
+ wire $1\rst_l_s_rst$next[0:0]$12672
+ attribute \src "libresoc.v:188979.7-188979.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:189435.3-189443.6"
- wire width 6 $1\src_l_r_src$next[5:0]$12895
- attribute \src "libresoc.v:189105.13-189105.32"
+ attribute \src "libresoc.v:189331.3-189339.6"
+ wire width 6 $1\src_l_r_src$next[5:0]$12687
+ attribute \src "libresoc.v:189001.13-189001.32"
wire width 6 $1\src_l_r_src[5:0]
- attribute \src "libresoc.v:189426.3-189434.6"
- wire width 6 $1\src_l_s_src$next[5:0]$12892
- attribute \src "libresoc.v:189109.13-189109.32"
+ attribute \src "libresoc.v:189322.3-189330.6"
+ wire width 6 $1\src_l_s_src$next[5:0]$12684
+ attribute \src "libresoc.v:189005.13-189005.32"
wire width 6 $1\src_l_s_src[5:0]
- attribute \src "libresoc.v:189607.3-189616.6"
- wire width 64 $1\src_r0$next[63:0]$12961
- attribute \src "libresoc.v:189113.14-189113.43"
+ attribute \src "libresoc.v:189503.3-189512.6"
+ wire width 64 $1\src_r0$next[63:0]$12753
+ attribute \src "libresoc.v:189009.14-189009.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:189617.3-189626.6"
- wire width 64 $1\src_r1$next[63:0]$12964
- attribute \src "libresoc.v:189117.14-189117.43"
+ attribute \src "libresoc.v:189513.3-189522.6"
+ wire width 64 $1\src_r1$next[63:0]$12756
+ attribute \src "libresoc.v:189013.14-189013.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:189627.3-189636.6"
- wire width 64 $1\src_r2$next[63:0]$12967
- attribute \src "libresoc.v:189121.14-189121.43"
+ attribute \src "libresoc.v:189523.3-189532.6"
+ wire width 64 $1\src_r2$next[63:0]$12759
+ attribute \src "libresoc.v:189017.14-189017.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:189637.3-189646.6"
- wire $1\src_r3$next[0:0]$12970
- attribute \src "libresoc.v:189125.7-189125.20"
+ attribute \src "libresoc.v:189533.3-189542.6"
+ wire $1\src_r3$next[0:0]$12762
+ attribute \src "libresoc.v:189021.7-189021.20"
wire $1\src_r3[0:0]
- attribute \src "libresoc.v:189647.3-189656.6"
- wire width 2 $1\src_r4$next[1:0]$12973
- attribute \src "libresoc.v:189129.13-189129.26"
+ attribute \src "libresoc.v:189543.3-189552.6"
+ wire width 2 $1\src_r4$next[1:0]$12765
+ attribute \src "libresoc.v:189025.13-189025.26"
wire width 2 $1\src_r4[1:0]
- attribute \src "libresoc.v:189657.3-189666.6"
- wire width 2 $1\src_r5$next[1:0]$12976
- attribute \src "libresoc.v:189133.13-189133.26"
+ attribute \src "libresoc.v:189553.3-189562.6"
+ wire width 2 $1\src_r5$next[1:0]$12768
+ attribute \src "libresoc.v:189029.13-189029.26"
wire width 2 $1\src_r5[1:0]
- attribute \src "libresoc.v:189475.3-189496.6"
- wire width 64 $2\data_r0__o$next[63:0]$12916
- attribute \src "libresoc.v:189475.3-189496.6"
- wire $2\data_r0__o_ok$next[0:0]$12917
- attribute \src "libresoc.v:189497.3-189518.6"
- wire width 64 $2\data_r1__spr1$next[63:0]$12924
- attribute \src "libresoc.v:189497.3-189518.6"
- wire $2\data_r1__spr1_ok$next[0:0]$12925
- attribute \src "libresoc.v:189519.3-189540.6"
- wire width 64 $2\data_r2__fast1$next[63:0]$12932
- attribute \src "libresoc.v:189519.3-189540.6"
- wire $2\data_r2__fast1_ok$next[0:0]$12933
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $2\data_r3__xer_so$next[0:0]$12940
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $2\data_r3__xer_so_ok$next[0:0]$12941
- attribute \src "libresoc.v:189563.3-189584.6"
- wire width 2 $2\data_r4__xer_ov$next[1:0]$12948
- attribute \src "libresoc.v:189563.3-189584.6"
- wire $2\data_r4__xer_ov_ok$next[0:0]$12949
- attribute \src "libresoc.v:189585.3-189606.6"
- wire width 2 $2\data_r5__xer_ca$next[1:0]$12956
- attribute \src "libresoc.v:189585.3-189606.6"
- wire $2\data_r5__xer_ca_ok$next[0:0]$12957
- attribute \src "libresoc.v:189475.3-189496.6"
- wire $3\data_r0__o_ok$next[0:0]$12918
- attribute \src "libresoc.v:189497.3-189518.6"
- wire $3\data_r1__spr1_ok$next[0:0]$12926
- attribute \src "libresoc.v:189519.3-189540.6"
- wire $3\data_r2__fast1_ok$next[0:0]$12934
- attribute \src "libresoc.v:189541.3-189562.6"
- wire $3\data_r3__xer_so_ok$next[0:0]$12942
- attribute \src "libresoc.v:189563.3-189584.6"
- wire $3\data_r4__xer_ov_ok$next[0:0]$12950
- attribute \src "libresoc.v:189585.3-189606.6"
- wire $3\data_r5__xer_ca_ok$next[0:0]$12958
- attribute \src "libresoc.v:189145.19-189145.133"
- wire $and$libresoc.v:189145$12769_Y
- attribute \src "libresoc.v:189146.19-189146.183"
- wire width 6 $and$libresoc.v:189146$12770_Y
- attribute \src "libresoc.v:189147.19-189147.115"
- wire width 6 $and$libresoc.v:189147$12771_Y
- attribute \src "libresoc.v:189149.19-189149.115"
- wire width 6 $and$libresoc.v:189149$12773_Y
- attribute \src "libresoc.v:189150.19-189150.125"
- wire $and$libresoc.v:189150$12774_Y
- attribute \src "libresoc.v:189151.19-189151.125"
- wire $and$libresoc.v:189151$12775_Y
- attribute \src "libresoc.v:189152.19-189152.125"
- wire $and$libresoc.v:189152$12776_Y
- attribute \src "libresoc.v:189153.19-189153.125"
- wire $and$libresoc.v:189153$12777_Y
- attribute \src "libresoc.v:189154.19-189154.125"
- wire $and$libresoc.v:189154$12778_Y
- attribute \src "libresoc.v:189156.19-189156.125"
- wire $and$libresoc.v:189156$12780_Y
- attribute \src "libresoc.v:189157.19-189157.165"
- wire width 6 $and$libresoc.v:189157$12781_Y
- attribute \src "libresoc.v:189158.19-189158.121"
- wire width 6 $and$libresoc.v:189158$12782_Y
- attribute \src "libresoc.v:189159.19-189159.127"
- wire $and$libresoc.v:189159$12783_Y
- attribute \src "libresoc.v:189160.19-189160.127"
- wire $and$libresoc.v:189160$12784_Y
- attribute \src "libresoc.v:189162.19-189162.127"
- wire $and$libresoc.v:189162$12786_Y
- attribute \src "libresoc.v:189163.19-189163.127"
- wire $and$libresoc.v:189163$12787_Y
- attribute \src "libresoc.v:189164.19-189164.127"
- wire $and$libresoc.v:189164$12788_Y
- attribute \src "libresoc.v:189165.19-189165.127"
- wire $and$libresoc.v:189165$12789_Y
- attribute \src "libresoc.v:189166.18-189166.110"
- wire $and$libresoc.v:189166$12790_Y
- attribute \src "libresoc.v:189168.18-189168.98"
- wire $and$libresoc.v:189168$12792_Y
- attribute \src "libresoc.v:189170.18-189170.100"
- wire $and$libresoc.v:189170$12794_Y
- attribute \src "libresoc.v:189171.18-189171.182"
- wire width 6 $and$libresoc.v:189171$12795_Y
- attribute \src "libresoc.v:189173.18-189173.119"
- wire width 6 $and$libresoc.v:189173$12797_Y
- attribute \src "libresoc.v:189176.18-189176.116"
- wire $and$libresoc.v:189176$12800_Y
- attribute \src "libresoc.v:189181.18-189181.113"
- wire $and$libresoc.v:189181$12805_Y
- attribute \src "libresoc.v:189182.18-189182.125"
- wire width 6 $and$libresoc.v:189182$12806_Y
- attribute \src "libresoc.v:189184.18-189184.112"
- wire $and$libresoc.v:189184$12808_Y
- attribute \src "libresoc.v:189186.18-189186.126"
- wire $and$libresoc.v:189186$12810_Y
- attribute \src "libresoc.v:189187.18-189187.126"
- wire $and$libresoc.v:189187$12811_Y
- attribute \src "libresoc.v:189188.18-189188.117"
- wire $and$libresoc.v:189188$12812_Y
- attribute \src "libresoc.v:189193.18-189193.130"
- wire $and$libresoc.v:189193$12817_Y
- attribute \src "libresoc.v:189194.17-189194.123"
- wire $and$libresoc.v:189194$12818_Y
- attribute \src "libresoc.v:189195.18-189195.124"
- wire width 6 $and$libresoc.v:189195$12819_Y
- attribute \src "libresoc.v:189197.18-189197.116"
- wire $and$libresoc.v:189197$12821_Y
- attribute \src "libresoc.v:189198.18-189198.119"
- wire $and$libresoc.v:189198$12822_Y
- attribute \src "libresoc.v:189199.18-189199.120"
- wire $and$libresoc.v:189199$12823_Y
- attribute \src "libresoc.v:189200.18-189200.121"
- wire $and$libresoc.v:189200$12824_Y
- attribute \src "libresoc.v:189201.18-189201.121"
- wire $and$libresoc.v:189201$12825_Y
- attribute \src "libresoc.v:189202.18-189202.121"
- wire $and$libresoc.v:189202$12826_Y
- attribute \src "libresoc.v:189209.18-189209.134"
- wire $and$libresoc.v:189209$12833_Y
- attribute \src "libresoc.v:189183.18-189183.113"
- wire $eq$libresoc.v:189183$12807_Y
- attribute \src "libresoc.v:189185.18-189185.119"
- wire $eq$libresoc.v:189185$12809_Y
- attribute \src "libresoc.v:189144.17-189144.113"
- wire width 6 $not$libresoc.v:189144$12768_Y
- attribute \src "libresoc.v:189148.19-189148.115"
- wire width 6 $not$libresoc.v:189148$12772_Y
- attribute \src "libresoc.v:189167.18-189167.97"
- wire $not$libresoc.v:189167$12791_Y
- attribute \src "libresoc.v:189169.18-189169.99"
- wire $not$libresoc.v:189169$12793_Y
- attribute \src "libresoc.v:189172.18-189172.113"
- wire width 6 $not$libresoc.v:189172$12796_Y
- attribute \src "libresoc.v:189175.18-189175.106"
- wire $not$libresoc.v:189175$12799_Y
- attribute \src "libresoc.v:189180.18-189180.120"
- wire $not$libresoc.v:189180$12804_Y
- attribute \src "libresoc.v:189155.18-189155.118"
- wire width 6 $or$libresoc.v:189155$12779_Y
- attribute \src "libresoc.v:189179.18-189179.112"
- wire $or$libresoc.v:189179$12803_Y
- attribute \src "libresoc.v:189189.18-189189.122"
- wire $or$libresoc.v:189189$12813_Y
- attribute \src "libresoc.v:189190.18-189190.124"
- wire $or$libresoc.v:189190$12814_Y
- attribute \src "libresoc.v:189191.18-189191.194"
- wire width 6 $or$libresoc.v:189191$12815_Y
- attribute \src "libresoc.v:189192.18-189192.194"
- wire width 6 $or$libresoc.v:189192$12816_Y
- attribute \src "libresoc.v:189196.18-189196.120"
- wire width 6 $or$libresoc.v:189196$12820_Y
- attribute \src "libresoc.v:189161.17-189161.105"
- wire $reduce_and$libresoc.v:189161$12785_Y
- attribute \src "libresoc.v:189174.18-189174.106"
- wire $reduce_or$libresoc.v:189174$12798_Y
- attribute \src "libresoc.v:189177.18-189177.113"
- wire $reduce_or$libresoc.v:189177$12801_Y
- attribute \src "libresoc.v:189178.18-189178.112"
- wire $reduce_or$libresoc.v:189178$12802_Y
- attribute \src "libresoc.v:189203.18-189203.118"
- wire width 64 $ternary$libresoc.v:189203$12827_Y
- attribute \src "libresoc.v:189204.18-189204.118"
- wire width 64 $ternary$libresoc.v:189204$12828_Y
- attribute \src "libresoc.v:189205.18-189205.118"
- wire width 64 $ternary$libresoc.v:189205$12829_Y
- attribute \src "libresoc.v:189206.18-189206.118"
- wire $ternary$libresoc.v:189206$12830_Y
- attribute \src "libresoc.v:189207.18-189207.118"
- wire width 2 $ternary$libresoc.v:189207$12831_Y
- attribute \src "libresoc.v:189208.18-189208.118"
- wire width 2 $ternary$libresoc.v:189208$12832_Y
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire width 64 $2\data_r0__o$next[63:0]$12708
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire $2\data_r0__o_ok$next[0:0]$12709
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire width 64 $2\data_r1__spr1$next[63:0]$12716
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire $2\data_r1__spr1_ok$next[0:0]$12717
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire width 64 $2\data_r2__fast1$next[63:0]$12724
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire $2\data_r2__fast1_ok$next[0:0]$12725
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $2\data_r3__xer_so$next[0:0]$12732
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $2\data_r3__xer_so_ok$next[0:0]$12733
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire width 2 $2\data_r4__xer_ov$next[1:0]$12740
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire $2\data_r4__xer_ov_ok$next[0:0]$12741
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire width 2 $2\data_r5__xer_ca$next[1:0]$12748
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire $2\data_r5__xer_ca_ok$next[0:0]$12749
+ attribute \src "libresoc.v:189371.3-189392.6"
+ wire $3\data_r0__o_ok$next[0:0]$12710
+ attribute \src "libresoc.v:189393.3-189414.6"
+ wire $3\data_r1__spr1_ok$next[0:0]$12718
+ attribute \src "libresoc.v:189415.3-189436.6"
+ wire $3\data_r2__fast1_ok$next[0:0]$12726
+ attribute \src "libresoc.v:189437.3-189458.6"
+ wire $3\data_r3__xer_so_ok$next[0:0]$12734
+ attribute \src "libresoc.v:189459.3-189480.6"
+ wire $3\data_r4__xer_ov_ok$next[0:0]$12742
+ attribute \src "libresoc.v:189481.3-189502.6"
+ wire $3\data_r5__xer_ca_ok$next[0:0]$12750
+ attribute \src "libresoc.v:189041.19-189041.133"
+ wire $and$libresoc.v:189041$12561_Y
+ attribute \src "libresoc.v:189042.19-189042.183"
+ wire width 6 $and$libresoc.v:189042$12562_Y
+ attribute \src "libresoc.v:189043.19-189043.115"
+ wire width 6 $and$libresoc.v:189043$12563_Y
+ attribute \src "libresoc.v:189045.19-189045.115"
+ wire width 6 $and$libresoc.v:189045$12565_Y
+ attribute \src "libresoc.v:189046.19-189046.125"
+ wire $and$libresoc.v:189046$12566_Y
+ attribute \src "libresoc.v:189047.19-189047.125"
+ wire $and$libresoc.v:189047$12567_Y
+ attribute \src "libresoc.v:189048.19-189048.125"
+ wire $and$libresoc.v:189048$12568_Y
+ attribute \src "libresoc.v:189049.19-189049.125"
+ wire $and$libresoc.v:189049$12569_Y
+ attribute \src "libresoc.v:189050.19-189050.125"
+ wire $and$libresoc.v:189050$12570_Y
+ attribute \src "libresoc.v:189052.19-189052.125"
+ wire $and$libresoc.v:189052$12572_Y
+ attribute \src "libresoc.v:189053.19-189053.165"
+ wire width 6 $and$libresoc.v:189053$12573_Y
+ attribute \src "libresoc.v:189054.19-189054.121"
+ wire width 6 $and$libresoc.v:189054$12574_Y
+ attribute \src "libresoc.v:189055.19-189055.127"
+ wire $and$libresoc.v:189055$12575_Y
+ attribute \src "libresoc.v:189056.19-189056.127"
+ wire $and$libresoc.v:189056$12576_Y
+ attribute \src "libresoc.v:189058.19-189058.127"
+ wire $and$libresoc.v:189058$12578_Y
+ attribute \src "libresoc.v:189059.19-189059.127"
+ wire $and$libresoc.v:189059$12579_Y
+ attribute \src "libresoc.v:189060.19-189060.127"
+ wire $and$libresoc.v:189060$12580_Y
+ attribute \src "libresoc.v:189061.19-189061.127"
+ wire $and$libresoc.v:189061$12581_Y
+ attribute \src "libresoc.v:189062.18-189062.110"
+ wire $and$libresoc.v:189062$12582_Y
+ attribute \src "libresoc.v:189064.18-189064.98"
+ wire $and$libresoc.v:189064$12584_Y
+ attribute \src "libresoc.v:189066.18-189066.100"
+ wire $and$libresoc.v:189066$12586_Y
+ attribute \src "libresoc.v:189067.18-189067.182"
+ wire width 6 $and$libresoc.v:189067$12587_Y
+ attribute \src "libresoc.v:189069.18-189069.119"
+ wire width 6 $and$libresoc.v:189069$12589_Y
+ attribute \src "libresoc.v:189072.18-189072.116"
+ wire $and$libresoc.v:189072$12592_Y
+ attribute \src "libresoc.v:189077.18-189077.113"
+ wire $and$libresoc.v:189077$12597_Y
+ attribute \src "libresoc.v:189078.18-189078.125"
+ wire width 6 $and$libresoc.v:189078$12598_Y
+ attribute \src "libresoc.v:189080.18-189080.112"
+ wire $and$libresoc.v:189080$12600_Y
+ attribute \src "libresoc.v:189082.18-189082.126"
+ wire $and$libresoc.v:189082$12602_Y
+ attribute \src "libresoc.v:189083.18-189083.126"
+ wire $and$libresoc.v:189083$12603_Y
+ attribute \src "libresoc.v:189084.18-189084.117"
+ wire $and$libresoc.v:189084$12604_Y
+ attribute \src "libresoc.v:189089.18-189089.130"
+ wire $and$libresoc.v:189089$12609_Y
+ attribute \src "libresoc.v:189090.17-189090.123"
+ wire $and$libresoc.v:189090$12610_Y
+ attribute \src "libresoc.v:189091.18-189091.124"
+ wire width 6 $and$libresoc.v:189091$12611_Y
+ attribute \src "libresoc.v:189093.18-189093.116"
+ wire $and$libresoc.v:189093$12613_Y
+ attribute \src "libresoc.v:189094.18-189094.119"
+ wire $and$libresoc.v:189094$12614_Y
+ attribute \src "libresoc.v:189095.18-189095.120"
+ wire $and$libresoc.v:189095$12615_Y
+ attribute \src "libresoc.v:189096.18-189096.121"
+ wire $and$libresoc.v:189096$12616_Y
+ attribute \src "libresoc.v:189097.18-189097.121"
+ wire $and$libresoc.v:189097$12617_Y
+ attribute \src "libresoc.v:189098.18-189098.121"
+ wire $and$libresoc.v:189098$12618_Y
+ attribute \src "libresoc.v:189105.18-189105.134"
+ wire $and$libresoc.v:189105$12625_Y
+ attribute \src "libresoc.v:189079.18-189079.113"
+ wire $eq$libresoc.v:189079$12599_Y
+ attribute \src "libresoc.v:189081.18-189081.119"
+ wire $eq$libresoc.v:189081$12601_Y
+ attribute \src "libresoc.v:189040.17-189040.113"
+ wire width 6 $not$libresoc.v:189040$12560_Y
+ attribute \src "libresoc.v:189044.19-189044.115"
+ wire width 6 $not$libresoc.v:189044$12564_Y
+ attribute \src "libresoc.v:189063.18-189063.97"
+ wire $not$libresoc.v:189063$12583_Y
+ attribute \src "libresoc.v:189065.18-189065.99"
+ wire $not$libresoc.v:189065$12585_Y
+ attribute \src "libresoc.v:189068.18-189068.113"
+ wire width 6 $not$libresoc.v:189068$12588_Y
+ attribute \src "libresoc.v:189071.18-189071.106"
+ wire $not$libresoc.v:189071$12591_Y
+ attribute \src "libresoc.v:189076.18-189076.120"
+ wire $not$libresoc.v:189076$12596_Y
+ attribute \src "libresoc.v:189051.18-189051.118"
+ wire width 6 $or$libresoc.v:189051$12571_Y
+ attribute \src "libresoc.v:189075.18-189075.112"
+ wire $or$libresoc.v:189075$12595_Y
+ attribute \src "libresoc.v:189085.18-189085.122"
+ wire $or$libresoc.v:189085$12605_Y
+ attribute \src "libresoc.v:189086.18-189086.124"
+ wire $or$libresoc.v:189086$12606_Y
+ attribute \src "libresoc.v:189087.18-189087.194"
+ wire width 6 $or$libresoc.v:189087$12607_Y
+ attribute \src "libresoc.v:189088.18-189088.194"
+ wire width 6 $or$libresoc.v:189088$12608_Y
+ attribute \src "libresoc.v:189092.18-189092.120"
+ wire width 6 $or$libresoc.v:189092$12612_Y
+ attribute \src "libresoc.v:189057.17-189057.105"
+ wire $reduce_and$libresoc.v:189057$12577_Y
+ attribute \src "libresoc.v:189070.18-189070.106"
+ wire $reduce_or$libresoc.v:189070$12590_Y
+ attribute \src "libresoc.v:189073.18-189073.113"
+ wire $reduce_or$libresoc.v:189073$12593_Y
+ attribute \src "libresoc.v:189074.18-189074.112"
+ wire $reduce_or$libresoc.v:189074$12594_Y
+ attribute \src "libresoc.v:189099.18-189099.118"
+ wire width 64 $ternary$libresoc.v:189099$12619_Y
+ attribute \src "libresoc.v:189100.18-189100.118"
+ wire width 64 $ternary$libresoc.v:189100$12620_Y
+ attribute \src "libresoc.v:189101.18-189101.118"
+ wire width 64 $ternary$libresoc.v:189101$12621_Y
+ attribute \src "libresoc.v:189102.18-189102.118"
+ wire $ternary$libresoc.v:189102$12622_Y
+ attribute \src "libresoc.v:189103.18-189103.118"
+ wire width 2 $ternary$libresoc.v:189103$12623_Y
+ attribute \src "libresoc.v:189104.18-189104.118"
+ wire width 2 $ternary$libresoc.v:189104$12624_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
wire \$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
wire \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 6 \alu_pulsem
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_spr0_fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_spr0_fast1$2
wire \alu_spr0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_spr0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_spr0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_spr0_p_ready_o
wire \alu_spr0_p_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_spr0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_spr0_spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_spr0_spr1$1
wire \alu_spr0_spr_op__is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
wire \alu_spr0_spr_op__is_32bit$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_spr0_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \alu_spr0_xer_ca$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 \alu_spr0_xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 \alu_spr0_xer_ov$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \alu_spr0_xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire \alu_spr0_xer_so$3
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 31 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 7 \cu_busy_o
wire width 2 output 24 \dest5_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 2 output 22 \dest6_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \fast1_ok
- attribute \src "libresoc.v:188533.7-188533.15"
+ attribute \src "libresoc.v:188429.7-188429.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 17 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
wire \rst_l_s_rst$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire \rst_r
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 29 \spr1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72"
wire width 64 input 11 \src1_i
wire width 2 \src_r5$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 21 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:189145$12769
+ cell $and $and$libresoc.v:189041$12561
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:189145$12769_Y
+ connect \Y $and$libresoc.v:189041$12561_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:189146$12770
+ cell $and $and$libresoc.v:189042$12562
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:189146$12770_Y
+ connect \Y $and$libresoc.v:189042$12562_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:189147$12771
+ cell $and $and$libresoc.v:189043$12563
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$102
connect \B 6'111111
- connect \Y $and$libresoc.v:189147$12771_Y
+ connect \Y $and$libresoc.v:189043$12563_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:189149$12773
+ cell $and $and$libresoc.v:189045$12565
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$104
connect \B \$106
- connect \Y $and$libresoc.v:189149$12773_Y
+ connect \Y $and$libresoc.v:189045$12565_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189150$12774
+ cell $and $and$libresoc.v:189046$12566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189150$12774_Y
+ connect \Y $and$libresoc.v:189046$12566_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189151$12775
+ cell $and $and$libresoc.v:189047$12567
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189151$12775_Y
+ connect \Y $and$libresoc.v:189047$12567_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189152$12776
+ cell $and $and$libresoc.v:189048$12568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189152$12776_Y
+ connect \Y $and$libresoc.v:189048$12568_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189153$12777
+ cell $and $and$libresoc.v:189049$12569
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189153$12777_Y
+ connect \Y $and$libresoc.v:189049$12569_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189154$12778
+ cell $and $and$libresoc.v:189050$12570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189154$12778_Y
+ connect \Y $and$libresoc.v:189050$12570_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:189156$12780
+ cell $and $and$libresoc.v:189052$12572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:189156$12780_Y
+ connect \Y $and$libresoc.v:189052$12572_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:189157$12781
+ cell $and $and$libresoc.v:189053$12573
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B { \$110 \$112 \$114 \$116 \$118 \$120 }
- connect \Y $and$libresoc.v:189157$12781_Y
+ connect \Y $and$libresoc.v:189053$12573_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:189158$12782
+ cell $and $and$libresoc.v:189054$12574
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$122
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:189158$12782_Y
+ connect \Y $and$libresoc.v:189054$12574_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189159$12783
+ cell $and $and$libresoc.v:189055$12575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189159$12783_Y
+ connect \Y $and$libresoc.v:189055$12575_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189160$12784
+ cell $and $and$libresoc.v:189056$12576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189160$12784_Y
+ connect \Y $and$libresoc.v:189056$12576_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189162$12786
+ cell $and $and$libresoc.v:189058$12578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189162$12786_Y
+ connect \Y $and$libresoc.v:189058$12578_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189163$12787
+ cell $and $and$libresoc.v:189059$12579
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189163$12787_Y
+ connect \Y $and$libresoc.v:189059$12579_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189164$12788
+ cell $and $and$libresoc.v:189060$12580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189164$12788_Y
+ connect \Y $and$libresoc.v:189060$12580_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:189165$12789
+ cell $and $and$libresoc.v:189061$12581
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [5]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189165$12789_Y
+ connect \Y $and$libresoc.v:189061$12581_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:189166$12790
+ cell $and $and$libresoc.v:189062$12582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$6
connect \B \$8
- connect \Y $and$libresoc.v:189166$12790_Y
+ connect \Y $and$libresoc.v:189062$12582_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:189168$12792
+ cell $and $and$libresoc.v:189064$12584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$16
- connect \Y $and$libresoc.v:189168$12792_Y
+ connect \Y $and$libresoc.v:189064$12584_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:189170$12794
+ cell $and $and$libresoc.v:189066$12586
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$20
- connect \Y $and$libresoc.v:189170$12794_Y
+ connect \Y $and$libresoc.v:189066$12586_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:189171$12795
+ cell $and $and$libresoc.v:189067$12587
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:189171$12795_Y
+ connect \Y $and$libresoc.v:189067$12587_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:189173$12797
+ cell $and $and$libresoc.v:189069$12589
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__rel_o
connect \B \$28
- connect \Y $and$libresoc.v:189173$12797_Y
+ connect \Y $and$libresoc.v:189069$12589_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:189176$12800
+ cell $and $and$libresoc.v:189072$12592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$26
- connect \Y $and$libresoc.v:189176$12800_Y
+ connect \Y $and$libresoc.v:189072$12592_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:189181$12805
+ cell $and $and$libresoc.v:189077$12597
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$42
- connect \Y $and$libresoc.v:189181$12805_Y
+ connect \Y $and$libresoc.v:189077$12597_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:189182$12806
+ cell $and $and$libresoc.v:189078$12598
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:189182$12806_Y
+ connect \Y $and$libresoc.v:189078$12598_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:189184$12808
+ cell $and $and$libresoc.v:189080$12600
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$48
- connect \Y $and$libresoc.v:189184$12808_Y
+ connect \Y $and$libresoc.v:189080$12600_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:189186$12810
+ cell $and $and$libresoc.v:189082$12602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$52
connect \B \alu_spr0_n_ready_i
- connect \Y $and$libresoc.v:189186$12810_Y
+ connect \Y $and$libresoc.v:189082$12602_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:189187$12811
+ cell $and $and$libresoc.v:189083$12603
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$54
connect \B \alu_spr0_n_valid_o
- connect \Y $and$libresoc.v:189187$12811_Y
+ connect \Y $and$libresoc.v:189083$12603_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:189188$12812
+ cell $and $and$libresoc.v:189084$12604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$56
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189188$12812_Y
+ connect \Y $and$libresoc.v:189084$12604_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:189193$12817
+ cell $and $and$libresoc.v:189089$12609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189193$12817_Y
+ connect \Y $and$libresoc.v:189089$12609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:189194$12818
+ cell $and $and$libresoc.v:189090$12610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:189194$12818_Y
+ connect \Y $and$libresoc.v:189090$12610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:189195$12819
+ cell $and $and$libresoc.v:189091$12611
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:189195$12819_Y
+ connect \Y $and$libresoc.v:189091$12611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189197$12821
+ cell $and $and$libresoc.v:189093$12613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189197$12821_Y
+ connect \Y $and$libresoc.v:189093$12613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189198$12822
+ cell $and $and$libresoc.v:189094$12614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189198$12822_Y
+ connect \Y $and$libresoc.v:189094$12614_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189199$12823
+ cell $and $and$libresoc.v:189095$12615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189199$12823_Y
+ connect \Y $and$libresoc.v:189095$12615_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189200$12824
+ cell $and $and$libresoc.v:189096$12616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_so_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189200$12824_Y
+ connect \Y $and$libresoc.v:189096$12616_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189201$12825
+ cell $and $and$libresoc.v:189097$12617
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ov_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189201$12825_Y
+ connect \Y $and$libresoc.v:189097$12617_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:189202$12826
+ cell $and $and$libresoc.v:189098$12618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xer_ca_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:189202$12826_Y
+ connect \Y $and$libresoc.v:189098$12618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:189209$12833
+ cell $and $and$libresoc.v:189105$12625
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:189209$12833_Y
+ connect \Y $and$libresoc.v:189105$12625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:189183$12807
+ cell $eq $eq$libresoc.v:189079$12599
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$46
connect \B 1'0
- connect \Y $eq$libresoc.v:189183$12807_Y
+ connect \Y $eq$libresoc.v:189079$12599_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:189185$12809
+ cell $eq $eq$libresoc.v:189081$12601
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:189185$12809_Y
+ connect \Y $eq$libresoc.v:189081$12601_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:189144$12768
+ cell $not $not$libresoc.v:189040$12560
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:189144$12768_Y
+ connect \Y $not$libresoc.v:189040$12560_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:189148$12772
+ cell $not $not$libresoc.v:189044$12564
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:189148$12772_Y
+ connect \Y $not$libresoc.v:189044$12564_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:189167$12791
+ cell $not $not$libresoc.v:189063$12583
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:189167$12791_Y
+ connect \Y $not$libresoc.v:189063$12583_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:189169$12793
+ cell $not $not$libresoc.v:189065$12585
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:189169$12793_Y
+ connect \Y $not$libresoc.v:189065$12585_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:189172$12796
+ cell $not $not$libresoc.v:189068$12588
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:189172$12796_Y
+ connect \Y $not$libresoc.v:189068$12588_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:189175$12799
+ cell $not $not$libresoc.v:189071$12591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $not$libresoc.v:189175$12799_Y
+ connect \Y $not$libresoc.v:189071$12591_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:189180$12804
+ cell $not $not$libresoc.v:189076$12596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_ready_i
- connect \Y $not$libresoc.v:189180$12804_Y
+ connect \Y $not$libresoc.v:189076$12596_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:189155$12779
+ cell $or $or$libresoc.v:189051$12571
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:189155$12779_Y
+ connect \Y $or$libresoc.v:189051$12571_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:189179$12803
+ cell $or $or$libresoc.v:189075$12595
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$36
connect \B \$38
- connect \Y $or$libresoc.v:189179$12803_Y
+ connect \Y $or$libresoc.v:189075$12595_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:189189$12813
+ cell $or $or$libresoc.v:189085$12605
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:189189$12813_Y
+ connect \Y $or$libresoc.v:189085$12605_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:189190$12814
+ cell $or $or$libresoc.v:189086$12606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:189190$12814_Y
+ connect \Y $or$libresoc.v:189086$12606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:189191$12815
+ cell $or $or$libresoc.v:189087$12607
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:189191$12815_Y
+ connect \Y $or$libresoc.v:189087$12607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:189192$12816
+ cell $or $or$libresoc.v:189088$12608
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:189192$12816_Y
+ connect \Y $or$libresoc.v:189088$12608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:189196$12820
+ cell $or $or$libresoc.v:189092$12612
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:189196$12820_Y
+ connect \Y $or$libresoc.v:189092$12612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:189161$12785
+ cell $reduce_and $reduce_and$libresoc.v:189057$12577
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$11
- connect \Y $reduce_and$libresoc.v:189161$12785_Y
+ connect \Y $reduce_and$libresoc.v:189057$12577_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:189174$12798
+ cell $reduce_or $reduce_or$libresoc.v:189070$12590
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \$30
- connect \Y $reduce_or$libresoc.v:189174$12798_Y
+ connect \Y $reduce_or$libresoc.v:189070$12590_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:189177$12801
+ cell $reduce_or $reduce_or$libresoc.v:189073$12593
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:189177$12801_Y
+ connect \Y $reduce_or$libresoc.v:189073$12593_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:189178$12802
+ cell $reduce_or $reduce_or$libresoc.v:189074$12594
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:189178$12802_Y
+ connect \Y $reduce_or$libresoc.v:189074$12594_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189203$12827
+ cell $mux $ternary$libresoc.v:189099$12619
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:189203$12827_Y
+ connect \Y $ternary$libresoc.v:189099$12619_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189204$12828
+ cell $mux $ternary$libresoc.v:189100$12620
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:189204$12828_Y
+ connect \Y $ternary$libresoc.v:189100$12620_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189205$12829
+ cell $mux $ternary$libresoc.v:189101$12621
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:189205$12829_Y
+ connect \Y $ternary$libresoc.v:189101$12621_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189206$12830
+ cell $mux $ternary$libresoc.v:189102$12622
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:189206$12830_Y
+ connect \Y $ternary$libresoc.v:189102$12622_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189207$12831
+ cell $mux $ternary$libresoc.v:189103$12623
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $ternary$libresoc.v:189207$12831_Y
+ connect \Y $ternary$libresoc.v:189103$12623_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:189208$12832
+ cell $mux $ternary$libresoc.v:189104$12624
parameter \WIDTH 2
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $ternary$libresoc.v:189208$12832_Y
+ connect \Y $ternary$libresoc.v:189104$12624_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189284.14-189290.4"
+ attribute \src "libresoc.v:189180.14-189186.4"
cell \alu_l$73 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189291.12-189320.4"
+ attribute \src "libresoc.v:189187.12-189216.4"
cell \alu_spr0 \alu_spr0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \xer_so_ok \xer_so_ok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189321.15-189327.4"
+ attribute \src "libresoc.v:189217.15-189223.4"
cell \alui_l$72 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189328.14-189334.4"
+ attribute \src "libresoc.v:189224.14-189230.4"
cell \opc_l$68 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189335.14-189341.4"
+ attribute \src "libresoc.v:189231.14-189237.4"
cell \req_l$69 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189342.14-189348.4"
+ attribute \src "libresoc.v:189238.14-189244.4"
cell \rok_l$71 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189349.14-189354.4"
+ attribute \src "libresoc.v:189245.14-189250.4"
cell \rst_l$70 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:189355.14-189361.4"
+ attribute \src "libresoc.v:189251.14-189257.4"
cell \src_l$67 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:188533.7-188533.20"
- process $proc$libresoc.v:188533$12992
+ attribute \src "libresoc.v:188429.7-188429.20"
+ process $proc$libresoc.v:188429$12784
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:188669.7-188669.24"
- process $proc$libresoc.v:188669$12993
+ attribute \src "libresoc.v:188565.7-188565.24"
+ process $proc$libresoc.v:188565$12785
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:188679.7-188679.26"
- process $proc$libresoc.v:188679$12994
+ attribute \src "libresoc.v:188575.7-188575.26"
+ process $proc$libresoc.v:188575$12786
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:188687.7-188687.25"
- process $proc$libresoc.v:188687$12995
+ attribute \src "libresoc.v:188583.7-188583.25"
+ process $proc$libresoc.v:188583$12787
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:188732.14-188732.49"
- process $proc$libresoc.v:188732$12996
+ attribute \src "libresoc.v:188628.14-188628.49"
+ process $proc$libresoc.v:188628$12788
assign { } { }
assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:188736.14-188736.43"
- process $proc$libresoc.v:188736$12997
+ attribute \src "libresoc.v:188632.14-188632.43"
+ process $proc$libresoc.v:188632$12789
assign { } { }
assign $1\alu_spr0_spr_op__insn[31:0] 0
sync always
sync init
update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:188815.13-188815.47"
- process $proc$libresoc.v:188815$12998
+ attribute \src "libresoc.v:188711.13-188711.47"
+ process $proc$libresoc.v:188711$12790
assign { } { }
assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:188819.7-188819.39"
- process $proc$libresoc.v:188819$12999
+ attribute \src "libresoc.v:188715.7-188715.39"
+ process $proc$libresoc.v:188715$12791
assign { } { }
assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:188837.7-188837.27"
- process $proc$libresoc.v:188837$13000
+ attribute \src "libresoc.v:188733.7-188733.27"
+ process $proc$libresoc.v:188733$12792
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:188869.14-188869.47"
- process $proc$libresoc.v:188869$13001
+ attribute \src "libresoc.v:188765.14-188765.47"
+ process $proc$libresoc.v:188765$12793
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:188873.7-188873.27"
- process $proc$libresoc.v:188873$13002
+ attribute \src "libresoc.v:188769.7-188769.27"
+ process $proc$libresoc.v:188769$12794
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:188877.14-188877.50"
- process $proc$libresoc.v:188877$13003
+ attribute \src "libresoc.v:188773.14-188773.50"
+ process $proc$libresoc.v:188773$12795
assign { } { }
assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__spr1 $1\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:188881.7-188881.30"
- process $proc$libresoc.v:188881$13004
+ attribute \src "libresoc.v:188777.7-188777.30"
+ process $proc$libresoc.v:188777$12796
assign { } { }
assign $1\data_r1__spr1_ok[0:0] 1'0
sync always
sync init
update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:188885.14-188885.51"
- process $proc$libresoc.v:188885$13005
+ attribute \src "libresoc.v:188781.14-188781.51"
+ process $proc$libresoc.v:188781$12797
assign { } { }
assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast1 $1\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:188889.7-188889.31"
- process $proc$libresoc.v:188889$13006
+ attribute \src "libresoc.v:188785.7-188785.31"
+ process $proc$libresoc.v:188785$12798
assign { } { }
assign $1\data_r2__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:188893.7-188893.29"
- process $proc$libresoc.v:188893$13007
+ attribute \src "libresoc.v:188789.7-188789.29"
+ process $proc$libresoc.v:188789$12799
assign { } { }
assign $1\data_r3__xer_so[0:0] 1'0
sync always
sync init
update \data_r3__xer_so $1\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:188897.7-188897.32"
- process $proc$libresoc.v:188897$13008
+ attribute \src "libresoc.v:188793.7-188793.32"
+ process $proc$libresoc.v:188793$12800
assign { } { }
assign $1\data_r3__xer_so_ok[0:0] 1'0
sync always
sync init
update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:188901.13-188901.35"
- process $proc$libresoc.v:188901$13009
+ attribute \src "libresoc.v:188797.13-188797.35"
+ process $proc$libresoc.v:188797$12801
assign { } { }
assign $1\data_r4__xer_ov[1:0] 2'00
sync always
sync init
update \data_r4__xer_ov $1\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:188905.7-188905.32"
- process $proc$libresoc.v:188905$13010
+ attribute \src "libresoc.v:188801.7-188801.32"
+ process $proc$libresoc.v:188801$12802
assign { } { }
assign $1\data_r4__xer_ov_ok[0:0] 1'0
sync always
sync init
update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:188909.13-188909.35"
- process $proc$libresoc.v:188909$13011
+ attribute \src "libresoc.v:188805.13-188805.35"
+ process $proc$libresoc.v:188805$12803
assign { } { }
assign $1\data_r5__xer_ca[1:0] 2'00
sync always
sync init
update \data_r5__xer_ca $1\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:188913.7-188913.32"
- process $proc$libresoc.v:188913$13012
+ attribute \src "libresoc.v:188809.7-188809.32"
+ process $proc$libresoc.v:188809$12804
assign { } { }
assign $1\data_r5__xer_ca_ok[0:0] 1'0
sync always
sync init
update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:188941.7-188941.25"
- process $proc$libresoc.v:188941$13013
+ attribute \src "libresoc.v:188837.7-188837.25"
+ process $proc$libresoc.v:188837$12805
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:188945.7-188945.25"
- process $proc$libresoc.v:188945$13014
+ attribute \src "libresoc.v:188841.7-188841.25"
+ process $proc$libresoc.v:188841$12806
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:189047.13-189047.31"
- process $proc$libresoc.v:189047$13015
+ attribute \src "libresoc.v:188943.13-188943.31"
+ process $proc$libresoc.v:188943$12807
assign { } { }
assign $1\prev_wr_go[5:0] 6'000000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:189055.13-189055.32"
- process $proc$libresoc.v:189055$13016
+ attribute \src "libresoc.v:188951.13-188951.32"
+ process $proc$libresoc.v:188951$12808
assign { } { }
assign $1\req_l_r_req[5:0] 6'111111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:189059.13-189059.32"
- process $proc$libresoc.v:189059$13017
+ attribute \src "libresoc.v:188955.13-188955.32"
+ process $proc$libresoc.v:188955$12809
assign { } { }
assign $1\req_l_s_req[5:0] 6'000000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:189071.7-189071.26"
- process $proc$libresoc.v:189071$13018
+ attribute \src "libresoc.v:188967.7-188967.26"
+ process $proc$libresoc.v:188967$12810
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:189075.7-189075.26"
- process $proc$libresoc.v:189075$13019
+ attribute \src "libresoc.v:188971.7-188971.26"
+ process $proc$libresoc.v:188971$12811
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:189079.7-189079.25"
- process $proc$libresoc.v:189079$13020
+ attribute \src "libresoc.v:188975.7-188975.25"
+ process $proc$libresoc.v:188975$12812
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:189083.7-189083.25"
- process $proc$libresoc.v:189083$13021
+ attribute \src "libresoc.v:188979.7-188979.25"
+ process $proc$libresoc.v:188979$12813
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:189105.13-189105.32"
- process $proc$libresoc.v:189105$13022
+ attribute \src "libresoc.v:189001.13-189001.32"
+ process $proc$libresoc.v:189001$12814
assign { } { }
assign $1\src_l_r_src[5:0] 6'111111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:189109.13-189109.32"
- process $proc$libresoc.v:189109$13023
+ attribute \src "libresoc.v:189005.13-189005.32"
+ process $proc$libresoc.v:189005$12815
assign { } { }
assign $1\src_l_s_src[5:0] 6'000000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:189113.14-189113.43"
- process $proc$libresoc.v:189113$13024
+ attribute \src "libresoc.v:189009.14-189009.43"
+ process $proc$libresoc.v:189009$12816
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:189117.14-189117.43"
- process $proc$libresoc.v:189117$13025
+ attribute \src "libresoc.v:189013.14-189013.43"
+ process $proc$libresoc.v:189013$12817
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:189121.14-189121.43"
- process $proc$libresoc.v:189121$13026
+ attribute \src "libresoc.v:189017.14-189017.43"
+ process $proc$libresoc.v:189017$12818
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:189125.7-189125.20"
- process $proc$libresoc.v:189125$13027
+ attribute \src "libresoc.v:189021.7-189021.20"
+ process $proc$libresoc.v:189021$12819
assign { } { }
assign $1\src_r3[0:0] 1'0
sync always
sync init
update \src_r3 $1\src_r3[0:0]
end
- attribute \src "libresoc.v:189129.13-189129.26"
- process $proc$libresoc.v:189129$13028
+ attribute \src "libresoc.v:189025.13-189025.26"
+ process $proc$libresoc.v:189025$12820
assign { } { }
assign $1\src_r4[1:0] 2'00
sync always
sync init
update \src_r4 $1\src_r4[1:0]
end
- attribute \src "libresoc.v:189133.13-189133.26"
- process $proc$libresoc.v:189133$13029
+ attribute \src "libresoc.v:189029.13-189029.26"
+ process $proc$libresoc.v:189029$12821
assign { } { }
assign $1\src_r5[1:0] 2'00
sync always
sync init
update \src_r5 $1\src_r5[1:0]
end
- attribute \src "libresoc.v:189210.3-189211.39"
- process $proc$libresoc.v:189210$12834
+ attribute \src "libresoc.v:189106.3-189107.39"
+ process $proc$libresoc.v:189106$12626
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:189212.3-189213.43"
- process $proc$libresoc.v:189212$12835
+ attribute \src "libresoc.v:189108.3-189109.43"
+ process $proc$libresoc.v:189108$12627
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:189214.3-189215.29"
- process $proc$libresoc.v:189214$12836
+ attribute \src "libresoc.v:189110.3-189111.29"
+ process $proc$libresoc.v:189110$12628
assign { } { }
assign $0\src_r5[1:0] \src_r5$next
sync posedge \coresync_clk
update \src_r5 $0\src_r5[1:0]
end
- attribute \src "libresoc.v:189216.3-189217.29"
- process $proc$libresoc.v:189216$12837
+ attribute \src "libresoc.v:189112.3-189113.29"
+ process $proc$libresoc.v:189112$12629
assign { } { }
assign $0\src_r4[1:0] \src_r4$next
sync posedge \coresync_clk
update \src_r4 $0\src_r4[1:0]
end
- attribute \src "libresoc.v:189218.3-189219.29"
- process $proc$libresoc.v:189218$12838
+ attribute \src "libresoc.v:189114.3-189115.29"
+ process $proc$libresoc.v:189114$12630
assign { } { }
assign $0\src_r3[0:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[0:0]
end
- attribute \src "libresoc.v:189220.3-189221.29"
- process $proc$libresoc.v:189220$12839
+ attribute \src "libresoc.v:189116.3-189117.29"
+ process $proc$libresoc.v:189116$12631
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:189222.3-189223.29"
- process $proc$libresoc.v:189222$12840
+ attribute \src "libresoc.v:189118.3-189119.29"
+ process $proc$libresoc.v:189118$12632
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:189224.3-189225.29"
- process $proc$libresoc.v:189224$12841
+ attribute \src "libresoc.v:189120.3-189121.29"
+ process $proc$libresoc.v:189120$12633
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:189226.3-189227.47"
- process $proc$libresoc.v:189226$12842
+ attribute \src "libresoc.v:189122.3-189123.47"
+ process $proc$libresoc.v:189122$12634
assign { } { }
assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next
sync posedge \coresync_clk
update \data_r5__xer_ca $0\data_r5__xer_ca[1:0]
end
- attribute \src "libresoc.v:189228.3-189229.53"
- process $proc$libresoc.v:189228$12843
+ attribute \src "libresoc.v:189124.3-189125.53"
+ process $proc$libresoc.v:189124$12635
assign { } { }
assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next
sync posedge \coresync_clk
update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:189230.3-189231.47"
- process $proc$libresoc.v:189230$12844
+ attribute \src "libresoc.v:189126.3-189127.47"
+ process $proc$libresoc.v:189126$12636
assign { } { }
assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next
sync posedge \coresync_clk
update \data_r4__xer_ov $0\data_r4__xer_ov[1:0]
end
- attribute \src "libresoc.v:189232.3-189233.53"
- process $proc$libresoc.v:189232$12845
+ attribute \src "libresoc.v:189128.3-189129.53"
+ process $proc$libresoc.v:189128$12637
assign { } { }
assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next
sync posedge \coresync_clk
update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:189234.3-189235.47"
- process $proc$libresoc.v:189234$12846
+ attribute \src "libresoc.v:189130.3-189131.47"
+ process $proc$libresoc.v:189130$12638
assign { } { }
assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next
sync posedge \coresync_clk
update \data_r3__xer_so $0\data_r3__xer_so[0:0]
end
- attribute \src "libresoc.v:189236.3-189237.53"
- process $proc$libresoc.v:189236$12847
+ attribute \src "libresoc.v:189132.3-189133.53"
+ process $proc$libresoc.v:189132$12639
assign { } { }
assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next
sync posedge \coresync_clk
update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0]
end
- attribute \src "libresoc.v:189238.3-189239.45"
- process $proc$libresoc.v:189238$12848
+ attribute \src "libresoc.v:189134.3-189135.45"
+ process $proc$libresoc.v:189134$12640
assign { } { }
assign $0\data_r2__fast1[63:0] \data_r2__fast1$next
sync posedge \coresync_clk
update \data_r2__fast1 $0\data_r2__fast1[63:0]
end
- attribute \src "libresoc.v:189240.3-189241.51"
- process $proc$libresoc.v:189240$12849
+ attribute \src "libresoc.v:189136.3-189137.51"
+ process $proc$libresoc.v:189136$12641
assign { } { }
assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next
sync posedge \coresync_clk
update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0]
end
- attribute \src "libresoc.v:189242.3-189243.43"
- process $proc$libresoc.v:189242$12850
+ attribute \src "libresoc.v:189138.3-189139.43"
+ process $proc$libresoc.v:189138$12642
assign { } { }
assign $0\data_r1__spr1[63:0] \data_r1__spr1$next
sync posedge \coresync_clk
update \data_r1__spr1 $0\data_r1__spr1[63:0]
end
- attribute \src "libresoc.v:189244.3-189245.49"
- process $proc$libresoc.v:189244$12851
+ attribute \src "libresoc.v:189140.3-189141.49"
+ process $proc$libresoc.v:189140$12643
assign { } { }
assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next
sync posedge \coresync_clk
update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0]
end
- attribute \src "libresoc.v:189246.3-189247.37"
- process $proc$libresoc.v:189246$12852
+ attribute \src "libresoc.v:189142.3-189143.37"
+ process $proc$libresoc.v:189142$12644
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:189248.3-189249.43"
- process $proc$libresoc.v:189248$12853
+ attribute \src "libresoc.v:189144.3-189145.43"
+ process $proc$libresoc.v:189144$12645
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:189250.3-189251.69"
- process $proc$libresoc.v:189250$12854
+ attribute \src "libresoc.v:189146.3-189147.69"
+ process $proc$libresoc.v:189146$12646
assign { } { }
assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0]
end
- attribute \src "libresoc.v:189252.3-189253.65"
- process $proc$libresoc.v:189252$12855
+ attribute \src "libresoc.v:189148.3-189149.65"
+ process $proc$libresoc.v:189148$12647
assign { } { }
assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:189254.3-189255.59"
- process $proc$libresoc.v:189254$12856
+ attribute \src "libresoc.v:189150.3-189151.59"
+ process $proc$libresoc.v:189150$12648
assign { } { }
assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0]
end
- attribute \src "libresoc.v:189256.3-189257.67"
- process $proc$libresoc.v:189256$12857
+ attribute \src "libresoc.v:189152.3-189153.67"
+ process $proc$libresoc.v:189152$12649
assign { } { }
assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next
sync posedge \coresync_clk
update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:189258.3-189259.39"
- process $proc$libresoc.v:189258$12858
+ attribute \src "libresoc.v:189154.3-189155.39"
+ process $proc$libresoc.v:189154$12650
assign { } { }
assign $0\req_l_r_req[5:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[5:0]
end
- attribute \src "libresoc.v:189260.3-189261.39"
- process $proc$libresoc.v:189260$12859
+ attribute \src "libresoc.v:189156.3-189157.39"
+ process $proc$libresoc.v:189156$12651
assign { } { }
assign $0\req_l_s_req[5:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[5:0]
end
- attribute \src "libresoc.v:189262.3-189263.39"
- process $proc$libresoc.v:189262$12860
+ attribute \src "libresoc.v:189158.3-189159.39"
+ process $proc$libresoc.v:189158$12652
assign { } { }
assign $0\src_l_r_src[5:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[5:0]
end
- attribute \src "libresoc.v:189264.3-189265.39"
- process $proc$libresoc.v:189264$12861
+ attribute \src "libresoc.v:189160.3-189161.39"
+ process $proc$libresoc.v:189160$12653
assign { } { }
assign $0\src_l_s_src[5:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[5:0]
end
- attribute \src "libresoc.v:189266.3-189267.39"
- process $proc$libresoc.v:189266$12862
+ attribute \src "libresoc.v:189162.3-189163.39"
+ process $proc$libresoc.v:189162$12654
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:189268.3-189269.39"
- process $proc$libresoc.v:189268$12863
+ attribute \src "libresoc.v:189164.3-189165.39"
+ process $proc$libresoc.v:189164$12655
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:189270.3-189271.39"
- process $proc$libresoc.v:189270$12864
+ attribute \src "libresoc.v:189166.3-189167.39"
+ process $proc$libresoc.v:189166$12656
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:189272.3-189273.39"
- process $proc$libresoc.v:189272$12865
+ attribute \src "libresoc.v:189168.3-189169.39"
+ process $proc$libresoc.v:189168$12657
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:189274.3-189275.41"
- process $proc$libresoc.v:189274$12866
+ attribute \src "libresoc.v:189170.3-189171.41"
+ process $proc$libresoc.v:189170$12658
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:189276.3-189277.41"
- process $proc$libresoc.v:189276$12867
+ attribute \src "libresoc.v:189172.3-189173.41"
+ process $proc$libresoc.v:189172$12659
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:189278.3-189279.37"
- process $proc$libresoc.v:189278$12868
+ attribute \src "libresoc.v:189174.3-189175.37"
+ process $proc$libresoc.v:189174$12660
assign { } { }
assign $0\prev_wr_go[5:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[5:0]
end
- attribute \src "libresoc.v:189280.3-189281.40"
- process $proc$libresoc.v:189280$12869
+ attribute \src "libresoc.v:189176.3-189177.40"
+ process $proc$libresoc.v:189176$12661
assign { } { }
assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:189282.3-189283.25"
- process $proc$libresoc.v:189282$12870
+ attribute \src "libresoc.v:189178.3-189179.25"
+ process $proc$libresoc.v:189178$12662
assign { } { }
assign $0\all_rd_dly[0:0] \$14
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:189362.3-189371.6"
- process $proc$libresoc.v:189362$12871
+ attribute \src "libresoc.v:189258.3-189267.6"
+ process $proc$libresoc.v:189258$12663
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:189363.5-189363.29"
+ attribute \src "libresoc.v:189259.5-189259.29"
switch \initial
- attribute \src "libresoc.v:189363.9-189363.17"
+ attribute \src "libresoc.v:189259.9-189259.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:189372.3-189380.6"
- process $proc$libresoc.v:189372$12872
+ attribute \src "libresoc.v:189268.3-189276.6"
+ process $proc$libresoc.v:189268$12664
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$12873 $1\rok_l_s_rdok$next[0:0]$12874
- attribute \src "libresoc.v:189373.5-189373.29"
+ assign $0\rok_l_s_rdok$next[0:0]$12665 $1\rok_l_s_rdok$next[0:0]$12666
+ attribute \src "libresoc.v:189269.5-189269.29"
switch \initial
- attribute \src "libresoc.v:189373.9-189373.17"
+ attribute \src "libresoc.v:189269.9-189269.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$12874 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$12666 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$12874 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$12666 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12873
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12665
end
- attribute \src "libresoc.v:189381.3-189389.6"
- process $proc$libresoc.v:189381$12875
+ attribute \src "libresoc.v:189277.3-189285.6"
+ process $proc$libresoc.v:189277$12667
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$12876 $1\rok_l_r_rdok$next[0:0]$12877
- attribute \src "libresoc.v:189382.5-189382.29"
+ assign $0\rok_l_r_rdok$next[0:0]$12668 $1\rok_l_r_rdok$next[0:0]$12669
+ attribute \src "libresoc.v:189278.5-189278.29"
switch \initial
- attribute \src "libresoc.v:189382.9-189382.17"
+ attribute \src "libresoc.v:189278.9-189278.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$12877 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$12669 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$12877 \$68
+ assign $1\rok_l_r_rdok$next[0:0]$12669 \$68
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12876
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12668
end
- attribute \src "libresoc.v:189390.3-189398.6"
- process $proc$libresoc.v:189390$12878
+ attribute \src "libresoc.v:189286.3-189294.6"
+ process $proc$libresoc.v:189286$12670
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$12879 $1\rst_l_s_rst$next[0:0]$12880
- attribute \src "libresoc.v:189391.5-189391.29"
+ assign $0\rst_l_s_rst$next[0:0]$12671 $1\rst_l_s_rst$next[0:0]$12672
+ attribute \src "libresoc.v:189287.5-189287.29"
switch \initial
- attribute \src "libresoc.v:189391.9-189391.17"
+ attribute \src "libresoc.v:189287.9-189287.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$12880 1'0
+ assign $1\rst_l_s_rst$next[0:0]$12672 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$12880 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$12672 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12879
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12671
end
- attribute \src "libresoc.v:189399.3-189407.6"
- process $proc$libresoc.v:189399$12881
+ attribute \src "libresoc.v:189295.3-189303.6"
+ process $proc$libresoc.v:189295$12673
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$12882 $1\rst_l_r_rst$next[0:0]$12883
- attribute \src "libresoc.v:189400.5-189400.29"
+ assign $0\rst_l_r_rst$next[0:0]$12674 $1\rst_l_r_rst$next[0:0]$12675
+ attribute \src "libresoc.v:189296.5-189296.29"
switch \initial
- attribute \src "libresoc.v:189400.9-189400.17"
+ attribute \src "libresoc.v:189296.9-189296.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$12883 1'1
+ assign $1\rst_l_r_rst$next[0:0]$12675 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$12883 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$12675 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12882
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12674
end
- attribute \src "libresoc.v:189408.3-189416.6"
- process $proc$libresoc.v:189408$12884
+ attribute \src "libresoc.v:189304.3-189312.6"
+ process $proc$libresoc.v:189304$12676
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$12885 $1\opc_l_s_opc$next[0:0]$12886
- attribute \src "libresoc.v:189409.5-189409.29"
+ assign $0\opc_l_s_opc$next[0:0]$12677 $1\opc_l_s_opc$next[0:0]$12678
+ attribute \src "libresoc.v:189305.5-189305.29"
switch \initial
- attribute \src "libresoc.v:189409.9-189409.17"
+ attribute \src "libresoc.v:189305.9-189305.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$12886 1'0
+ assign $1\opc_l_s_opc$next[0:0]$12678 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$12886 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$12678 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12885
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12677
end
- attribute \src "libresoc.v:189417.3-189425.6"
- process $proc$libresoc.v:189417$12887
+ attribute \src "libresoc.v:189313.3-189321.6"
+ process $proc$libresoc.v:189313$12679
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$12888 $1\opc_l_r_opc$next[0:0]$12889
- attribute \src "libresoc.v:189418.5-189418.29"
+ assign $0\opc_l_r_opc$next[0:0]$12680 $1\opc_l_r_opc$next[0:0]$12681
+ attribute \src "libresoc.v:189314.5-189314.29"
switch \initial
- attribute \src "libresoc.v:189418.9-189418.17"
+ attribute \src "libresoc.v:189314.9-189314.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$12889 1'1
+ assign $1\opc_l_r_opc$next[0:0]$12681 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$12889 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$12681 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12888
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12680
end
- attribute \src "libresoc.v:189426.3-189434.6"
- process $proc$libresoc.v:189426$12890
+ attribute \src "libresoc.v:189322.3-189330.6"
+ process $proc$libresoc.v:189322$12682
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[5:0]$12891 $1\src_l_s_src$next[5:0]$12892
- attribute \src "libresoc.v:189427.5-189427.29"
+ assign $0\src_l_s_src$next[5:0]$12683 $1\src_l_s_src$next[5:0]$12684
+ attribute \src "libresoc.v:189323.5-189323.29"
switch \initial
- attribute \src "libresoc.v:189427.9-189427.17"
+ attribute \src "libresoc.v:189323.9-189323.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[5:0]$12892 6'000000
+ assign $1\src_l_s_src$next[5:0]$12684 6'000000
case
- assign $1\src_l_s_src$next[5:0]$12892 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[5:0]$12684 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12891
+ update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12683
end
- attribute \src "libresoc.v:189435.3-189443.6"
- process $proc$libresoc.v:189435$12893
+ attribute \src "libresoc.v:189331.3-189339.6"
+ process $proc$libresoc.v:189331$12685
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[5:0]$12894 $1\src_l_r_src$next[5:0]$12895
- attribute \src "libresoc.v:189436.5-189436.29"
+ assign $0\src_l_r_src$next[5:0]$12686 $1\src_l_r_src$next[5:0]$12687
+ attribute \src "libresoc.v:189332.5-189332.29"
switch \initial
- attribute \src "libresoc.v:189436.9-189436.17"
+ attribute \src "libresoc.v:189332.9-189332.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[5:0]$12895 6'111111
+ assign $1\src_l_r_src$next[5:0]$12687 6'111111
case
- assign $1\src_l_r_src$next[5:0]$12895 \reset_r
+ assign $1\src_l_r_src$next[5:0]$12687 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12894
+ update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12686
end
- attribute \src "libresoc.v:189444.3-189452.6"
- process $proc$libresoc.v:189444$12896
+ attribute \src "libresoc.v:189340.3-189348.6"
+ process $proc$libresoc.v:189340$12688
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[5:0]$12897 $1\req_l_s_req$next[5:0]$12898
- attribute \src "libresoc.v:189445.5-189445.29"
+ assign $0\req_l_s_req$next[5:0]$12689 $1\req_l_s_req$next[5:0]$12690
+ attribute \src "libresoc.v:189341.5-189341.29"
switch \initial
- attribute \src "libresoc.v:189445.9-189445.17"
+ attribute \src "libresoc.v:189341.9-189341.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[5:0]$12898 6'000000
+ assign $1\req_l_s_req$next[5:0]$12690 6'000000
case
- assign $1\req_l_s_req$next[5:0]$12898 \$70
+ assign $1\req_l_s_req$next[5:0]$12690 \$70
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12897
+ update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12689
end
- attribute \src "libresoc.v:189453.3-189461.6"
- process $proc$libresoc.v:189453$12899
+ attribute \src "libresoc.v:189349.3-189357.6"
+ process $proc$libresoc.v:189349$12691
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[5:0]$12900 $1\req_l_r_req$next[5:0]$12901
- attribute \src "libresoc.v:189454.5-189454.29"
+ assign $0\req_l_r_req$next[5:0]$12692 $1\req_l_r_req$next[5:0]$12693
+ attribute \src "libresoc.v:189350.5-189350.29"
switch \initial
- attribute \src "libresoc.v:189454.9-189454.17"
+ attribute \src "libresoc.v:189350.9-189350.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[5:0]$12901 6'111111
+ assign $1\req_l_r_req$next[5:0]$12693 6'111111
case
- assign $1\req_l_r_req$next[5:0]$12901 \$72
+ assign $1\req_l_r_req$next[5:0]$12693 \$72
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12900
+ update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12692
end
- attribute \src "libresoc.v:189462.3-189474.6"
- process $proc$libresoc.v:189462$12902
+ attribute \src "libresoc.v:189358.3-189370.6"
+ process $proc$libresoc.v:189358$12694
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907
- assign $0\alu_spr0_spr_op__insn$next[31:0]$12904 $1\alu_spr0_spr_op__insn$next[31:0]$12908
- assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12905 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909
- assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910
- attribute \src "libresoc.v:189463.5-189463.29"
+ assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699
+ assign $0\alu_spr0_spr_op__insn$next[31:0]$12696 $1\alu_spr0_spr_op__insn$next[31:0]$12700
+ assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12697 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701
+ assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702
+ attribute \src "libresoc.v:189359.5-189359.29"
switch \initial
- attribute \src "libresoc.v:189463.9-189463.17"
+ attribute \src "libresoc.v:189359.9-189359.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910 $1\alu_spr0_spr_op__insn$next[31:0]$12908 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907 $1\alu_spr0_spr_op__insn_type$next[6:0]$12909 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
+ assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 $1\alu_spr0_spr_op__insn$next[31:0]$12700 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
case
- assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12907 \alu_spr0_spr_op__fn_unit
- assign $1\alu_spr0_spr_op__insn$next[31:0]$12908 \alu_spr0_spr_op__insn
- assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12909 \alu_spr0_spr_op__insn_type
- assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12910 \alu_spr0_spr_op__is_32bit
+ assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12699 \alu_spr0_spr_op__fn_unit
+ assign $1\alu_spr0_spr_op__insn$next[31:0]$12700 \alu_spr0_spr_op__insn
+ assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12701 \alu_spr0_spr_op__insn_type
+ assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12702 \alu_spr0_spr_op__is_32bit
end
sync always
- update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12903
- update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12904
- update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12905
- update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12906
+ update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12695
+ update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12696
+ update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12697
+ update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12698
end
- attribute \src "libresoc.v:189475.3-189496.6"
- process $proc$libresoc.v:189475$12911
+ attribute \src "libresoc.v:189371.3-189392.6"
+ process $proc$libresoc.v:189371$12703
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$12912 $2\data_r0__o$next[63:0]$12916
+ assign $0\data_r0__o$next[63:0]$12704 $2\data_r0__o$next[63:0]$12708
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$12913 $3\data_r0__o_ok$next[0:0]$12918
- attribute \src "libresoc.v:189476.5-189476.29"
+ assign $0\data_r0__o_ok$next[0:0]$12705 $3\data_r0__o_ok$next[0:0]$12710
+ attribute \src "libresoc.v:189372.5-189372.29"
switch \initial
- attribute \src "libresoc.v:189476.9-189476.17"
+ attribute \src "libresoc.v:189372.9-189372.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$12915 $1\data_r0__o$next[63:0]$12914 } { \o_ok \alu_spr0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$12707 $1\data_r0__o$next[63:0]$12706 } { \o_ok \alu_spr0_o }
case
- assign $1\data_r0__o$next[63:0]$12914 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$12915 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$12706 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$12707 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$12917 $2\data_r0__o$next[63:0]$12916 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$12709 $2\data_r0__o$next[63:0]$12708 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$12916 $1\data_r0__o$next[63:0]$12914
- assign $2\data_r0__o_ok$next[0:0]$12917 $1\data_r0__o_ok$next[0:0]$12915
+ assign $2\data_r0__o$next[63:0]$12708 $1\data_r0__o$next[63:0]$12706
+ assign $2\data_r0__o_ok$next[0:0]$12709 $1\data_r0__o_ok$next[0:0]$12707
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$12918 1'0
+ assign $3\data_r0__o_ok$next[0:0]$12710 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$12918 $2\data_r0__o_ok$next[0:0]$12917
+ assign $3\data_r0__o_ok$next[0:0]$12710 $2\data_r0__o_ok$next[0:0]$12709
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$12912
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12913
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$12704
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12705
end
- attribute \src "libresoc.v:189497.3-189518.6"
- process $proc$libresoc.v:189497$12919
+ attribute \src "libresoc.v:189393.3-189414.6"
+ process $proc$libresoc.v:189393$12711
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__spr1$next[63:0]$12920 $2\data_r1__spr1$next[63:0]$12924
+ assign $0\data_r1__spr1$next[63:0]$12712 $2\data_r1__spr1$next[63:0]$12716
assign { } { }
- assign $0\data_r1__spr1_ok$next[0:0]$12921 $3\data_r1__spr1_ok$next[0:0]$12926
- attribute \src "libresoc.v:189498.5-189498.29"
+ assign $0\data_r1__spr1_ok$next[0:0]$12713 $3\data_r1__spr1_ok$next[0:0]$12718
+ attribute \src "libresoc.v:189394.5-189394.29"
switch \initial
- attribute \src "libresoc.v:189498.9-189498.17"
+ attribute \src "libresoc.v:189394.9-189394.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__spr1_ok$next[0:0]$12923 $1\data_r1__spr1$next[63:0]$12922 } { \spr1_ok \alu_spr0_spr1 }
+ assign { $1\data_r1__spr1_ok$next[0:0]$12715 $1\data_r1__spr1$next[63:0]$12714 } { \spr1_ok \alu_spr0_spr1 }
case
- assign $1\data_r1__spr1$next[63:0]$12922 \data_r1__spr1
- assign $1\data_r1__spr1_ok$next[0:0]$12923 \data_r1__spr1_ok
+ assign $1\data_r1__spr1$next[63:0]$12714 \data_r1__spr1
+ assign $1\data_r1__spr1_ok$next[0:0]$12715 \data_r1__spr1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__spr1_ok$next[0:0]$12925 $2\data_r1__spr1$next[63:0]$12924 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__spr1_ok$next[0:0]$12717 $2\data_r1__spr1$next[63:0]$12716 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__spr1$next[63:0]$12924 $1\data_r1__spr1$next[63:0]$12922
- assign $2\data_r1__spr1_ok$next[0:0]$12925 $1\data_r1__spr1_ok$next[0:0]$12923
+ assign $2\data_r1__spr1$next[63:0]$12716 $1\data_r1__spr1$next[63:0]$12714
+ assign $2\data_r1__spr1_ok$next[0:0]$12717 $1\data_r1__spr1_ok$next[0:0]$12715
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__spr1_ok$next[0:0]$12926 1'0
+ assign $3\data_r1__spr1_ok$next[0:0]$12718 1'0
case
- assign $3\data_r1__spr1_ok$next[0:0]$12926 $2\data_r1__spr1_ok$next[0:0]$12925
+ assign $3\data_r1__spr1_ok$next[0:0]$12718 $2\data_r1__spr1_ok$next[0:0]$12717
end
sync always
- update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12920
- update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12921
+ update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12712
+ update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12713
end
- attribute \src "libresoc.v:189519.3-189540.6"
- process $proc$libresoc.v:189519$12927
+ attribute \src "libresoc.v:189415.3-189436.6"
+ process $proc$libresoc.v:189415$12719
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast1$next[63:0]$12928 $2\data_r2__fast1$next[63:0]$12932
+ assign $0\data_r2__fast1$next[63:0]$12720 $2\data_r2__fast1$next[63:0]$12724
assign { } { }
- assign $0\data_r2__fast1_ok$next[0:0]$12929 $3\data_r2__fast1_ok$next[0:0]$12934
- attribute \src "libresoc.v:189520.5-189520.29"
+ assign $0\data_r2__fast1_ok$next[0:0]$12721 $3\data_r2__fast1_ok$next[0:0]$12726
+ attribute \src "libresoc.v:189416.5-189416.29"
switch \initial
- attribute \src "libresoc.v:189520.9-189520.17"
+ attribute \src "libresoc.v:189416.9-189416.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast1_ok$next[0:0]$12931 $1\data_r2__fast1$next[63:0]$12930 } { \fast1_ok \alu_spr0_fast1 }
+ assign { $1\data_r2__fast1_ok$next[0:0]$12723 $1\data_r2__fast1$next[63:0]$12722 } { \fast1_ok \alu_spr0_fast1 }
case
- assign $1\data_r2__fast1$next[63:0]$12930 \data_r2__fast1
- assign $1\data_r2__fast1_ok$next[0:0]$12931 \data_r2__fast1_ok
+ assign $1\data_r2__fast1$next[63:0]$12722 \data_r2__fast1
+ assign $1\data_r2__fast1_ok$next[0:0]$12723 \data_r2__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast1_ok$next[0:0]$12933 $2\data_r2__fast1$next[63:0]$12932 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast1_ok$next[0:0]$12725 $2\data_r2__fast1$next[63:0]$12724 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast1$next[63:0]$12932 $1\data_r2__fast1$next[63:0]$12930
- assign $2\data_r2__fast1_ok$next[0:0]$12933 $1\data_r2__fast1_ok$next[0:0]$12931
+ assign $2\data_r2__fast1$next[63:0]$12724 $1\data_r2__fast1$next[63:0]$12722
+ assign $2\data_r2__fast1_ok$next[0:0]$12725 $1\data_r2__fast1_ok$next[0:0]$12723
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast1_ok$next[0:0]$12934 1'0
+ assign $3\data_r2__fast1_ok$next[0:0]$12726 1'0
case
- assign $3\data_r2__fast1_ok$next[0:0]$12934 $2\data_r2__fast1_ok$next[0:0]$12933
+ assign $3\data_r2__fast1_ok$next[0:0]$12726 $2\data_r2__fast1_ok$next[0:0]$12725
end
sync always
- update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12928
- update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12929
+ update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12720
+ update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12721
end
- attribute \src "libresoc.v:189541.3-189562.6"
- process $proc$libresoc.v:189541$12935
+ attribute \src "libresoc.v:189437.3-189458.6"
+ process $proc$libresoc.v:189437$12727
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__xer_so$next[0:0]$12936 $2\data_r3__xer_so$next[0:0]$12940
+ assign $0\data_r3__xer_so$next[0:0]$12728 $2\data_r3__xer_so$next[0:0]$12732
assign { } { }
- assign $0\data_r3__xer_so_ok$next[0:0]$12937 $3\data_r3__xer_so_ok$next[0:0]$12942
- attribute \src "libresoc.v:189542.5-189542.29"
+ assign $0\data_r3__xer_so_ok$next[0:0]$12729 $3\data_r3__xer_so_ok$next[0:0]$12734
+ attribute \src "libresoc.v:189438.5-189438.29"
switch \initial
- attribute \src "libresoc.v:189542.9-189542.17"
+ attribute \src "libresoc.v:189438.9-189438.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__xer_so_ok$next[0:0]$12939 $1\data_r3__xer_so$next[0:0]$12938 } { \xer_so_ok \alu_spr0_xer_so }
+ assign { $1\data_r3__xer_so_ok$next[0:0]$12731 $1\data_r3__xer_so$next[0:0]$12730 } { \xer_so_ok \alu_spr0_xer_so }
case
- assign $1\data_r3__xer_so$next[0:0]$12938 \data_r3__xer_so
- assign $1\data_r3__xer_so_ok$next[0:0]$12939 \data_r3__xer_so_ok
+ assign $1\data_r3__xer_so$next[0:0]$12730 \data_r3__xer_so
+ assign $1\data_r3__xer_so_ok$next[0:0]$12731 \data_r3__xer_so_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__xer_so_ok$next[0:0]$12941 $2\data_r3__xer_so$next[0:0]$12940 } 2'00
+ assign { $2\data_r3__xer_so_ok$next[0:0]$12733 $2\data_r3__xer_so$next[0:0]$12732 } 2'00
case
- assign $2\data_r3__xer_so$next[0:0]$12940 $1\data_r3__xer_so$next[0:0]$12938
- assign $2\data_r3__xer_so_ok$next[0:0]$12941 $1\data_r3__xer_so_ok$next[0:0]$12939
+ assign $2\data_r3__xer_so$next[0:0]$12732 $1\data_r3__xer_so$next[0:0]$12730
+ assign $2\data_r3__xer_so_ok$next[0:0]$12733 $1\data_r3__xer_so_ok$next[0:0]$12731
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__xer_so_ok$next[0:0]$12942 1'0
+ assign $3\data_r3__xer_so_ok$next[0:0]$12734 1'0
case
- assign $3\data_r3__xer_so_ok$next[0:0]$12942 $2\data_r3__xer_so_ok$next[0:0]$12941
+ assign $3\data_r3__xer_so_ok$next[0:0]$12734 $2\data_r3__xer_so_ok$next[0:0]$12733
end
sync always
- update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12936
- update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12937
+ update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12728
+ update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12729
end
- attribute \src "libresoc.v:189563.3-189584.6"
- process $proc$libresoc.v:189563$12943
+ attribute \src "libresoc.v:189459.3-189480.6"
+ process $proc$libresoc.v:189459$12735
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__xer_ov$next[1:0]$12944 $2\data_r4__xer_ov$next[1:0]$12948
+ assign $0\data_r4__xer_ov$next[1:0]$12736 $2\data_r4__xer_ov$next[1:0]$12740
assign { } { }
- assign $0\data_r4__xer_ov_ok$next[0:0]$12945 $3\data_r4__xer_ov_ok$next[0:0]$12950
- attribute \src "libresoc.v:189564.5-189564.29"
+ assign $0\data_r4__xer_ov_ok$next[0:0]$12737 $3\data_r4__xer_ov_ok$next[0:0]$12742
+ attribute \src "libresoc.v:189460.5-189460.29"
switch \initial
- attribute \src "libresoc.v:189564.9-189564.17"
+ attribute \src "libresoc.v:189460.9-189460.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__xer_ov_ok$next[0:0]$12947 $1\data_r4__xer_ov$next[1:0]$12946 } { \xer_ov_ok \alu_spr0_xer_ov }
+ assign { $1\data_r4__xer_ov_ok$next[0:0]$12739 $1\data_r4__xer_ov$next[1:0]$12738 } { \xer_ov_ok \alu_spr0_xer_ov }
case
- assign $1\data_r4__xer_ov$next[1:0]$12946 \data_r4__xer_ov
- assign $1\data_r4__xer_ov_ok$next[0:0]$12947 \data_r4__xer_ov_ok
+ assign $1\data_r4__xer_ov$next[1:0]$12738 \data_r4__xer_ov
+ assign $1\data_r4__xer_ov_ok$next[0:0]$12739 \data_r4__xer_ov_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__xer_ov_ok$next[0:0]$12949 $2\data_r4__xer_ov$next[1:0]$12948 } 3'000
+ assign { $2\data_r4__xer_ov_ok$next[0:0]$12741 $2\data_r4__xer_ov$next[1:0]$12740 } 3'000
case
- assign $2\data_r4__xer_ov$next[1:0]$12948 $1\data_r4__xer_ov$next[1:0]$12946
- assign $2\data_r4__xer_ov_ok$next[0:0]$12949 $1\data_r4__xer_ov_ok$next[0:0]$12947
+ assign $2\data_r4__xer_ov$next[1:0]$12740 $1\data_r4__xer_ov$next[1:0]$12738
+ assign $2\data_r4__xer_ov_ok$next[0:0]$12741 $1\data_r4__xer_ov_ok$next[0:0]$12739
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__xer_ov_ok$next[0:0]$12950 1'0
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12742 1'0
case
- assign $3\data_r4__xer_ov_ok$next[0:0]$12950 $2\data_r4__xer_ov_ok$next[0:0]$12949
+ assign $3\data_r4__xer_ov_ok$next[0:0]$12742 $2\data_r4__xer_ov_ok$next[0:0]$12741
end
sync always
- update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12944
- update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12945
+ update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12736
+ update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12737
end
- attribute \src "libresoc.v:189585.3-189606.6"
- process $proc$libresoc.v:189585$12951
+ attribute \src "libresoc.v:189481.3-189502.6"
+ process $proc$libresoc.v:189481$12743
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r5__xer_ca$next[1:0]$12952 $2\data_r5__xer_ca$next[1:0]$12956
+ assign $0\data_r5__xer_ca$next[1:0]$12744 $2\data_r5__xer_ca$next[1:0]$12748
assign { } { }
- assign $0\data_r5__xer_ca_ok$next[0:0]$12953 $3\data_r5__xer_ca_ok$next[0:0]$12958
- attribute \src "libresoc.v:189586.5-189586.29"
+ assign $0\data_r5__xer_ca_ok$next[0:0]$12745 $3\data_r5__xer_ca_ok$next[0:0]$12750
+ attribute \src "libresoc.v:189482.5-189482.29"
switch \initial
- attribute \src "libresoc.v:189586.9-189586.17"
+ attribute \src "libresoc.v:189482.9-189482.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r5__xer_ca_ok$next[0:0]$12955 $1\data_r5__xer_ca$next[1:0]$12954 } { \xer_ca_ok \alu_spr0_xer_ca }
+ assign { $1\data_r5__xer_ca_ok$next[0:0]$12747 $1\data_r5__xer_ca$next[1:0]$12746 } { \xer_ca_ok \alu_spr0_xer_ca }
case
- assign $1\data_r5__xer_ca$next[1:0]$12954 \data_r5__xer_ca
- assign $1\data_r5__xer_ca_ok$next[0:0]$12955 \data_r5__xer_ca_ok
+ assign $1\data_r5__xer_ca$next[1:0]$12746 \data_r5__xer_ca
+ assign $1\data_r5__xer_ca_ok$next[0:0]$12747 \data_r5__xer_ca_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r5__xer_ca_ok$next[0:0]$12957 $2\data_r5__xer_ca$next[1:0]$12956 } 3'000
+ assign { $2\data_r5__xer_ca_ok$next[0:0]$12749 $2\data_r5__xer_ca$next[1:0]$12748 } 3'000
case
- assign $2\data_r5__xer_ca$next[1:0]$12956 $1\data_r5__xer_ca$next[1:0]$12954
- assign $2\data_r5__xer_ca_ok$next[0:0]$12957 $1\data_r5__xer_ca_ok$next[0:0]$12955
+ assign $2\data_r5__xer_ca$next[1:0]$12748 $1\data_r5__xer_ca$next[1:0]$12746
+ assign $2\data_r5__xer_ca_ok$next[0:0]$12749 $1\data_r5__xer_ca_ok$next[0:0]$12747
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r5__xer_ca_ok$next[0:0]$12958 1'0
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12750 1'0
case
- assign $3\data_r5__xer_ca_ok$next[0:0]$12958 $2\data_r5__xer_ca_ok$next[0:0]$12957
+ assign $3\data_r5__xer_ca_ok$next[0:0]$12750 $2\data_r5__xer_ca_ok$next[0:0]$12749
end
sync always
- update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12952
- update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12953
+ update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12744
+ update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12745
end
- attribute \src "libresoc.v:189607.3-189616.6"
- process $proc$libresoc.v:189607$12959
+ attribute \src "libresoc.v:189503.3-189512.6"
+ process $proc$libresoc.v:189503$12751
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$12960 $1\src_r0$next[63:0]$12961
- attribute \src "libresoc.v:189608.5-189608.29"
+ assign $0\src_r0$next[63:0]$12752 $1\src_r0$next[63:0]$12753
+ attribute \src "libresoc.v:189504.5-189504.29"
switch \initial
- attribute \src "libresoc.v:189608.9-189608.17"
+ attribute \src "libresoc.v:189504.9-189504.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$12961 \src1_i
+ assign $1\src_r0$next[63:0]$12753 \src1_i
case
- assign $1\src_r0$next[63:0]$12961 \src_r0
+ assign $1\src_r0$next[63:0]$12753 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$12960
+ update \src_r0$next $0\src_r0$next[63:0]$12752
end
- attribute \src "libresoc.v:189617.3-189626.6"
- process $proc$libresoc.v:189617$12962
+ attribute \src "libresoc.v:189513.3-189522.6"
+ process $proc$libresoc.v:189513$12754
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$12963 $1\src_r1$next[63:0]$12964
- attribute \src "libresoc.v:189618.5-189618.29"
+ assign $0\src_r1$next[63:0]$12755 $1\src_r1$next[63:0]$12756
+ attribute \src "libresoc.v:189514.5-189514.29"
switch \initial
- attribute \src "libresoc.v:189618.9-189618.17"
+ attribute \src "libresoc.v:189514.9-189514.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$12964 \src2_i
+ assign $1\src_r1$next[63:0]$12756 \src2_i
case
- assign $1\src_r1$next[63:0]$12964 \src_r1
+ assign $1\src_r1$next[63:0]$12756 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$12963
+ update \src_r1$next $0\src_r1$next[63:0]$12755
end
- attribute \src "libresoc.v:189627.3-189636.6"
- process $proc$libresoc.v:189627$12965
+ attribute \src "libresoc.v:189523.3-189532.6"
+ process $proc$libresoc.v:189523$12757
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$12966 $1\src_r2$next[63:0]$12967
- attribute \src "libresoc.v:189628.5-189628.29"
+ assign $0\src_r2$next[63:0]$12758 $1\src_r2$next[63:0]$12759
+ attribute \src "libresoc.v:189524.5-189524.29"
switch \initial
- attribute \src "libresoc.v:189628.9-189628.17"
+ attribute \src "libresoc.v:189524.9-189524.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$12967 \src3_i
+ assign $1\src_r2$next[63:0]$12759 \src3_i
case
- assign $1\src_r2$next[63:0]$12967 \src_r2
+ assign $1\src_r2$next[63:0]$12759 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$12966
+ update \src_r2$next $0\src_r2$next[63:0]$12758
end
- attribute \src "libresoc.v:189637.3-189646.6"
- process $proc$libresoc.v:189637$12968
+ attribute \src "libresoc.v:189533.3-189542.6"
+ process $proc$libresoc.v:189533$12760
assign { } { }
assign { } { }
- assign $0\src_r3$next[0:0]$12969 $1\src_r3$next[0:0]$12970
- attribute \src "libresoc.v:189638.5-189638.29"
+ assign $0\src_r3$next[0:0]$12761 $1\src_r3$next[0:0]$12762
+ attribute \src "libresoc.v:189534.5-189534.29"
switch \initial
- attribute \src "libresoc.v:189638.9-189638.17"
+ attribute \src "libresoc.v:189534.9-189534.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[0:0]$12970 \src4_i
+ assign $1\src_r3$next[0:0]$12762 \src4_i
case
- assign $1\src_r3$next[0:0]$12970 \src_r3
+ assign $1\src_r3$next[0:0]$12762 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[0:0]$12969
+ update \src_r3$next $0\src_r3$next[0:0]$12761
end
- attribute \src "libresoc.v:189647.3-189656.6"
- process $proc$libresoc.v:189647$12971
+ attribute \src "libresoc.v:189543.3-189552.6"
+ process $proc$libresoc.v:189543$12763
assign { } { }
assign { } { }
- assign $0\src_r4$next[1:0]$12972 $1\src_r4$next[1:0]$12973
- attribute \src "libresoc.v:189648.5-189648.29"
+ assign $0\src_r4$next[1:0]$12764 $1\src_r4$next[1:0]$12765
+ attribute \src "libresoc.v:189544.5-189544.29"
switch \initial
- attribute \src "libresoc.v:189648.9-189648.17"
+ attribute \src "libresoc.v:189544.9-189544.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r4$next[1:0]$12973 \src5_i
+ assign $1\src_r4$next[1:0]$12765 \src5_i
case
- assign $1\src_r4$next[1:0]$12973 \src_r4
+ assign $1\src_r4$next[1:0]$12765 \src_r4
end
sync always
- update \src_r4$next $0\src_r4$next[1:0]$12972
+ update \src_r4$next $0\src_r4$next[1:0]$12764
end
- attribute \src "libresoc.v:189657.3-189666.6"
- process $proc$libresoc.v:189657$12974
+ attribute \src "libresoc.v:189553.3-189562.6"
+ process $proc$libresoc.v:189553$12766
assign { } { }
assign { } { }
- assign $0\src_r5$next[1:0]$12975 $1\src_r5$next[1:0]$12976
- attribute \src "libresoc.v:189658.5-189658.29"
+ assign $0\src_r5$next[1:0]$12767 $1\src_r5$next[1:0]$12768
+ attribute \src "libresoc.v:189554.5-189554.29"
switch \initial
- attribute \src "libresoc.v:189658.9-189658.17"
+ attribute \src "libresoc.v:189554.9-189554.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r5$next[1:0]$12976 \src6_i
+ assign $1\src_r5$next[1:0]$12768 \src6_i
case
- assign $1\src_r5$next[1:0]$12976 \src_r5
+ assign $1\src_r5$next[1:0]$12768 \src_r5
end
sync always
- update \src_r5$next $0\src_r5$next[1:0]$12975
+ update \src_r5$next $0\src_r5$next[1:0]$12767
end
- attribute \src "libresoc.v:189667.3-189675.6"
- process $proc$libresoc.v:189667$12977
+ attribute \src "libresoc.v:189563.3-189571.6"
+ process $proc$libresoc.v:189563$12769
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$12978 $1\alui_l_r_alui$next[0:0]$12979
- attribute \src "libresoc.v:189668.5-189668.29"
+ assign $0\alui_l_r_alui$next[0:0]$12770 $1\alui_l_r_alui$next[0:0]$12771
+ attribute \src "libresoc.v:189564.5-189564.29"
switch \initial
- attribute \src "libresoc.v:189668.9-189668.17"
+ attribute \src "libresoc.v:189564.9-189564.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$12979 1'1
+ assign $1\alui_l_r_alui$next[0:0]$12771 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$12979 \$98
+ assign $1\alui_l_r_alui$next[0:0]$12771 \$98
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12978
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12770
end
- attribute \src "libresoc.v:189676.3-189684.6"
- process $proc$libresoc.v:189676$12980
+ attribute \src "libresoc.v:189572.3-189580.6"
+ process $proc$libresoc.v:189572$12772
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$12981 $1\alu_l_r_alu$next[0:0]$12982
- attribute \src "libresoc.v:189677.5-189677.29"
+ assign $0\alu_l_r_alu$next[0:0]$12773 $1\alu_l_r_alu$next[0:0]$12774
+ attribute \src "libresoc.v:189573.5-189573.29"
switch \initial
- attribute \src "libresoc.v:189677.9-189677.17"
+ attribute \src "libresoc.v:189573.9-189573.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$12982 1'1
+ assign $1\alu_l_r_alu$next[0:0]$12774 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$12982 \$100
+ assign $1\alu_l_r_alu$next[0:0]$12774 \$100
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12981
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12773
end
- attribute \src "libresoc.v:189685.3-189694.6"
- process $proc$libresoc.v:189685$12983
+ attribute \src "libresoc.v:189581.3-189590.6"
+ process $proc$libresoc.v:189581$12775
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:189686.5-189686.29"
+ attribute \src "libresoc.v:189582.5-189582.29"
switch \initial
- attribute \src "libresoc.v:189686.9-189686.17"
+ attribute \src "libresoc.v:189582.9-189582.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:189695.3-189704.6"
- process $proc$libresoc.v:189695$12984
+ attribute \src "libresoc.v:189591.3-189600.6"
+ process $proc$libresoc.v:189591$12776
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:189696.5-189696.29"
+ attribute \src "libresoc.v:189592.5-189592.29"
switch \initial
- attribute \src "libresoc.v:189696.9-189696.17"
+ attribute \src "libresoc.v:189592.9-189592.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:189705.3-189714.6"
- process $proc$libresoc.v:189705$12985
+ attribute \src "libresoc.v:189601.3-189610.6"
+ process $proc$libresoc.v:189601$12777
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:189706.5-189706.29"
+ attribute \src "libresoc.v:189602.5-189602.29"
switch \initial
- attribute \src "libresoc.v:189706.9-189706.17"
+ attribute \src "libresoc.v:189602.9-189602.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:189715.3-189724.6"
- process $proc$libresoc.v:189715$12986
+ attribute \src "libresoc.v:189611.3-189620.6"
+ process $proc$libresoc.v:189611$12778
assign { } { }
assign { } { }
assign $0\dest4_o[0:0] $1\dest4_o[0:0]
- attribute \src "libresoc.v:189716.5-189716.29"
+ attribute \src "libresoc.v:189612.5-189612.29"
switch \initial
- attribute \src "libresoc.v:189716.9-189716.17"
+ attribute \src "libresoc.v:189612.9-189612.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[0:0]
end
- attribute \src "libresoc.v:189725.3-189734.6"
- process $proc$libresoc.v:189725$12987
+ attribute \src "libresoc.v:189621.3-189630.6"
+ process $proc$libresoc.v:189621$12779
assign { } { }
assign { } { }
assign $0\dest5_o[1:0] $1\dest5_o[1:0]
- attribute \src "libresoc.v:189726.5-189726.29"
+ attribute \src "libresoc.v:189622.5-189622.29"
switch \initial
- attribute \src "libresoc.v:189726.9-189726.17"
+ attribute \src "libresoc.v:189622.9-189622.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[1:0]
end
- attribute \src "libresoc.v:189735.3-189744.6"
- process $proc$libresoc.v:189735$12988
+ attribute \src "libresoc.v:189631.3-189640.6"
+ process $proc$libresoc.v:189631$12780
assign { } { }
assign { } { }
assign $0\dest6_o[1:0] $1\dest6_o[1:0]
- attribute \src "libresoc.v:189736.5-189736.29"
+ attribute \src "libresoc.v:189632.5-189632.29"
switch \initial
- attribute \src "libresoc.v:189736.9-189736.17"
+ attribute \src "libresoc.v:189632.9-189632.17"
case 1'1
case
end
sync always
update \dest6_o $0\dest6_o[1:0]
end
- attribute \src "libresoc.v:189745.3-189753.6"
- process $proc$libresoc.v:189745$12989
+ attribute \src "libresoc.v:189641.3-189649.6"
+ process $proc$libresoc.v:189641$12781
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[5:0]$12990 $1\prev_wr_go$next[5:0]$12991
- attribute \src "libresoc.v:189746.5-189746.29"
+ assign $0\prev_wr_go$next[5:0]$12782 $1\prev_wr_go$next[5:0]$12783
+ attribute \src "libresoc.v:189642.5-189642.29"
switch \initial
- attribute \src "libresoc.v:189746.9-189746.17"
+ attribute \src "libresoc.v:189642.9-189642.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[5:0]$12991 6'000000
- case
- assign $1\prev_wr_go$next[5:0]$12991 \$24
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12990
- end
- connect \$9 $not$libresoc.v:189144$12768_Y
- connect \$100 $and$libresoc.v:189145$12769_Y
- connect \$102 $and$libresoc.v:189146$12770_Y
- connect \$104 $and$libresoc.v:189147$12771_Y
- connect \$106 $not$libresoc.v:189148$12772_Y
- connect \$108 $and$libresoc.v:189149$12773_Y
- connect \$110 $and$libresoc.v:189150$12774_Y
- connect \$112 $and$libresoc.v:189151$12775_Y
- connect \$114 $and$libresoc.v:189152$12776_Y
- connect \$116 $and$libresoc.v:189153$12777_Y
- connect \$118 $and$libresoc.v:189154$12778_Y
- connect \$11 $or$libresoc.v:189155$12779_Y
- connect \$120 $and$libresoc.v:189156$12780_Y
- connect \$122 $and$libresoc.v:189157$12781_Y
- connect \$124 $and$libresoc.v:189158$12782_Y
- connect \$126 $and$libresoc.v:189159$12783_Y
- connect \$128 $and$libresoc.v:189160$12784_Y
- connect \$8 $reduce_and$libresoc.v:189161$12785_Y
- connect \$130 $and$libresoc.v:189162$12786_Y
- connect \$132 $and$libresoc.v:189163$12787_Y
- connect \$134 $and$libresoc.v:189164$12788_Y
- connect \$136 $and$libresoc.v:189165$12789_Y
- connect \$14 $and$libresoc.v:189166$12790_Y
- connect \$16 $not$libresoc.v:189167$12791_Y
- connect \$18 $and$libresoc.v:189168$12792_Y
- connect \$20 $not$libresoc.v:189169$12793_Y
- connect \$22 $and$libresoc.v:189170$12794_Y
- connect \$24 $and$libresoc.v:189171$12795_Y
- connect \$28 $not$libresoc.v:189172$12796_Y
- connect \$30 $and$libresoc.v:189173$12797_Y
- connect \$27 $reduce_or$libresoc.v:189174$12798_Y
- connect \$26 $not$libresoc.v:189175$12799_Y
- connect \$34 $and$libresoc.v:189176$12800_Y
- connect \$36 $reduce_or$libresoc.v:189177$12801_Y
- connect \$38 $reduce_or$libresoc.v:189178$12802_Y
- connect \$40 $or$libresoc.v:189179$12803_Y
- connect \$42 $not$libresoc.v:189180$12804_Y
- connect \$44 $and$libresoc.v:189181$12805_Y
- connect \$46 $and$libresoc.v:189182$12806_Y
- connect \$48 $eq$libresoc.v:189183$12807_Y
- connect \$50 $and$libresoc.v:189184$12808_Y
- connect \$52 $eq$libresoc.v:189185$12809_Y
- connect \$54 $and$libresoc.v:189186$12810_Y
- connect \$56 $and$libresoc.v:189187$12811_Y
- connect \$58 $and$libresoc.v:189188$12812_Y
- connect \$60 $or$libresoc.v:189189$12813_Y
- connect \$62 $or$libresoc.v:189190$12814_Y
- connect \$64 $or$libresoc.v:189191$12815_Y
- connect \$66 $or$libresoc.v:189192$12816_Y
- connect \$68 $and$libresoc.v:189193$12817_Y
- connect \$6 $and$libresoc.v:189194$12818_Y
- connect \$70 $and$libresoc.v:189195$12819_Y
- connect \$72 $or$libresoc.v:189196$12820_Y
- connect \$74 $and$libresoc.v:189197$12821_Y
- connect \$76 $and$libresoc.v:189198$12822_Y
- connect \$78 $and$libresoc.v:189199$12823_Y
- connect \$80 $and$libresoc.v:189200$12824_Y
- connect \$82 $and$libresoc.v:189201$12825_Y
- connect \$84 $and$libresoc.v:189202$12826_Y
- connect \$86 $ternary$libresoc.v:189203$12827_Y
- connect \$88 $ternary$libresoc.v:189204$12828_Y
- connect \$90 $ternary$libresoc.v:189205$12829_Y
- connect \$92 $ternary$libresoc.v:189206$12830_Y
- connect \$94 $ternary$libresoc.v:189207$12831_Y
- connect \$96 $ternary$libresoc.v:189208$12832_Y
- connect \$98 $and$libresoc.v:189209$12833_Y
+ assign $1\prev_wr_go$next[5:0]$12783 6'000000
+ case
+ assign $1\prev_wr_go$next[5:0]$12783 \$24
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12782
+ end
+ connect \$9 $not$libresoc.v:189040$12560_Y
+ connect \$100 $and$libresoc.v:189041$12561_Y
+ connect \$102 $and$libresoc.v:189042$12562_Y
+ connect \$104 $and$libresoc.v:189043$12563_Y
+ connect \$106 $not$libresoc.v:189044$12564_Y
+ connect \$108 $and$libresoc.v:189045$12565_Y
+ connect \$110 $and$libresoc.v:189046$12566_Y
+ connect \$112 $and$libresoc.v:189047$12567_Y
+ connect \$114 $and$libresoc.v:189048$12568_Y
+ connect \$116 $and$libresoc.v:189049$12569_Y
+ connect \$118 $and$libresoc.v:189050$12570_Y
+ connect \$11 $or$libresoc.v:189051$12571_Y
+ connect \$120 $and$libresoc.v:189052$12572_Y
+ connect \$122 $and$libresoc.v:189053$12573_Y
+ connect \$124 $and$libresoc.v:189054$12574_Y
+ connect \$126 $and$libresoc.v:189055$12575_Y
+ connect \$128 $and$libresoc.v:189056$12576_Y
+ connect \$8 $reduce_and$libresoc.v:189057$12577_Y
+ connect \$130 $and$libresoc.v:189058$12578_Y
+ connect \$132 $and$libresoc.v:189059$12579_Y
+ connect \$134 $and$libresoc.v:189060$12580_Y
+ connect \$136 $and$libresoc.v:189061$12581_Y
+ connect \$14 $and$libresoc.v:189062$12582_Y
+ connect \$16 $not$libresoc.v:189063$12583_Y
+ connect \$18 $and$libresoc.v:189064$12584_Y
+ connect \$20 $not$libresoc.v:189065$12585_Y
+ connect \$22 $and$libresoc.v:189066$12586_Y
+ connect \$24 $and$libresoc.v:189067$12587_Y
+ connect \$28 $not$libresoc.v:189068$12588_Y
+ connect \$30 $and$libresoc.v:189069$12589_Y
+ connect \$27 $reduce_or$libresoc.v:189070$12590_Y
+ connect \$26 $not$libresoc.v:189071$12591_Y
+ connect \$34 $and$libresoc.v:189072$12592_Y
+ connect \$36 $reduce_or$libresoc.v:189073$12593_Y
+ connect \$38 $reduce_or$libresoc.v:189074$12594_Y
+ connect \$40 $or$libresoc.v:189075$12595_Y
+ connect \$42 $not$libresoc.v:189076$12596_Y
+ connect \$44 $and$libresoc.v:189077$12597_Y
+ connect \$46 $and$libresoc.v:189078$12598_Y
+ connect \$48 $eq$libresoc.v:189079$12599_Y
+ connect \$50 $and$libresoc.v:189080$12600_Y
+ connect \$52 $eq$libresoc.v:189081$12601_Y
+ connect \$54 $and$libresoc.v:189082$12602_Y
+ connect \$56 $and$libresoc.v:189083$12603_Y
+ connect \$58 $and$libresoc.v:189084$12604_Y
+ connect \$60 $or$libresoc.v:189085$12605_Y
+ connect \$62 $or$libresoc.v:189086$12606_Y
+ connect \$64 $or$libresoc.v:189087$12607_Y
+ connect \$66 $or$libresoc.v:189088$12608_Y
+ connect \$68 $and$libresoc.v:189089$12609_Y
+ connect \$6 $and$libresoc.v:189090$12610_Y
+ connect \$70 $and$libresoc.v:189091$12611_Y
+ connect \$72 $or$libresoc.v:189092$12612_Y
+ connect \$74 $and$libresoc.v:189093$12613_Y
+ connect \$76 $and$libresoc.v:189094$12614_Y
+ connect \$78 $and$libresoc.v:189095$12615_Y
+ connect \$80 $and$libresoc.v:189096$12616_Y
+ connect \$82 $and$libresoc.v:189097$12617_Y
+ connect \$84 $and$libresoc.v:189098$12618_Y
+ connect \$86 $ternary$libresoc.v:189099$12619_Y
+ connect \$88 $ternary$libresoc.v:189100$12620_Y
+ connect \$90 $ternary$libresoc.v:189101$12621_Y
+ connect \$92 $ternary$libresoc.v:189102$12622_Y
+ connect \$94 $ternary$libresoc.v:189103$12623_Y
+ connect \$96 $ternary$libresoc.v:189104$12624_Y
+ connect \$98 $and$libresoc.v:189105$12625_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$124
connect \all_rd_dly$next \all_rd
connect \all_rd \$14
end
-attribute \src "libresoc.v:189789.1-190313.10"
+attribute \src "libresoc.v:189685.1-190209.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main"
attribute \generator "nMigen"
module \spr_main
- attribute \src "libresoc.v:190062.3-190077.6"
- wire width 64 $0\fast1$7[63:0]$13038
- attribute \src "libresoc.v:190143.3-190158.6"
+ attribute \src "libresoc.v:189958.3-189973.6"
+ wire width 64 $0\fast1$7[63:0]$12830
+ attribute \src "libresoc.v:190039.3-190054.6"
wire $0\fast1_ok[0:0]
- attribute \src "libresoc.v:189790.7-189790.20"
+ attribute \src "libresoc.v:189686.7-189686.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire width 64 $0\o[63:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire $0\o_ok[0:0]
- attribute \src "libresoc.v:190291.3-190309.6"
- wire width 64 $0\spr1$6[63:0]$13063
- attribute \src "libresoc.v:190078.3-190096.6"
+ attribute \src "libresoc.v:190187.3-190205.6"
+ wire width 64 $0\spr1$6[63:0]$12855
+ attribute \src "libresoc.v:189974.3-189992.6"
wire $0\spr1_ok[0:0]
- attribute \src "libresoc.v:190246.3-190269.6"
- wire width 2 $0\xer_ca$10[1:0]$13057
- attribute \src "libresoc.v:190270.3-190290.6"
+ attribute \src "libresoc.v:190142.3-190165.6"
+ wire width 2 $0\xer_ca$10[1:0]$12849
+ attribute \src "libresoc.v:190166.3-190186.6"
wire $0\xer_ca_ok[0:0]
- attribute \src "libresoc.v:190201.3-190224.6"
- wire width 2 $0\xer_ov$9[1:0]$13051
- attribute \src "libresoc.v:190225.3-190245.6"
+ attribute \src "libresoc.v:190097.3-190120.6"
+ wire width 2 $0\xer_ov$9[1:0]$12843
+ attribute \src "libresoc.v:190121.3-190141.6"
wire $0\xer_ov_ok[0:0]
- attribute \src "libresoc.v:190159.3-190179.6"
- wire $0\xer_so$8[0:0]$13045
- attribute \src "libresoc.v:190180.3-190200.6"
+ attribute \src "libresoc.v:190055.3-190075.6"
+ wire $0\xer_so$8[0:0]$12837
+ attribute \src "libresoc.v:190076.3-190096.6"
wire $0\xer_so_ok[0:0]
- attribute \src "libresoc.v:190062.3-190077.6"
- wire width 64 $1\fast1$7[63:0]$13039
- attribute \src "libresoc.v:190143.3-190158.6"
+ attribute \src "libresoc.v:189958.3-189973.6"
+ wire width 64 $1\fast1$7[63:0]$12831
+ attribute \src "libresoc.v:190039.3-190054.6"
wire $1\fast1_ok[0:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire width 64 $1\o[63:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire $1\o_ok[0:0]
- attribute \src "libresoc.v:190291.3-190309.6"
- wire width 64 $1\spr1$6[63:0]$13064
- attribute \src "libresoc.v:190078.3-190096.6"
+ attribute \src "libresoc.v:190187.3-190205.6"
+ wire width 64 $1\spr1$6[63:0]$12856
+ attribute \src "libresoc.v:189974.3-189992.6"
wire $1\spr1_ok[0:0]
- attribute \src "libresoc.v:190246.3-190269.6"
- wire width 2 $1\xer_ca$10[1:0]$13058
- attribute \src "libresoc.v:190270.3-190290.6"
+ attribute \src "libresoc.v:190142.3-190165.6"
+ wire width 2 $1\xer_ca$10[1:0]$12850
+ attribute \src "libresoc.v:190166.3-190186.6"
wire $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:190201.3-190224.6"
- wire width 2 $1\xer_ov$9[1:0]$13052
- attribute \src "libresoc.v:190225.3-190245.6"
+ attribute \src "libresoc.v:190097.3-190120.6"
+ wire width 2 $1\xer_ov$9[1:0]$12844
+ attribute \src "libresoc.v:190121.3-190141.6"
wire $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:190159.3-190179.6"
- wire $1\xer_so$8[0:0]$13046
- attribute \src "libresoc.v:190180.3-190200.6"
+ attribute \src "libresoc.v:190055.3-190075.6"
+ wire $1\xer_so$8[0:0]$12838
+ attribute \src "libresoc.v:190076.3-190096.6"
wire $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:190062.3-190077.6"
- wire width 64 $2\fast1$7[63:0]$13040
- attribute \src "libresoc.v:190143.3-190158.6"
+ attribute \src "libresoc.v:189958.3-189973.6"
+ wire width 64 $2\fast1$7[63:0]$12832
+ attribute \src "libresoc.v:190039.3-190054.6"
wire $2\fast1_ok[0:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire width 64 $2\o[63:0]
- attribute \src "libresoc.v:190291.3-190309.6"
- wire width 64 $2\spr1$6[63:0]$13065
- attribute \src "libresoc.v:190078.3-190096.6"
+ attribute \src "libresoc.v:190187.3-190205.6"
+ wire width 64 $2\spr1$6[63:0]$12857
+ attribute \src "libresoc.v:189974.3-189992.6"
wire $2\spr1_ok[0:0]
- attribute \src "libresoc.v:190246.3-190269.6"
- wire width 2 $2\xer_ca$10[1:0]$13059
- attribute \src "libresoc.v:190270.3-190290.6"
+ attribute \src "libresoc.v:190142.3-190165.6"
+ wire width 2 $2\xer_ca$10[1:0]$12851
+ attribute \src "libresoc.v:190166.3-190186.6"
wire $2\xer_ca_ok[0:0]
- attribute \src "libresoc.v:190201.3-190224.6"
- wire width 2 $2\xer_ov$9[1:0]$13053
- attribute \src "libresoc.v:190225.3-190245.6"
+ attribute \src "libresoc.v:190097.3-190120.6"
+ wire width 2 $2\xer_ov$9[1:0]$12845
+ attribute \src "libresoc.v:190121.3-190141.6"
wire $2\xer_ov_ok[0:0]
- attribute \src "libresoc.v:190159.3-190179.6"
- wire $2\xer_so$8[0:0]$13047
- attribute \src "libresoc.v:190180.3-190200.6"
+ attribute \src "libresoc.v:190055.3-190075.6"
+ wire $2\xer_so$8[0:0]$12839
+ attribute \src "libresoc.v:190076.3-190096.6"
wire $2\xer_so_ok[0:0]
- attribute \src "libresoc.v:190097.3-190142.6"
+ attribute \src "libresoc.v:189993.3-190038.6"
wire width 46 $3\o[63:18]
- attribute \src "libresoc.v:190246.3-190269.6"
- wire width 2 $3\xer_ca$10[1:0]$13060
- attribute \src "libresoc.v:190270.3-190290.6"
+ attribute \src "libresoc.v:190142.3-190165.6"
+ wire width 2 $3\xer_ca$10[1:0]$12852
+ attribute \src "libresoc.v:190166.3-190186.6"
wire $3\xer_ca_ok[0:0]
- attribute \src "libresoc.v:190201.3-190224.6"
- wire width 2 $3\xer_ov$9[1:0]$13054
- attribute \src "libresoc.v:190225.3-190245.6"
+ attribute \src "libresoc.v:190097.3-190120.6"
+ wire width 2 $3\xer_ov$9[1:0]$12846
+ attribute \src "libresoc.v:190121.3-190141.6"
wire $3\xer_ov_ok[0:0]
- attribute \src "libresoc.v:190159.3-190179.6"
- wire $3\xer_so$8[0:0]$13048
- attribute \src "libresoc.v:190180.3-190200.6"
+ attribute \src "libresoc.v:190055.3-190075.6"
+ wire $3\xer_so$8[0:0]$12840
+ attribute \src "libresoc.v:190076.3-190096.6"
wire $3\xer_so_ok[0:0]
- attribute \src "libresoc.v:190055.18-190055.106"
- wire $eq$libresoc.v:190055$13030_Y
- attribute \src "libresoc.v:190056.18-190056.106"
- wire $eq$libresoc.v:190056$13031_Y
- attribute \src "libresoc.v:190057.18-190057.106"
- wire $eq$libresoc.v:190057$13032_Y
- attribute \src "libresoc.v:190058.18-190058.106"
- wire $eq$libresoc.v:190058$13033_Y
- attribute \src "libresoc.v:190059.18-190059.106"
- wire $eq$libresoc.v:190059$13034_Y
- attribute \src "libresoc.v:190060.18-190060.106"
- wire $eq$libresoc.v:190060$13035_Y
- attribute \src "libresoc.v:190061.18-190061.106"
- wire $eq$libresoc.v:190061$13036_Y
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "libresoc.v:189951.18-189951.106"
+ wire $eq$libresoc.v:189951$12822_Y
+ attribute \src "libresoc.v:189952.18-189952.106"
+ wire $eq$libresoc.v:189952$12823_Y
+ attribute \src "libresoc.v:189953.18-189953.106"
+ wire $eq$libresoc.v:189953$12824_Y
+ attribute \src "libresoc.v:189954.18-189954.106"
+ wire $eq$libresoc.v:189954$12825_Y
+ attribute \src "libresoc.v:189955.18-189955.106"
+ wire $eq$libresoc.v:189955$12826_Y
+ attribute \src "libresoc.v:189956.18-189956.106"
+ wire $eq$libresoc.v:189956$12827_Y
+ attribute \src "libresoc.v:189957.18-189957.106"
+ wire $eq$libresoc.v:189957$12828_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
wire \$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90"
wire \$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 7 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 20 \fast1$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 21 \fast1_ok
- attribute \src "libresoc.v:189790.7-189790.15"
+ attribute \src "libresoc.v:189686.7-189686.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 input 28 \muxid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45"
wire width 2 output 11 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 16 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 17 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 5 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50"
wire width 10 \spr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 input 6 \spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 output 18 \spr1$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 19 \spr1_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
wire output 15 \spr_op__is_32bit$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 10 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 26 \xer_ca$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 27 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 2 input 9 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 2 output 24 \xer_ov$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire input 8 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 22 \xer_so$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 23 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190055$13030
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189951$12822
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190055$13030_Y
+ connect \Y $eq$libresoc.v:189951$12822_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190056$13031
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189952$12823
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190056$13031_Y
+ connect \Y $eq$libresoc.v:189952$12823_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190057$13032
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189953$12824
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190057$13032_Y
+ connect \Y $eq$libresoc.v:189953$12824_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190058$13033
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189954$12825
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190058$13033_Y
+ connect \Y $eq$libresoc.v:189954$12825_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190059$13034
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189955$12826
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190059$13034_Y
+ connect \Y $eq$libresoc.v:189955$12826_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
- cell $eq $eq$libresoc.v:190060$13035
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
+ cell $eq $eq$libresoc.v:189956$12827
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190060$13035_Y
+ connect \Y $eq$libresoc.v:189956$12827_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82"
- cell $eq $eq$libresoc.v:190061$13036
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90"
+ cell $eq $eq$libresoc.v:189957$12828
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \spr
connect \B 10'0000000001
- connect \Y $eq$libresoc.v:190061$13036_Y
+ connect \Y $eq$libresoc.v:189957$12828_Y
end
- attribute \src "libresoc.v:189790.7-189790.20"
- process $proc$libresoc.v:189790$13066
+ attribute \src "libresoc.v:189686.7-189686.20"
+ process $proc$libresoc.v:189686$12858
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190062.3-190077.6"
- process $proc$libresoc.v:190062$13037
+ attribute \src "libresoc.v:189958.3-189973.6"
+ process $proc$libresoc.v:189958$12829
assign { } { }
assign { } { }
- assign $0\fast1$7[63:0]$13038 $1\fast1$7[63:0]$13039
- attribute \src "libresoc.v:190063.5-190063.29"
+ assign $0\fast1$7[63:0]$12830 $1\fast1$7[63:0]$12831
+ attribute \src "libresoc.v:189959.5-189959.29"
switch \initial
- attribute \src "libresoc.v:190063.9-190063.17"
+ attribute \src "libresoc.v:189959.9-189959.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\fast1$7[63:0]$13039 $2\fast1$7[63:0]$13040
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ assign $1\fast1$7[63:0]$12831 $2\fast1$7[63:0]$12832
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\fast1$7[63:0]$13040 \ra
+ assign $2\fast1$7[63:0]$12832 \ra
case
- assign $2\fast1$7[63:0]$13040 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\fast1$7[63:0]$12832 64'0000000000000000000000000000000000000000000000000000000000000000
end
case
- assign $1\fast1$7[63:0]$13039 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\fast1$7[63:0]$12831 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \fast1$7 $0\fast1$7[63:0]$13038
+ update \fast1$7 $0\fast1$7[63:0]$12830
end
- attribute \src "libresoc.v:190078.3-190096.6"
- process $proc$libresoc.v:190078$13041
+ attribute \src "libresoc.v:189974.3-189992.6"
+ process $proc$libresoc.v:189974$12833
assign { } { }
assign { } { }
assign $0\spr1_ok[0:0] $1\spr1_ok[0:0]
- attribute \src "libresoc.v:190079.5-190079.29"
+ attribute \src "libresoc.v:189975.5-189975.29"
switch \initial
- attribute \src "libresoc.v:190079.9-190079.17"
+ attribute \src "libresoc.v:189975.9-189975.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\spr1_ok[0:0] $2\spr1_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
sync always
update \spr1_ok $0\spr1_ok[0:0]
end
- attribute \src "libresoc.v:190097.3-190142.6"
- process $proc$libresoc.v:190097$13042
+ attribute \src "libresoc.v:189993.3-190038.6"
+ process $proc$libresoc.v:189993$12834
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $0\o_ok[0:0] $1\o_ok[0:0]
assign $0\o[63:0] $1\o[63:0]
- attribute \src "libresoc.v:190098.5-190098.29"
+ attribute \src "libresoc.v:189994.5-189994.29"
switch \initial
- attribute \src "libresoc.v:190098.9-190098.17"
+ attribute \src "libresoc.v:189994.9-189994.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\o_ok[0:0] 1'1
assign $1\o[63:0] $2\o[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100
assign { } { }
assign $2\o[63:0] [17:0] \fast1 [17:0]
assign $2\o[63:0] [63:18] $3\o[63:18]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90"
switch \$23
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \o_ok $0\o_ok[0:0]
update \o $0\o[63:0]
end
- attribute \src "libresoc.v:190143.3-190158.6"
- process $proc$libresoc.v:190143$13043
+ attribute \src "libresoc.v:190039.3-190054.6"
+ process $proc$libresoc.v:190039$12835
assign { } { }
assign { } { }
assign $0\fast1_ok[0:0] $1\fast1_ok[0:0]
- attribute \src "libresoc.v:190144.5-190144.29"
+ attribute \src "libresoc.v:190040.5-190040.29"
switch \initial
- attribute \src "libresoc.v:190144.9-190144.17"
+ attribute \src "libresoc.v:190040.9-190040.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\fast1_ok[0:0] $2\fast1_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
sync always
update \fast1_ok $0\fast1_ok[0:0]
end
- attribute \src "libresoc.v:190159.3-190179.6"
- process $proc$libresoc.v:190159$13044
+ attribute \src "libresoc.v:190055.3-190075.6"
+ process $proc$libresoc.v:190055$12836
assign { } { }
assign { } { }
- assign $0\xer_so$8[0:0]$13045 $1\xer_so$8[0:0]$13046
- attribute \src "libresoc.v:190160.5-190160.29"
+ assign $0\xer_so$8[0:0]$12837 $1\xer_so$8[0:0]$12838
+ attribute \src "libresoc.v:190056.5-190056.29"
switch \initial
- attribute \src "libresoc.v:190160.9-190160.17"
+ attribute \src "libresoc.v:190056.9-190056.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_so$8[0:0]$13046 $2\xer_so$8[0:0]$13047
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ assign $1\xer_so$8[0:0]$12838 $2\xer_so$8[0:0]$12839
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_so$8[0:0]$13047 $3\xer_so$8[0:0]$13048
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ assign $2\xer_so$8[0:0]$12839 $3\xer_so$8[0:0]$12840
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$11
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_so$8[0:0]$13048 \ra [31]
+ assign $3\xer_so$8[0:0]$12840 \ra [31]
case
- assign $3\xer_so$8[0:0]$13048 1'0
+ assign $3\xer_so$8[0:0]$12840 1'0
end
case
- assign $2\xer_so$8[0:0]$13047 1'0
+ assign $2\xer_so$8[0:0]$12839 1'0
end
case
- assign $1\xer_so$8[0:0]$13046 1'0
+ assign $1\xer_so$8[0:0]$12838 1'0
end
sync always
- update \xer_so$8 $0\xer_so$8[0:0]$13045
+ update \xer_so$8 $0\xer_so$8[0:0]$12837
end
- attribute \src "libresoc.v:190180.3-190200.6"
- process $proc$libresoc.v:190180$13049
+ attribute \src "libresoc.v:190076.3-190096.6"
+ process $proc$libresoc.v:190076$12841
assign { } { }
assign { } { }
assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0]
- attribute \src "libresoc.v:190181.5-190181.29"
+ attribute \src "libresoc.v:190077.5-190077.29"
switch \initial
- attribute \src "libresoc.v:190181.9-190181.17"
+ attribute \src "libresoc.v:190077.9-190077.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$13
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \xer_so_ok $0\xer_so_ok[0:0]
end
- attribute \src "libresoc.v:190201.3-190224.6"
- process $proc$libresoc.v:190201$13050
+ attribute \src "libresoc.v:190097.3-190120.6"
+ process $proc$libresoc.v:190097$12842
assign { } { }
assign { } { }
- assign $0\xer_ov$9[1:0]$13051 $1\xer_ov$9[1:0]$13052
- attribute \src "libresoc.v:190202.5-190202.29"
+ assign $0\xer_ov$9[1:0]$12843 $1\xer_ov$9[1:0]$12844
+ attribute \src "libresoc.v:190098.5-190098.29"
switch \initial
- attribute \src "libresoc.v:190202.9-190202.17"
+ attribute \src "libresoc.v:190098.9-190098.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ov$9[1:0]$13052 $2\xer_ov$9[1:0]$13053
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ assign $1\xer_ov$9[1:0]$12844 $2\xer_ov$9[1:0]$12845
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ov$9[1:0]$13053 $3\xer_ov$9[1:0]$13054
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ assign $2\xer_ov$9[1:0]$12845 $3\xer_ov$9[1:0]$12846
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$15
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ov$9[1:0]$13054 [0] \ra [30]
- assign $3\xer_ov$9[1:0]$13054 [1] \ra [19]
+ assign $3\xer_ov$9[1:0]$12846 [0] \ra [30]
+ assign $3\xer_ov$9[1:0]$12846 [1] \ra [19]
case
- assign $3\xer_ov$9[1:0]$13054 2'00
+ assign $3\xer_ov$9[1:0]$12846 2'00
end
case
- assign $2\xer_ov$9[1:0]$13053 2'00
+ assign $2\xer_ov$9[1:0]$12845 2'00
end
case
- assign $1\xer_ov$9[1:0]$13052 2'00
+ assign $1\xer_ov$9[1:0]$12844 2'00
end
sync always
- update \xer_ov$9 $0\xer_ov$9[1:0]$13051
+ update \xer_ov$9 $0\xer_ov$9[1:0]$12843
end
- attribute \src "libresoc.v:190225.3-190245.6"
- process $proc$libresoc.v:190225$13055
+ attribute \src "libresoc.v:190121.3-190141.6"
+ process $proc$libresoc.v:190121$12847
assign { } { }
assign { } { }
assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0]
- attribute \src "libresoc.v:190226.5-190226.29"
+ attribute \src "libresoc.v:190122.5-190122.29"
switch \initial
- attribute \src "libresoc.v:190226.9-190226.17"
+ attribute \src "libresoc.v:190122.9-190122.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \xer_ov_ok $0\xer_ov_ok[0:0]
end
- attribute \src "libresoc.v:190246.3-190269.6"
- process $proc$libresoc.v:190246$13056
+ attribute \src "libresoc.v:190142.3-190165.6"
+ process $proc$libresoc.v:190142$12848
assign { } { }
assign { } { }
- assign $0\xer_ca$10[1:0]$13057 $1\xer_ca$10[1:0]$13058
- attribute \src "libresoc.v:190247.5-190247.29"
+ assign $0\xer_ca$10[1:0]$12849 $1\xer_ca$10[1:0]$12850
+ attribute \src "libresoc.v:190143.5-190143.29"
switch \initial
- attribute \src "libresoc.v:190247.9-190247.17"
+ attribute \src "libresoc.v:190143.9-190143.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\xer_ca$10[1:0]$13058 $2\xer_ca$10[1:0]$13059
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ assign $1\xer_ca$10[1:0]$12850 $2\xer_ca$10[1:0]$12851
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
- assign $2\xer_ca$10[1:0]$13059 $3\xer_ca$10[1:0]$13060
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ assign $2\xer_ca$10[1:0]$12851 $3\xer_ca$10[1:0]$12852
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\xer_ca$10[1:0]$13060 [0] \ra [29]
- assign $3\xer_ca$10[1:0]$13060 [1] \ra [18]
+ assign $3\xer_ca$10[1:0]$12852 [0] \ra [29]
+ assign $3\xer_ca$10[1:0]$12852 [1] \ra [18]
case
- assign $3\xer_ca$10[1:0]$13060 2'00
+ assign $3\xer_ca$10[1:0]$12852 2'00
end
case
- assign $2\xer_ca$10[1:0]$13059 2'00
+ assign $2\xer_ca$10[1:0]$12851 2'00
end
case
- assign $1\xer_ca$10[1:0]$13058 2'00
+ assign $1\xer_ca$10[1:0]$12850 2'00
end
sync always
- update \xer_ca$10 $0\xer_ca$10[1:0]$13057
+ update \xer_ca$10 $0\xer_ca$10[1:0]$12849
end
- attribute \src "libresoc.v:190270.3-190290.6"
- process $proc$libresoc.v:190270$13061
+ attribute \src "libresoc.v:190166.3-190186.6"
+ process $proc$libresoc.v:190166$12853
assign { } { }
assign { } { }
assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0]
- attribute \src "libresoc.v:190271.5-190271.29"
+ attribute \src "libresoc.v:190167.5-190167.29"
switch \initial
- attribute \src "libresoc.v:190271.9-190271.17"
+ attribute \src "libresoc.v:190167.9-190167.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
assign { } { }
assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64"
switch \$21
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \xer_ca_ok $0\xer_ca_ok[0:0]
end
- attribute \src "libresoc.v:190291.3-190309.6"
- process $proc$libresoc.v:190291$13062
+ attribute \src "libresoc.v:190187.3-190205.6"
+ process $proc$libresoc.v:190187$12854
assign { } { }
assign { } { }
- assign $0\spr1$6[63:0]$13063 $1\spr1$6[63:0]$13064
- attribute \src "libresoc.v:190292.5-190292.29"
+ assign $0\spr1$6[63:0]$12855 $1\spr1$6[63:0]$12856
+ attribute \src "libresoc.v:190188.5-190188.29"
switch \initial
- attribute \src "libresoc.v:190292.9-190292.17"
+ attribute \src "libresoc.v:190188.9-190188.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54"
switch \spr_op__insn_type
attribute \src "libresoc.v:0.0-0.0"
case 7'0110001
assign { } { }
- assign $1\spr1$6[63:0]$13064 $2\spr1$6[63:0]$13065
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49"
+ assign $1\spr1$6[63:0]$12856 $2\spr1$6[63:0]$12857
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57"
switch \spr
attribute \src "libresoc.v:0.0-0.0"
case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110
- assign $2\spr1$6[63:0]$13065 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\spr1$6[63:0]$12857 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\spr1$6[63:0]$13065 \ra
+ assign $2\spr1$6[63:0]$12857 \ra
end
case
- assign $1\spr1$6[63:0]$13064 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\spr1$6[63:0]$12856 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \spr1$6 $0\spr1$6[63:0]$13063
+ update \spr1$6 $0\spr1$6[63:0]$12855
end
- connect \$11 $eq$libresoc.v:190055$13030_Y
- connect \$13 $eq$libresoc.v:190056$13031_Y
- connect \$15 $eq$libresoc.v:190057$13032_Y
- connect \$17 $eq$libresoc.v:190058$13033_Y
- connect \$19 $eq$libresoc.v:190059$13034_Y
- connect \$21 $eq$libresoc.v:190060$13035_Y
- connect \$23 $eq$libresoc.v:190061$13036_Y
+ connect \$11 $eq$libresoc.v:189951$12822_Y
+ connect \$13 $eq$libresoc.v:189952$12823_Y
+ connect \$15 $eq$libresoc.v:189953$12824_Y
+ connect \$17 $eq$libresoc.v:189954$12825_Y
+ connect \$19 $eq$libresoc.v:189955$12826_Y
+ connect \$21 $eq$libresoc.v:189956$12827_Y
+ connect \$23 $eq$libresoc.v:189957$12828_Y
connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
connect \muxid$1 \muxid
connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] }
end
-attribute \src "libresoc.v:190317.1-191783.10"
+attribute \src "libresoc.v:190213.1-191679.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
attribute \generator "nMigen"
module \sprmap
- attribute \src "libresoc.v:190447.3-190768.6"
+ attribute \src "libresoc.v:190343.3-190664.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:190769.3-191090.6"
+ attribute \src "libresoc.v:190665.3-190986.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:190318.7-190318.20"
+ attribute \src "libresoc.v:190214.7-190214.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:191091.3-191436.6"
+ attribute \src "libresoc.v:190987.3-191332.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:191437.3-191782.6"
+ attribute \src "libresoc.v:191333.3-191678.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:190447.3-190768.6"
+ attribute \src "libresoc.v:190343.3-190664.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:190769.3-191090.6"
+ attribute \src "libresoc.v:190665.3-190986.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:191091.3-191436.6"
+ attribute \src "libresoc.v:190987.3-191332.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:191437.3-191782.6"
+ attribute \src "libresoc.v:191333.3-191678.6"
wire $1\spr_o_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 3 \fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:190318.7-190318.15"
+ attribute \src "libresoc.v:190214.7-190214.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
wire width 10 input 5 \spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 1 \spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:190318.7-190318.20"
- process $proc$libresoc.v:190318$13071
+ attribute \src "libresoc.v:190214.7-190214.20"
+ process $proc$libresoc.v:190214$12863
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:190447.3-190768.6"
- process $proc$libresoc.v:190447$13067
+ attribute \src "libresoc.v:190343.3-190664.6"
+ process $proc$libresoc.v:190343$12859
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:190448.5-190448.29"
+ attribute \src "libresoc.v:190344.5-190344.29"
switch \initial
- attribute \src "libresoc.v:190448.9-190448.17"
+ attribute \src "libresoc.v:190344.9-190344.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:190769.3-191090.6"
- process $proc$libresoc.v:190769$13068
+ attribute \src "libresoc.v:190665.3-190986.6"
+ process $proc$libresoc.v:190665$12860
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:190770.5-190770.29"
+ attribute \src "libresoc.v:190666.5-190666.29"
switch \initial
- attribute \src "libresoc.v:190770.9-190770.17"
+ attribute \src "libresoc.v:190666.9-190666.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:191091.3-191436.6"
- process $proc$libresoc.v:191091$13069
+ attribute \src "libresoc.v:190987.3-191332.6"
+ process $proc$libresoc.v:190987$12861
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:191092.5-191092.29"
+ attribute \src "libresoc.v:190988.5-190988.29"
switch \initial
- attribute \src "libresoc.v:191092.9-191092.17"
+ attribute \src "libresoc.v:190988.9-190988.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:191437.3-191782.6"
- process $proc$libresoc.v:191437$13070
+ attribute \src "libresoc.v:191333.3-191678.6"
+ process $proc$libresoc.v:191333$12862
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:191438.5-191438.29"
+ attribute \src "libresoc.v:191334.5-191334.29"
switch \initial
- attribute \src "libresoc.v:191438.9-191438.17"
+ attribute \src "libresoc.v:191334.9-191334.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:191787.1-193253.10"
+attribute \src "libresoc.v:191683.1-193149.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
attribute \generator "nMigen"
module \sprmap$174
- attribute \src "libresoc.v:191917.3-192238.6"
+ attribute \src "libresoc.v:191813.3-192134.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:192239.3-192560.6"
+ attribute \src "libresoc.v:192135.3-192456.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:191788.7-191788.20"
+ attribute \src "libresoc.v:191684.7-191684.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:192561.3-192906.6"
+ attribute \src "libresoc.v:192457.3-192802.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:192907.3-193252.6"
+ attribute \src "libresoc.v:192803.3-193148.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:191917.3-192238.6"
+ attribute \src "libresoc.v:191813.3-192134.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:192239.3-192560.6"
+ attribute \src "libresoc.v:192135.3-192456.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:192561.3-192906.6"
+ attribute \src "libresoc.v:192457.3-192802.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:192907.3-193252.6"
+ attribute \src "libresoc.v:192803.3-193148.6"
wire $1\spr_o_ok[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 output 3 \fast_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:191788.7-191788.15"
+ attribute \src "libresoc.v:191684.7-191684.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
wire width 10 input 5 \spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 output 1 \spr_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:191788.7-191788.20"
- process $proc$libresoc.v:191788$13076
+ attribute \src "libresoc.v:191684.7-191684.20"
+ process $proc$libresoc.v:191684$12868
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:191917.3-192238.6"
- process $proc$libresoc.v:191917$13072
+ attribute \src "libresoc.v:191813.3-192134.6"
+ process $proc$libresoc.v:191813$12864
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:191918.5-191918.29"
+ attribute \src "libresoc.v:191814.5-191814.29"
switch \initial
- attribute \src "libresoc.v:191918.9-191918.17"
+ attribute \src "libresoc.v:191814.9-191814.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:192239.3-192560.6"
- process $proc$libresoc.v:192239$13073
+ attribute \src "libresoc.v:192135.3-192456.6"
+ process $proc$libresoc.v:192135$12865
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:192240.5-192240.29"
+ attribute \src "libresoc.v:192136.5-192136.29"
switch \initial
- attribute \src "libresoc.v:192240.9-192240.17"
+ attribute \src "libresoc.v:192136.9-192136.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:192561.3-192906.6"
- process $proc$libresoc.v:192561$13074
+ attribute \src "libresoc.v:192457.3-192802.6"
+ process $proc$libresoc.v:192457$12866
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:192562.5-192562.29"
+ attribute \src "libresoc.v:192458.5-192458.29"
switch \initial
- attribute \src "libresoc.v:192562.9-192562.17"
+ attribute \src "libresoc.v:192458.9-192458.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:192907.3-193252.6"
- process $proc$libresoc.v:192907$13075
+ attribute \src "libresoc.v:192803.3-193148.6"
+ process $proc$libresoc.v:192803$12867
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:192908.5-192908.29"
+ attribute \src "libresoc.v:192804.5-192804.29"
switch \initial
- attribute \src "libresoc.v:192908.9-192908.17"
+ attribute \src "libresoc.v:192804.9-192804.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86"
switch \spr_i
attribute \src "libresoc.v:0.0-0.0"
case 10'0000000001
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:193257.1-193315.10"
+attribute \src "libresoc.v:193153.1-193211.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l"
attribute \generator "nMigen"
module \src_l
- attribute \src "libresoc.v:193258.7-193258.20"
+ attribute \src "libresoc.v:193154.7-193154.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193303.3-193311.6"
- wire width 4 $0\q_int$next[3:0]$13087
- attribute \src "libresoc.v:193301.3-193302.27"
+ attribute \src "libresoc.v:193199.3-193207.6"
+ wire width 4 $0\q_int$next[3:0]$12879
+ attribute \src "libresoc.v:193197.3-193198.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:193303.3-193311.6"
- wire width 4 $1\q_int$next[3:0]$13088
- attribute \src "libresoc.v:193280.13-193280.25"
+ attribute \src "libresoc.v:193199.3-193207.6"
+ wire width 4 $1\q_int$next[3:0]$12880
+ attribute \src "libresoc.v:193176.13-193176.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:193293.17-193293.96"
- wire width 4 $and$libresoc.v:193293$13077_Y
- attribute \src "libresoc.v:193298.17-193298.96"
- wire width 4 $and$libresoc.v:193298$13082_Y
- attribute \src "libresoc.v:193295.18-193295.93"
- wire width 4 $not$libresoc.v:193295$13079_Y
- attribute \src "libresoc.v:193297.17-193297.92"
- wire width 4 $not$libresoc.v:193297$13081_Y
- attribute \src "libresoc.v:193300.17-193300.92"
- wire width 4 $not$libresoc.v:193300$13084_Y
- attribute \src "libresoc.v:193294.18-193294.98"
- wire width 4 $or$libresoc.v:193294$13078_Y
- attribute \src "libresoc.v:193296.18-193296.99"
- wire width 4 $or$libresoc.v:193296$13080_Y
- attribute \src "libresoc.v:193299.17-193299.97"
- wire width 4 $or$libresoc.v:193299$13083_Y
+ attribute \src "libresoc.v:193189.17-193189.96"
+ wire width 4 $and$libresoc.v:193189$12869_Y
+ attribute \src "libresoc.v:193194.17-193194.96"
+ wire width 4 $and$libresoc.v:193194$12874_Y
+ attribute \src "libresoc.v:193191.18-193191.93"
+ wire width 4 $not$libresoc.v:193191$12871_Y
+ attribute \src "libresoc.v:193193.17-193193.92"
+ wire width 4 $not$libresoc.v:193193$12873_Y
+ attribute \src "libresoc.v:193196.17-193196.92"
+ wire width 4 $not$libresoc.v:193196$12876_Y
+ attribute \src "libresoc.v:193190.18-193190.98"
+ wire width 4 $or$libresoc.v:193190$12870_Y
+ attribute \src "libresoc.v:193192.18-193192.99"
+ wire width 4 $or$libresoc.v:193192$12872_Y
+ attribute \src "libresoc.v:193195.17-193195.97"
+ wire width 4 $or$libresoc.v:193195$12875_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193258.7-193258.15"
+ attribute \src "libresoc.v:193154.7-193154.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193293$13077
+ cell $and $and$libresoc.v:193189$12869
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193293$13077_Y
+ connect \Y $and$libresoc.v:193189$12869_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193298$13082
+ cell $and $and$libresoc.v:193194$12874
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193298$13082_Y
+ connect \Y $and$libresoc.v:193194$12874_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193295$13079
+ cell $not $not$libresoc.v:193191$12871
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:193295$13079_Y
+ connect \Y $not$libresoc.v:193191$12871_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193297$13081
+ cell $not $not$libresoc.v:193193$12873
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:193297$13081_Y
+ connect \Y $not$libresoc.v:193193$12873_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193300$13084
+ cell $not $not$libresoc.v:193196$12876
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:193300$13084_Y
+ connect \Y $not$libresoc.v:193196$12876_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193294$13078
+ cell $or $or$libresoc.v:193190$12870
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193294$13078_Y
+ connect \Y $or$libresoc.v:193190$12870_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193296$13080
+ cell $or $or$libresoc.v:193192$12872
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193296$13080_Y
+ connect \Y $or$libresoc.v:193192$12872_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193299$13083
+ cell $or $or$libresoc.v:193195$12875
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193299$13083_Y
+ connect \Y $or$libresoc.v:193195$12875_Y
end
- attribute \src "libresoc.v:193258.7-193258.20"
- process $proc$libresoc.v:193258$13089
+ attribute \src "libresoc.v:193154.7-193154.20"
+ process $proc$libresoc.v:193154$12881
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193280.13-193280.25"
- process $proc$libresoc.v:193280$13090
+ attribute \src "libresoc.v:193176.13-193176.25"
+ process $proc$libresoc.v:193176$12882
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:193301.3-193302.27"
- process $proc$libresoc.v:193301$13085
+ attribute \src "libresoc.v:193197.3-193198.27"
+ process $proc$libresoc.v:193197$12877
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:193303.3-193311.6"
- process $proc$libresoc.v:193303$13086
+ attribute \src "libresoc.v:193199.3-193207.6"
+ process $proc$libresoc.v:193199$12878
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13087 $1\q_int$next[3:0]$13088
- attribute \src "libresoc.v:193304.5-193304.29"
+ assign $0\q_int$next[3:0]$12879 $1\q_int$next[3:0]$12880
+ attribute \src "libresoc.v:193200.5-193200.29"
switch \initial
- attribute \src "libresoc.v:193304.9-193304.17"
+ attribute \src "libresoc.v:193200.9-193200.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13088 4'0000
+ assign $1\q_int$next[3:0]$12880 4'0000
case
- assign $1\q_int$next[3:0]$13088 \$5
+ assign $1\q_int$next[3:0]$12880 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13087
+ update \q_int$next $0\q_int$next[3:0]$12879
end
- connect \$9 $and$libresoc.v:193293$13077_Y
- connect \$11 $or$libresoc.v:193294$13078_Y
- connect \$13 $not$libresoc.v:193295$13079_Y
- connect \$15 $or$libresoc.v:193296$13080_Y
- connect \$1 $not$libresoc.v:193297$13081_Y
- connect \$3 $and$libresoc.v:193298$13082_Y
- connect \$5 $or$libresoc.v:193299$13083_Y
- connect \$7 $not$libresoc.v:193300$13084_Y
+ connect \$9 $and$libresoc.v:193189$12869_Y
+ connect \$11 $or$libresoc.v:193190$12870_Y
+ connect \$13 $not$libresoc.v:193191$12871_Y
+ connect \$15 $or$libresoc.v:193192$12872_Y
+ connect \$1 $not$libresoc.v:193193$12873_Y
+ connect \$3 $and$libresoc.v:193194$12874_Y
+ connect \$5 $or$libresoc.v:193195$12875_Y
+ connect \$7 $not$libresoc.v:193196$12876_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193319.1-193377.10"
+attribute \src "libresoc.v:193215.1-193273.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l"
attribute \generator "nMigen"
module \src_l$10
- attribute \src "libresoc.v:193320.7-193320.20"
+ attribute \src "libresoc.v:193216.7-193216.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193365.3-193373.6"
- wire width 6 $0\q_int$next[5:0]$13101
- attribute \src "libresoc.v:193363.3-193364.27"
+ attribute \src "libresoc.v:193261.3-193269.6"
+ wire width 6 $0\q_int$next[5:0]$12893
+ attribute \src "libresoc.v:193259.3-193260.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:193365.3-193373.6"
- wire width 6 $1\q_int$next[5:0]$13102
- attribute \src "libresoc.v:193342.13-193342.26"
+ attribute \src "libresoc.v:193261.3-193269.6"
+ wire width 6 $1\q_int$next[5:0]$12894
+ attribute \src "libresoc.v:193238.13-193238.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:193355.17-193355.96"
- wire width 6 $and$libresoc.v:193355$13091_Y
- attribute \src "libresoc.v:193360.17-193360.96"
- wire width 6 $and$libresoc.v:193360$13096_Y
- attribute \src "libresoc.v:193357.18-193357.93"
- wire width 6 $not$libresoc.v:193357$13093_Y
- attribute \src "libresoc.v:193359.17-193359.92"
- wire width 6 $not$libresoc.v:193359$13095_Y
- attribute \src "libresoc.v:193362.17-193362.92"
- wire width 6 $not$libresoc.v:193362$13098_Y
- attribute \src "libresoc.v:193356.18-193356.98"
- wire width 6 $or$libresoc.v:193356$13092_Y
- attribute \src "libresoc.v:193358.18-193358.99"
- wire width 6 $or$libresoc.v:193358$13094_Y
- attribute \src "libresoc.v:193361.17-193361.97"
- wire width 6 $or$libresoc.v:193361$13097_Y
+ attribute \src "libresoc.v:193251.17-193251.96"
+ wire width 6 $and$libresoc.v:193251$12883_Y
+ attribute \src "libresoc.v:193256.17-193256.96"
+ wire width 6 $and$libresoc.v:193256$12888_Y
+ attribute \src "libresoc.v:193253.18-193253.93"
+ wire width 6 $not$libresoc.v:193253$12885_Y
+ attribute \src "libresoc.v:193255.17-193255.92"
+ wire width 6 $not$libresoc.v:193255$12887_Y
+ attribute \src "libresoc.v:193258.17-193258.92"
+ wire width 6 $not$libresoc.v:193258$12890_Y
+ attribute \src "libresoc.v:193252.18-193252.98"
+ wire width 6 $or$libresoc.v:193252$12884_Y
+ attribute \src "libresoc.v:193254.18-193254.99"
+ wire width 6 $or$libresoc.v:193254$12886_Y
+ attribute \src "libresoc.v:193257.17-193257.97"
+ wire width 6 $or$libresoc.v:193257$12889_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193320.7-193320.15"
+ attribute \src "libresoc.v:193216.7-193216.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193355$13091
+ cell $and $and$libresoc.v:193251$12883
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193355$13091_Y
+ connect \Y $and$libresoc.v:193251$12883_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193360$13096
+ cell $and $and$libresoc.v:193256$12888
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193360$13096_Y
+ connect \Y $and$libresoc.v:193256$12888_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193357$13093
+ cell $not $not$libresoc.v:193253$12885
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:193357$13093_Y
+ connect \Y $not$libresoc.v:193253$12885_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193359$13095
+ cell $not $not$libresoc.v:193255$12887
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:193359$13095_Y
+ connect \Y $not$libresoc.v:193255$12887_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193362$13098
+ cell $not $not$libresoc.v:193258$12890
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:193362$13098_Y
+ connect \Y $not$libresoc.v:193258$12890_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193356$13092
+ cell $or $or$libresoc.v:193252$12884
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193356$13092_Y
+ connect \Y $or$libresoc.v:193252$12884_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193358$13094
+ cell $or $or$libresoc.v:193254$12886
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193358$13094_Y
+ connect \Y $or$libresoc.v:193254$12886_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193361$13097
+ cell $or $or$libresoc.v:193257$12889
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193361$13097_Y
+ connect \Y $or$libresoc.v:193257$12889_Y
end
- attribute \src "libresoc.v:193320.7-193320.20"
- process $proc$libresoc.v:193320$13103
+ attribute \src "libresoc.v:193216.7-193216.20"
+ process $proc$libresoc.v:193216$12895
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193342.13-193342.26"
- process $proc$libresoc.v:193342$13104
+ attribute \src "libresoc.v:193238.13-193238.26"
+ process $proc$libresoc.v:193238$12896
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:193363.3-193364.27"
- process $proc$libresoc.v:193363$13099
+ attribute \src "libresoc.v:193259.3-193260.27"
+ process $proc$libresoc.v:193259$12891
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:193365.3-193373.6"
- process $proc$libresoc.v:193365$13100
+ attribute \src "libresoc.v:193261.3-193269.6"
+ process $proc$libresoc.v:193261$12892
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13101 $1\q_int$next[5:0]$13102
- attribute \src "libresoc.v:193366.5-193366.29"
+ assign $0\q_int$next[5:0]$12893 $1\q_int$next[5:0]$12894
+ attribute \src "libresoc.v:193262.5-193262.29"
switch \initial
- attribute \src "libresoc.v:193366.9-193366.17"
+ attribute \src "libresoc.v:193262.9-193262.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13102 6'000000
+ assign $1\q_int$next[5:0]$12894 6'000000
case
- assign $1\q_int$next[5:0]$13102 \$5
+ assign $1\q_int$next[5:0]$12894 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13101
+ update \q_int$next $0\q_int$next[5:0]$12893
end
- connect \$9 $and$libresoc.v:193355$13091_Y
- connect \$11 $or$libresoc.v:193356$13092_Y
- connect \$13 $not$libresoc.v:193357$13093_Y
- connect \$15 $or$libresoc.v:193358$13094_Y
- connect \$1 $not$libresoc.v:193359$13095_Y
- connect \$3 $and$libresoc.v:193360$13096_Y
- connect \$5 $or$libresoc.v:193361$13097_Y
- connect \$7 $not$libresoc.v:193362$13098_Y
+ connect \$9 $and$libresoc.v:193251$12883_Y
+ connect \$11 $or$libresoc.v:193252$12884_Y
+ connect \$13 $not$libresoc.v:193253$12885_Y
+ connect \$15 $or$libresoc.v:193254$12886_Y
+ connect \$1 $not$libresoc.v:193255$12887_Y
+ connect \$3 $and$libresoc.v:193256$12888_Y
+ connect \$5 $or$libresoc.v:193257$12889_Y
+ connect \$7 $not$libresoc.v:193258$12890_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193381.1-193439.10"
+attribute \src "libresoc.v:193277.1-193335.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l"
attribute \generator "nMigen"
module \src_l$101
- attribute \src "libresoc.v:193382.7-193382.20"
+ attribute \src "libresoc.v:193278.7-193278.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193427.3-193435.6"
- wire width 3 $0\q_int$next[2:0]$13115
- attribute \src "libresoc.v:193425.3-193426.27"
+ attribute \src "libresoc.v:193323.3-193331.6"
+ wire width 3 $0\q_int$next[2:0]$12907
+ attribute \src "libresoc.v:193321.3-193322.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:193427.3-193435.6"
- wire width 3 $1\q_int$next[2:0]$13116
- attribute \src "libresoc.v:193404.13-193404.25"
+ attribute \src "libresoc.v:193323.3-193331.6"
+ wire width 3 $1\q_int$next[2:0]$12908
+ attribute \src "libresoc.v:193300.13-193300.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:193417.17-193417.96"
- wire width 3 $and$libresoc.v:193417$13105_Y
- attribute \src "libresoc.v:193422.17-193422.96"
- wire width 3 $and$libresoc.v:193422$13110_Y
- attribute \src "libresoc.v:193419.18-193419.93"
- wire width 3 $not$libresoc.v:193419$13107_Y
- attribute \src "libresoc.v:193421.17-193421.92"
- wire width 3 $not$libresoc.v:193421$13109_Y
- attribute \src "libresoc.v:193424.17-193424.92"
- wire width 3 $not$libresoc.v:193424$13112_Y
- attribute \src "libresoc.v:193418.18-193418.98"
- wire width 3 $or$libresoc.v:193418$13106_Y
- attribute \src "libresoc.v:193420.18-193420.99"
- wire width 3 $or$libresoc.v:193420$13108_Y
- attribute \src "libresoc.v:193423.17-193423.97"
- wire width 3 $or$libresoc.v:193423$13111_Y
+ attribute \src "libresoc.v:193313.17-193313.96"
+ wire width 3 $and$libresoc.v:193313$12897_Y
+ attribute \src "libresoc.v:193318.17-193318.96"
+ wire width 3 $and$libresoc.v:193318$12902_Y
+ attribute \src "libresoc.v:193315.18-193315.93"
+ wire width 3 $not$libresoc.v:193315$12899_Y
+ attribute \src "libresoc.v:193317.17-193317.92"
+ wire width 3 $not$libresoc.v:193317$12901_Y
+ attribute \src "libresoc.v:193320.17-193320.92"
+ wire width 3 $not$libresoc.v:193320$12904_Y
+ attribute \src "libresoc.v:193314.18-193314.98"
+ wire width 3 $or$libresoc.v:193314$12898_Y
+ attribute \src "libresoc.v:193316.18-193316.99"
+ wire width 3 $or$libresoc.v:193316$12900_Y
+ attribute \src "libresoc.v:193319.17-193319.97"
+ wire width 3 $or$libresoc.v:193319$12903_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193382.7-193382.15"
+ attribute \src "libresoc.v:193278.7-193278.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193417$13105
+ cell $and $and$libresoc.v:193313$12897
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193417$13105_Y
+ connect \Y $and$libresoc.v:193313$12897_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193422$13110
+ cell $and $and$libresoc.v:193318$12902
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193422$13110_Y
+ connect \Y $and$libresoc.v:193318$12902_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193419$13107
+ cell $not $not$libresoc.v:193315$12899
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:193419$13107_Y
+ connect \Y $not$libresoc.v:193315$12899_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193421$13109
+ cell $not $not$libresoc.v:193317$12901
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193421$13109_Y
+ connect \Y $not$libresoc.v:193317$12901_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193424$13112
+ cell $not $not$libresoc.v:193320$12904
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193424$13112_Y
+ connect \Y $not$libresoc.v:193320$12904_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193418$13106
+ cell $or $or$libresoc.v:193314$12898
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193418$13106_Y
+ connect \Y $or$libresoc.v:193314$12898_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193420$13108
+ cell $or $or$libresoc.v:193316$12900
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193420$13108_Y
+ connect \Y $or$libresoc.v:193316$12900_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193423$13111
+ cell $or $or$libresoc.v:193319$12903
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193423$13111_Y
+ connect \Y $or$libresoc.v:193319$12903_Y
end
- attribute \src "libresoc.v:193382.7-193382.20"
- process $proc$libresoc.v:193382$13117
+ attribute \src "libresoc.v:193278.7-193278.20"
+ process $proc$libresoc.v:193278$12909
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193404.13-193404.25"
- process $proc$libresoc.v:193404$13118
+ attribute \src "libresoc.v:193300.13-193300.25"
+ process $proc$libresoc.v:193300$12910
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:193425.3-193426.27"
- process $proc$libresoc.v:193425$13113
+ attribute \src "libresoc.v:193321.3-193322.27"
+ process $proc$libresoc.v:193321$12905
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:193427.3-193435.6"
- process $proc$libresoc.v:193427$13114
+ attribute \src "libresoc.v:193323.3-193331.6"
+ process $proc$libresoc.v:193323$12906
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13115 $1\q_int$next[2:0]$13116
- attribute \src "libresoc.v:193428.5-193428.29"
+ assign $0\q_int$next[2:0]$12907 $1\q_int$next[2:0]$12908
+ attribute \src "libresoc.v:193324.5-193324.29"
switch \initial
- attribute \src "libresoc.v:193428.9-193428.17"
+ attribute \src "libresoc.v:193324.9-193324.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13116 3'000
+ assign $1\q_int$next[2:0]$12908 3'000
case
- assign $1\q_int$next[2:0]$13116 \$5
+ assign $1\q_int$next[2:0]$12908 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13115
+ update \q_int$next $0\q_int$next[2:0]$12907
end
- connect \$9 $and$libresoc.v:193417$13105_Y
- connect \$11 $or$libresoc.v:193418$13106_Y
- connect \$13 $not$libresoc.v:193419$13107_Y
- connect \$15 $or$libresoc.v:193420$13108_Y
- connect \$1 $not$libresoc.v:193421$13109_Y
- connect \$3 $and$libresoc.v:193422$13110_Y
- connect \$5 $or$libresoc.v:193423$13111_Y
- connect \$7 $not$libresoc.v:193424$13112_Y
+ connect \$9 $and$libresoc.v:193313$12897_Y
+ connect \$11 $or$libresoc.v:193314$12898_Y
+ connect \$13 $not$libresoc.v:193315$12899_Y
+ connect \$15 $or$libresoc.v:193316$12900_Y
+ connect \$1 $not$libresoc.v:193317$12901_Y
+ connect \$3 $and$libresoc.v:193318$12902_Y
+ connect \$5 $or$libresoc.v:193319$12903_Y
+ connect \$7 $not$libresoc.v:193320$12904_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193443.1-193501.10"
+attribute \src "libresoc.v:193339.1-193397.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l"
attribute \generator "nMigen"
module \src_l$119
- attribute \src "libresoc.v:193444.7-193444.20"
+ attribute \src "libresoc.v:193340.7-193340.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193489.3-193497.6"
- wire width 5 $0\q_int$next[4:0]$13129
- attribute \src "libresoc.v:193487.3-193488.27"
+ attribute \src "libresoc.v:193385.3-193393.6"
+ wire width 5 $0\q_int$next[4:0]$12921
+ attribute \src "libresoc.v:193383.3-193384.27"
wire width 5 $0\q_int[4:0]
- attribute \src "libresoc.v:193489.3-193497.6"
- wire width 5 $1\q_int$next[4:0]$13130
- attribute \src "libresoc.v:193466.13-193466.26"
+ attribute \src "libresoc.v:193385.3-193393.6"
+ wire width 5 $1\q_int$next[4:0]$12922
+ attribute \src "libresoc.v:193362.13-193362.26"
wire width 5 $1\q_int[4:0]
- attribute \src "libresoc.v:193479.17-193479.96"
- wire width 5 $and$libresoc.v:193479$13119_Y
- attribute \src "libresoc.v:193484.17-193484.96"
- wire width 5 $and$libresoc.v:193484$13124_Y
- attribute \src "libresoc.v:193481.18-193481.93"
- wire width 5 $not$libresoc.v:193481$13121_Y
- attribute \src "libresoc.v:193483.17-193483.92"
- wire width 5 $not$libresoc.v:193483$13123_Y
- attribute \src "libresoc.v:193486.17-193486.92"
- wire width 5 $not$libresoc.v:193486$13126_Y
- attribute \src "libresoc.v:193480.18-193480.98"
- wire width 5 $or$libresoc.v:193480$13120_Y
- attribute \src "libresoc.v:193482.18-193482.99"
- wire width 5 $or$libresoc.v:193482$13122_Y
- attribute \src "libresoc.v:193485.17-193485.97"
- wire width 5 $or$libresoc.v:193485$13125_Y
+ attribute \src "libresoc.v:193375.17-193375.96"
+ wire width 5 $and$libresoc.v:193375$12911_Y
+ attribute \src "libresoc.v:193380.17-193380.96"
+ wire width 5 $and$libresoc.v:193380$12916_Y
+ attribute \src "libresoc.v:193377.18-193377.93"
+ wire width 5 $not$libresoc.v:193377$12913_Y
+ attribute \src "libresoc.v:193379.17-193379.92"
+ wire width 5 $not$libresoc.v:193379$12915_Y
+ attribute \src "libresoc.v:193382.17-193382.92"
+ wire width 5 $not$libresoc.v:193382$12918_Y
+ attribute \src "libresoc.v:193376.18-193376.98"
+ wire width 5 $or$libresoc.v:193376$12912_Y
+ attribute \src "libresoc.v:193378.18-193378.99"
+ wire width 5 $or$libresoc.v:193378$12914_Y
+ attribute \src "libresoc.v:193381.17-193381.97"
+ wire width 5 $or$libresoc.v:193381$12917_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 5 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193444.7-193444.15"
+ attribute \src "libresoc.v:193340.7-193340.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193479$13119
+ cell $and $and$libresoc.v:193375$12911
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193479$13119_Y
+ connect \Y $and$libresoc.v:193375$12911_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193484$13124
+ cell $and $and$libresoc.v:193380$12916
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193484$13124_Y
+ connect \Y $and$libresoc.v:193380$12916_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193481$13121
+ cell $not $not$libresoc.v:193377$12913
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \q_src
- connect \Y $not$libresoc.v:193481$13121_Y
+ connect \Y $not$libresoc.v:193377$12913_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193483$13123
+ cell $not $not$libresoc.v:193379$12915
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:193483$13123_Y
+ connect \Y $not$libresoc.v:193379$12915_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193486$13126
+ cell $not $not$libresoc.v:193382$12918
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \r_src
- connect \Y $not$libresoc.v:193486$13126_Y
+ connect \Y $not$libresoc.v:193382$12918_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193480$13120
+ cell $or $or$libresoc.v:193376$12912
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193480$13120_Y
+ connect \Y $or$libresoc.v:193376$12912_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193482$13122
+ cell $or $or$libresoc.v:193378$12914
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193482$13122_Y
+ connect \Y $or$libresoc.v:193378$12914_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193485$13125
+ cell $or $or$libresoc.v:193381$12917
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193485$13125_Y
+ connect \Y $or$libresoc.v:193381$12917_Y
end
- attribute \src "libresoc.v:193444.7-193444.20"
- process $proc$libresoc.v:193444$13131
+ attribute \src "libresoc.v:193340.7-193340.20"
+ process $proc$libresoc.v:193340$12923
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193466.13-193466.26"
- process $proc$libresoc.v:193466$13132
+ attribute \src "libresoc.v:193362.13-193362.26"
+ process $proc$libresoc.v:193362$12924
assign { } { }
assign $1\q_int[4:0] 5'00000
sync always
sync init
update \q_int $1\q_int[4:0]
end
- attribute \src "libresoc.v:193487.3-193488.27"
- process $proc$libresoc.v:193487$13127
+ attribute \src "libresoc.v:193383.3-193384.27"
+ process $proc$libresoc.v:193383$12919
assign { } { }
assign $0\q_int[4:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[4:0]
end
- attribute \src "libresoc.v:193489.3-193497.6"
- process $proc$libresoc.v:193489$13128
+ attribute \src "libresoc.v:193385.3-193393.6"
+ process $proc$libresoc.v:193385$12920
assign { } { }
assign { } { }
- assign $0\q_int$next[4:0]$13129 $1\q_int$next[4:0]$13130
- attribute \src "libresoc.v:193490.5-193490.29"
+ assign $0\q_int$next[4:0]$12921 $1\q_int$next[4:0]$12922
+ attribute \src "libresoc.v:193386.5-193386.29"
switch \initial
- attribute \src "libresoc.v:193490.9-193490.17"
+ attribute \src "libresoc.v:193386.9-193386.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[4:0]$13130 5'00000
+ assign $1\q_int$next[4:0]$12922 5'00000
case
- assign $1\q_int$next[4:0]$13130 \$5
+ assign $1\q_int$next[4:0]$12922 \$5
end
sync always
- update \q_int$next $0\q_int$next[4:0]$13129
+ update \q_int$next $0\q_int$next[4:0]$12921
end
- connect \$9 $and$libresoc.v:193479$13119_Y
- connect \$11 $or$libresoc.v:193480$13120_Y
- connect \$13 $not$libresoc.v:193481$13121_Y
- connect \$15 $or$libresoc.v:193482$13122_Y
- connect \$1 $not$libresoc.v:193483$13123_Y
- connect \$3 $and$libresoc.v:193484$13124_Y
- connect \$5 $or$libresoc.v:193485$13125_Y
- connect \$7 $not$libresoc.v:193486$13126_Y
+ connect \$9 $and$libresoc.v:193375$12911_Y
+ connect \$11 $or$libresoc.v:193376$12912_Y
+ connect \$13 $not$libresoc.v:193377$12913_Y
+ connect \$15 $or$libresoc.v:193378$12914_Y
+ connect \$1 $not$libresoc.v:193379$12915_Y
+ connect \$3 $and$libresoc.v:193380$12916_Y
+ connect \$5 $or$libresoc.v:193381$12917_Y
+ connect \$7 $not$libresoc.v:193382$12918_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193505.1-193563.10"
+attribute \src "libresoc.v:193401.1-193459.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l"
attribute \generator "nMigen"
module \src_l$127
- attribute \src "libresoc.v:193506.7-193506.20"
+ attribute \src "libresoc.v:193402.7-193402.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193551.3-193559.6"
- wire width 3 $0\q_int$next[2:0]$13143
- attribute \src "libresoc.v:193549.3-193550.27"
+ attribute \src "libresoc.v:193447.3-193455.6"
+ wire width 3 $0\q_int$next[2:0]$12935
+ attribute \src "libresoc.v:193445.3-193446.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:193551.3-193559.6"
- wire width 3 $1\q_int$next[2:0]$13144
- attribute \src "libresoc.v:193528.13-193528.25"
+ attribute \src "libresoc.v:193447.3-193455.6"
+ wire width 3 $1\q_int$next[2:0]$12936
+ attribute \src "libresoc.v:193424.13-193424.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:193541.17-193541.96"
- wire width 3 $and$libresoc.v:193541$13133_Y
- attribute \src "libresoc.v:193546.17-193546.96"
- wire width 3 $and$libresoc.v:193546$13138_Y
- attribute \src "libresoc.v:193543.18-193543.93"
- wire width 3 $not$libresoc.v:193543$13135_Y
- attribute \src "libresoc.v:193545.17-193545.92"
- wire width 3 $not$libresoc.v:193545$13137_Y
- attribute \src "libresoc.v:193548.17-193548.92"
- wire width 3 $not$libresoc.v:193548$13140_Y
- attribute \src "libresoc.v:193542.18-193542.98"
- wire width 3 $or$libresoc.v:193542$13134_Y
- attribute \src "libresoc.v:193544.18-193544.99"
- wire width 3 $or$libresoc.v:193544$13136_Y
- attribute \src "libresoc.v:193547.17-193547.97"
- wire width 3 $or$libresoc.v:193547$13139_Y
+ attribute \src "libresoc.v:193437.17-193437.96"
+ wire width 3 $and$libresoc.v:193437$12925_Y
+ attribute \src "libresoc.v:193442.17-193442.96"
+ wire width 3 $and$libresoc.v:193442$12930_Y
+ attribute \src "libresoc.v:193439.18-193439.93"
+ wire width 3 $not$libresoc.v:193439$12927_Y
+ attribute \src "libresoc.v:193441.17-193441.92"
+ wire width 3 $not$libresoc.v:193441$12929_Y
+ attribute \src "libresoc.v:193444.17-193444.92"
+ wire width 3 $not$libresoc.v:193444$12932_Y
+ attribute \src "libresoc.v:193438.18-193438.98"
+ wire width 3 $or$libresoc.v:193438$12926_Y
+ attribute \src "libresoc.v:193440.18-193440.99"
+ wire width 3 $or$libresoc.v:193440$12928_Y
+ attribute \src "libresoc.v:193443.17-193443.97"
+ wire width 3 $or$libresoc.v:193443$12931_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193506.7-193506.15"
+ attribute \src "libresoc.v:193402.7-193402.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193541$13133
+ cell $and $and$libresoc.v:193437$12925
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193541$13133_Y
+ connect \Y $and$libresoc.v:193437$12925_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193546$13138
+ cell $and $and$libresoc.v:193442$12930
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193546$13138_Y
+ connect \Y $and$libresoc.v:193442$12930_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193543$13135
+ cell $not $not$libresoc.v:193439$12927
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:193543$13135_Y
+ connect \Y $not$libresoc.v:193439$12927_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193545$13137
+ cell $not $not$libresoc.v:193441$12929
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193545$13137_Y
+ connect \Y $not$libresoc.v:193441$12929_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193548$13140
+ cell $not $not$libresoc.v:193444$12932
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193548$13140_Y
+ connect \Y $not$libresoc.v:193444$12932_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193542$13134
+ cell $or $or$libresoc.v:193438$12926
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193542$13134_Y
+ connect \Y $or$libresoc.v:193438$12926_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193544$13136
+ cell $or $or$libresoc.v:193440$12928
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193544$13136_Y
+ connect \Y $or$libresoc.v:193440$12928_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193547$13139
+ cell $or $or$libresoc.v:193443$12931
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193547$13139_Y
+ connect \Y $or$libresoc.v:193443$12931_Y
end
- attribute \src "libresoc.v:193506.7-193506.20"
- process $proc$libresoc.v:193506$13145
+ attribute \src "libresoc.v:193402.7-193402.20"
+ process $proc$libresoc.v:193402$12937
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193528.13-193528.25"
- process $proc$libresoc.v:193528$13146
+ attribute \src "libresoc.v:193424.13-193424.25"
+ process $proc$libresoc.v:193424$12938
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:193549.3-193550.27"
- process $proc$libresoc.v:193549$13141
+ attribute \src "libresoc.v:193445.3-193446.27"
+ process $proc$libresoc.v:193445$12933
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:193551.3-193559.6"
- process $proc$libresoc.v:193551$13142
+ attribute \src "libresoc.v:193447.3-193455.6"
+ process $proc$libresoc.v:193447$12934
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13143 $1\q_int$next[2:0]$13144
- attribute \src "libresoc.v:193552.5-193552.29"
+ assign $0\q_int$next[2:0]$12935 $1\q_int$next[2:0]$12936
+ attribute \src "libresoc.v:193448.5-193448.29"
switch \initial
- attribute \src "libresoc.v:193552.9-193552.17"
+ attribute \src "libresoc.v:193448.9-193448.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13144 3'000
+ assign $1\q_int$next[2:0]$12936 3'000
case
- assign $1\q_int$next[2:0]$13144 \$5
+ assign $1\q_int$next[2:0]$12936 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13143
+ update \q_int$next $0\q_int$next[2:0]$12935
end
- connect \$9 $and$libresoc.v:193541$13133_Y
- connect \$11 $or$libresoc.v:193542$13134_Y
- connect \$13 $not$libresoc.v:193543$13135_Y
- connect \$15 $or$libresoc.v:193544$13136_Y
- connect \$1 $not$libresoc.v:193545$13137_Y
- connect \$3 $and$libresoc.v:193546$13138_Y
- connect \$5 $or$libresoc.v:193547$13139_Y
- connect \$7 $not$libresoc.v:193548$13140_Y
+ connect \$9 $and$libresoc.v:193437$12925_Y
+ connect \$11 $or$libresoc.v:193438$12926_Y
+ connect \$13 $not$libresoc.v:193439$12927_Y
+ connect \$15 $or$libresoc.v:193440$12928_Y
+ connect \$1 $not$libresoc.v:193441$12929_Y
+ connect \$3 $and$libresoc.v:193442$12930_Y
+ connect \$5 $or$libresoc.v:193443$12931_Y
+ connect \$7 $not$libresoc.v:193444$12932_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193567.1-193625.10"
+attribute \src "libresoc.v:193463.1-193521.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l"
attribute \generator "nMigen"
module \src_l$23
- attribute \src "libresoc.v:193568.7-193568.20"
+ attribute \src "libresoc.v:193464.7-193464.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193613.3-193621.6"
- wire width 3 $0\q_int$next[2:0]$13157
- attribute \src "libresoc.v:193611.3-193612.27"
+ attribute \src "libresoc.v:193509.3-193517.6"
+ wire width 3 $0\q_int$next[2:0]$12949
+ attribute \src "libresoc.v:193507.3-193508.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:193613.3-193621.6"
- wire width 3 $1\q_int$next[2:0]$13158
- attribute \src "libresoc.v:193590.13-193590.25"
+ attribute \src "libresoc.v:193509.3-193517.6"
+ wire width 3 $1\q_int$next[2:0]$12950
+ attribute \src "libresoc.v:193486.13-193486.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:193603.17-193603.96"
- wire width 3 $and$libresoc.v:193603$13147_Y
- attribute \src "libresoc.v:193608.17-193608.96"
- wire width 3 $and$libresoc.v:193608$13152_Y
- attribute \src "libresoc.v:193605.18-193605.93"
- wire width 3 $not$libresoc.v:193605$13149_Y
- attribute \src "libresoc.v:193607.17-193607.92"
- wire width 3 $not$libresoc.v:193607$13151_Y
- attribute \src "libresoc.v:193610.17-193610.92"
- wire width 3 $not$libresoc.v:193610$13154_Y
- attribute \src "libresoc.v:193604.18-193604.98"
- wire width 3 $or$libresoc.v:193604$13148_Y
- attribute \src "libresoc.v:193606.18-193606.99"
- wire width 3 $or$libresoc.v:193606$13150_Y
- attribute \src "libresoc.v:193609.17-193609.97"
- wire width 3 $or$libresoc.v:193609$13153_Y
+ attribute \src "libresoc.v:193499.17-193499.96"
+ wire width 3 $and$libresoc.v:193499$12939_Y
+ attribute \src "libresoc.v:193504.17-193504.96"
+ wire width 3 $and$libresoc.v:193504$12944_Y
+ attribute \src "libresoc.v:193501.18-193501.93"
+ wire width 3 $not$libresoc.v:193501$12941_Y
+ attribute \src "libresoc.v:193503.17-193503.92"
+ wire width 3 $not$libresoc.v:193503$12943_Y
+ attribute \src "libresoc.v:193506.17-193506.92"
+ wire width 3 $not$libresoc.v:193506$12946_Y
+ attribute \src "libresoc.v:193500.18-193500.98"
+ wire width 3 $or$libresoc.v:193500$12940_Y
+ attribute \src "libresoc.v:193502.18-193502.99"
+ wire width 3 $or$libresoc.v:193502$12942_Y
+ attribute \src "libresoc.v:193505.17-193505.97"
+ wire width 3 $or$libresoc.v:193505$12945_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193568.7-193568.15"
+ attribute \src "libresoc.v:193464.7-193464.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193603$13147
+ cell $and $and$libresoc.v:193499$12939
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193603$13147_Y
+ connect \Y $and$libresoc.v:193499$12939_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193608$13152
+ cell $and $and$libresoc.v:193504$12944
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193608$13152_Y
+ connect \Y $and$libresoc.v:193504$12944_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193605$13149
+ cell $not $not$libresoc.v:193501$12941
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:193605$13149_Y
+ connect \Y $not$libresoc.v:193501$12941_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193607$13151
+ cell $not $not$libresoc.v:193503$12943
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193607$13151_Y
+ connect \Y $not$libresoc.v:193503$12943_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193610$13154
+ cell $not $not$libresoc.v:193506$12946
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193610$13154_Y
+ connect \Y $not$libresoc.v:193506$12946_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193604$13148
+ cell $or $or$libresoc.v:193500$12940
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193604$13148_Y
+ connect \Y $or$libresoc.v:193500$12940_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193606$13150
+ cell $or $or$libresoc.v:193502$12942
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193606$13150_Y
+ connect \Y $or$libresoc.v:193502$12942_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193609$13153
+ cell $or $or$libresoc.v:193505$12945
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193609$13153_Y
+ connect \Y $or$libresoc.v:193505$12945_Y
end
- attribute \src "libresoc.v:193568.7-193568.20"
- process $proc$libresoc.v:193568$13159
+ attribute \src "libresoc.v:193464.7-193464.20"
+ process $proc$libresoc.v:193464$12951
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193590.13-193590.25"
- process $proc$libresoc.v:193590$13160
+ attribute \src "libresoc.v:193486.13-193486.25"
+ process $proc$libresoc.v:193486$12952
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:193611.3-193612.27"
- process $proc$libresoc.v:193611$13155
+ attribute \src "libresoc.v:193507.3-193508.27"
+ process $proc$libresoc.v:193507$12947
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:193613.3-193621.6"
- process $proc$libresoc.v:193613$13156
+ attribute \src "libresoc.v:193509.3-193517.6"
+ process $proc$libresoc.v:193509$12948
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13157 $1\q_int$next[2:0]$13158
- attribute \src "libresoc.v:193614.5-193614.29"
+ assign $0\q_int$next[2:0]$12949 $1\q_int$next[2:0]$12950
+ attribute \src "libresoc.v:193510.5-193510.29"
switch \initial
- attribute \src "libresoc.v:193614.9-193614.17"
+ attribute \src "libresoc.v:193510.9-193510.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13158 3'000
+ assign $1\q_int$next[2:0]$12950 3'000
case
- assign $1\q_int$next[2:0]$13158 \$5
+ assign $1\q_int$next[2:0]$12950 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13157
+ update \q_int$next $0\q_int$next[2:0]$12949
end
- connect \$9 $and$libresoc.v:193603$13147_Y
- connect \$11 $or$libresoc.v:193604$13148_Y
- connect \$13 $not$libresoc.v:193605$13149_Y
- connect \$15 $or$libresoc.v:193606$13150_Y
- connect \$1 $not$libresoc.v:193607$13151_Y
- connect \$3 $and$libresoc.v:193608$13152_Y
- connect \$5 $or$libresoc.v:193609$13153_Y
- connect \$7 $not$libresoc.v:193610$13154_Y
+ connect \$9 $and$libresoc.v:193499$12939_Y
+ connect \$11 $or$libresoc.v:193500$12940_Y
+ connect \$13 $not$libresoc.v:193501$12941_Y
+ connect \$15 $or$libresoc.v:193502$12942_Y
+ connect \$1 $not$libresoc.v:193503$12943_Y
+ connect \$3 $and$libresoc.v:193504$12944_Y
+ connect \$5 $or$libresoc.v:193505$12945_Y
+ connect \$7 $not$libresoc.v:193506$12946_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193629.1-193687.10"
+attribute \src "libresoc.v:193525.1-193583.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l"
attribute \generator "nMigen"
module \src_l$39
- attribute \src "libresoc.v:193630.7-193630.20"
+ attribute \src "libresoc.v:193526.7-193526.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193675.3-193683.6"
- wire width 4 $0\q_int$next[3:0]$13171
- attribute \src "libresoc.v:193673.3-193674.27"
+ attribute \src "libresoc.v:193571.3-193579.6"
+ wire width 4 $0\q_int$next[3:0]$12963
+ attribute \src "libresoc.v:193569.3-193570.27"
wire width 4 $0\q_int[3:0]
- attribute \src "libresoc.v:193675.3-193683.6"
- wire width 4 $1\q_int$next[3:0]$13172
- attribute \src "libresoc.v:193652.13-193652.25"
+ attribute \src "libresoc.v:193571.3-193579.6"
+ wire width 4 $1\q_int$next[3:0]$12964
+ attribute \src "libresoc.v:193548.13-193548.25"
wire width 4 $1\q_int[3:0]
- attribute \src "libresoc.v:193665.17-193665.96"
- wire width 4 $and$libresoc.v:193665$13161_Y
- attribute \src "libresoc.v:193670.17-193670.96"
- wire width 4 $and$libresoc.v:193670$13166_Y
- attribute \src "libresoc.v:193667.18-193667.93"
- wire width 4 $not$libresoc.v:193667$13163_Y
- attribute \src "libresoc.v:193669.17-193669.92"
- wire width 4 $not$libresoc.v:193669$13165_Y
- attribute \src "libresoc.v:193672.17-193672.92"
- wire width 4 $not$libresoc.v:193672$13168_Y
- attribute \src "libresoc.v:193666.18-193666.98"
- wire width 4 $or$libresoc.v:193666$13162_Y
- attribute \src "libresoc.v:193668.18-193668.99"
- wire width 4 $or$libresoc.v:193668$13164_Y
- attribute \src "libresoc.v:193671.17-193671.97"
- wire width 4 $or$libresoc.v:193671$13167_Y
+ attribute \src "libresoc.v:193561.17-193561.96"
+ wire width 4 $and$libresoc.v:193561$12953_Y
+ attribute \src "libresoc.v:193566.17-193566.96"
+ wire width 4 $and$libresoc.v:193566$12958_Y
+ attribute \src "libresoc.v:193563.18-193563.93"
+ wire width 4 $not$libresoc.v:193563$12955_Y
+ attribute \src "libresoc.v:193565.17-193565.92"
+ wire width 4 $not$libresoc.v:193565$12957_Y
+ attribute \src "libresoc.v:193568.17-193568.92"
+ wire width 4 $not$libresoc.v:193568$12960_Y
+ attribute \src "libresoc.v:193562.18-193562.98"
+ wire width 4 $or$libresoc.v:193562$12954_Y
+ attribute \src "libresoc.v:193564.18-193564.99"
+ wire width 4 $or$libresoc.v:193564$12956_Y
+ attribute \src "libresoc.v:193567.17-193567.97"
+ wire width 4 $or$libresoc.v:193567$12959_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 4 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193630.7-193630.15"
+ attribute \src "libresoc.v:193526.7-193526.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193665$13161
+ cell $and $and$libresoc.v:193561$12953
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193665$13161_Y
+ connect \Y $and$libresoc.v:193561$12953_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193670$13166
+ cell $and $and$libresoc.v:193566$12958
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193670$13166_Y
+ connect \Y $and$libresoc.v:193566$12958_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193667$13163
+ cell $not $not$libresoc.v:193563$12955
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \q_src
- connect \Y $not$libresoc.v:193667$13163_Y
+ connect \Y $not$libresoc.v:193563$12955_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193669$13165
+ cell $not $not$libresoc.v:193565$12957
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:193669$13165_Y
+ connect \Y $not$libresoc.v:193565$12957_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193672$13168
+ cell $not $not$libresoc.v:193568$12960
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \r_src
- connect \Y $not$libresoc.v:193672$13168_Y
+ connect \Y $not$libresoc.v:193568$12960_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193666$13162
+ cell $or $or$libresoc.v:193562$12954
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193666$13162_Y
+ connect \Y $or$libresoc.v:193562$12954_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193668$13164
+ cell $or $or$libresoc.v:193564$12956
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193668$13164_Y
+ connect \Y $or$libresoc.v:193564$12956_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193671$13167
+ cell $or $or$libresoc.v:193567$12959
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193671$13167_Y
+ connect \Y $or$libresoc.v:193567$12959_Y
end
- attribute \src "libresoc.v:193630.7-193630.20"
- process $proc$libresoc.v:193630$13173
+ attribute \src "libresoc.v:193526.7-193526.20"
+ process $proc$libresoc.v:193526$12965
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193652.13-193652.25"
- process $proc$libresoc.v:193652$13174
+ attribute \src "libresoc.v:193548.13-193548.25"
+ process $proc$libresoc.v:193548$12966
assign { } { }
assign $1\q_int[3:0] 4'0000
sync always
sync init
update \q_int $1\q_int[3:0]
end
- attribute \src "libresoc.v:193673.3-193674.27"
- process $proc$libresoc.v:193673$13169
+ attribute \src "libresoc.v:193569.3-193570.27"
+ process $proc$libresoc.v:193569$12961
assign { } { }
assign $0\q_int[3:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[3:0]
end
- attribute \src "libresoc.v:193675.3-193683.6"
- process $proc$libresoc.v:193675$13170
+ attribute \src "libresoc.v:193571.3-193579.6"
+ process $proc$libresoc.v:193571$12962
assign { } { }
assign { } { }
- assign $0\q_int$next[3:0]$13171 $1\q_int$next[3:0]$13172
- attribute \src "libresoc.v:193676.5-193676.29"
+ assign $0\q_int$next[3:0]$12963 $1\q_int$next[3:0]$12964
+ attribute \src "libresoc.v:193572.5-193572.29"
switch \initial
- attribute \src "libresoc.v:193676.9-193676.17"
+ attribute \src "libresoc.v:193572.9-193572.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[3:0]$13172 4'0000
+ assign $1\q_int$next[3:0]$12964 4'0000
case
- assign $1\q_int$next[3:0]$13172 \$5
+ assign $1\q_int$next[3:0]$12964 \$5
end
sync always
- update \q_int$next $0\q_int$next[3:0]$13171
+ update \q_int$next $0\q_int$next[3:0]$12963
end
- connect \$9 $and$libresoc.v:193665$13161_Y
- connect \$11 $or$libresoc.v:193666$13162_Y
- connect \$13 $not$libresoc.v:193667$13163_Y
- connect \$15 $or$libresoc.v:193668$13164_Y
- connect \$1 $not$libresoc.v:193669$13165_Y
- connect \$3 $and$libresoc.v:193670$13166_Y
- connect \$5 $or$libresoc.v:193671$13167_Y
- connect \$7 $not$libresoc.v:193672$13168_Y
+ connect \$9 $and$libresoc.v:193561$12953_Y
+ connect \$11 $or$libresoc.v:193562$12954_Y
+ connect \$13 $not$libresoc.v:193563$12955_Y
+ connect \$15 $or$libresoc.v:193564$12956_Y
+ connect \$1 $not$libresoc.v:193565$12957_Y
+ connect \$3 $and$libresoc.v:193566$12958_Y
+ connect \$5 $or$libresoc.v:193567$12959_Y
+ connect \$7 $not$libresoc.v:193568$12960_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193691.1-193749.10"
+attribute \src "libresoc.v:193587.1-193645.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l"
attribute \generator "nMigen"
module \src_l$55
- attribute \src "libresoc.v:193692.7-193692.20"
+ attribute \src "libresoc.v:193588.7-193588.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193737.3-193745.6"
- wire width 3 $0\q_int$next[2:0]$13185
- attribute \src "libresoc.v:193735.3-193736.27"
+ attribute \src "libresoc.v:193633.3-193641.6"
+ wire width 3 $0\q_int$next[2:0]$12977
+ attribute \src "libresoc.v:193631.3-193632.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:193737.3-193745.6"
- wire width 3 $1\q_int$next[2:0]$13186
- attribute \src "libresoc.v:193714.13-193714.25"
+ attribute \src "libresoc.v:193633.3-193641.6"
+ wire width 3 $1\q_int$next[2:0]$12978
+ attribute \src "libresoc.v:193610.13-193610.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:193727.17-193727.96"
- wire width 3 $and$libresoc.v:193727$13175_Y
- attribute \src "libresoc.v:193732.17-193732.96"
- wire width 3 $and$libresoc.v:193732$13180_Y
- attribute \src "libresoc.v:193729.18-193729.93"
- wire width 3 $not$libresoc.v:193729$13177_Y
- attribute \src "libresoc.v:193731.17-193731.92"
- wire width 3 $not$libresoc.v:193731$13179_Y
- attribute \src "libresoc.v:193734.17-193734.92"
- wire width 3 $not$libresoc.v:193734$13182_Y
- attribute \src "libresoc.v:193728.18-193728.98"
- wire width 3 $or$libresoc.v:193728$13176_Y
- attribute \src "libresoc.v:193730.18-193730.99"
- wire width 3 $or$libresoc.v:193730$13178_Y
- attribute \src "libresoc.v:193733.17-193733.97"
- wire width 3 $or$libresoc.v:193733$13181_Y
+ attribute \src "libresoc.v:193623.17-193623.96"
+ wire width 3 $and$libresoc.v:193623$12967_Y
+ attribute \src "libresoc.v:193628.17-193628.96"
+ wire width 3 $and$libresoc.v:193628$12972_Y
+ attribute \src "libresoc.v:193625.18-193625.93"
+ wire width 3 $not$libresoc.v:193625$12969_Y
+ attribute \src "libresoc.v:193627.17-193627.92"
+ wire width 3 $not$libresoc.v:193627$12971_Y
+ attribute \src "libresoc.v:193630.17-193630.92"
+ wire width 3 $not$libresoc.v:193630$12974_Y
+ attribute \src "libresoc.v:193624.18-193624.98"
+ wire width 3 $or$libresoc.v:193624$12968_Y
+ attribute \src "libresoc.v:193626.18-193626.99"
+ wire width 3 $or$libresoc.v:193626$12970_Y
+ attribute \src "libresoc.v:193629.17-193629.97"
+ wire width 3 $or$libresoc.v:193629$12973_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193692.7-193692.15"
+ attribute \src "libresoc.v:193588.7-193588.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193727$13175
+ cell $and $and$libresoc.v:193623$12967
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193727$13175_Y
+ connect \Y $and$libresoc.v:193623$12967_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193732$13180
+ cell $and $and$libresoc.v:193628$12972
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193732$13180_Y
+ connect \Y $and$libresoc.v:193628$12972_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193729$13177
+ cell $not $not$libresoc.v:193625$12969
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:193729$13177_Y
+ connect \Y $not$libresoc.v:193625$12969_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193731$13179
+ cell $not $not$libresoc.v:193627$12971
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193731$13179_Y
+ connect \Y $not$libresoc.v:193627$12971_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193734$13182
+ cell $not $not$libresoc.v:193630$12974
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193734$13182_Y
+ connect \Y $not$libresoc.v:193630$12974_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193728$13176
+ cell $or $or$libresoc.v:193624$12968
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193728$13176_Y
+ connect \Y $or$libresoc.v:193624$12968_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193730$13178
+ cell $or $or$libresoc.v:193626$12970
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193730$13178_Y
+ connect \Y $or$libresoc.v:193626$12970_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193733$13181
+ cell $or $or$libresoc.v:193629$12973
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193733$13181_Y
+ connect \Y $or$libresoc.v:193629$12973_Y
end
- attribute \src "libresoc.v:193692.7-193692.20"
- process $proc$libresoc.v:193692$13187
+ attribute \src "libresoc.v:193588.7-193588.20"
+ process $proc$libresoc.v:193588$12979
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193714.13-193714.25"
- process $proc$libresoc.v:193714$13188
+ attribute \src "libresoc.v:193610.13-193610.25"
+ process $proc$libresoc.v:193610$12980
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:193735.3-193736.27"
- process $proc$libresoc.v:193735$13183
+ attribute \src "libresoc.v:193631.3-193632.27"
+ process $proc$libresoc.v:193631$12975
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:193737.3-193745.6"
- process $proc$libresoc.v:193737$13184
+ attribute \src "libresoc.v:193633.3-193641.6"
+ process $proc$libresoc.v:193633$12976
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13185 $1\q_int$next[2:0]$13186
- attribute \src "libresoc.v:193738.5-193738.29"
+ assign $0\q_int$next[2:0]$12977 $1\q_int$next[2:0]$12978
+ attribute \src "libresoc.v:193634.5-193634.29"
switch \initial
- attribute \src "libresoc.v:193738.9-193738.17"
+ attribute \src "libresoc.v:193634.9-193634.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13186 3'000
+ assign $1\q_int$next[2:0]$12978 3'000
case
- assign $1\q_int$next[2:0]$13186 \$5
+ assign $1\q_int$next[2:0]$12978 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13185
+ update \q_int$next $0\q_int$next[2:0]$12977
end
- connect \$9 $and$libresoc.v:193727$13175_Y
- connect \$11 $or$libresoc.v:193728$13176_Y
- connect \$13 $not$libresoc.v:193729$13177_Y
- connect \$15 $or$libresoc.v:193730$13178_Y
- connect \$1 $not$libresoc.v:193731$13179_Y
- connect \$3 $and$libresoc.v:193732$13180_Y
- connect \$5 $or$libresoc.v:193733$13181_Y
- connect \$7 $not$libresoc.v:193734$13182_Y
+ connect \$9 $and$libresoc.v:193623$12967_Y
+ connect \$11 $or$libresoc.v:193624$12968_Y
+ connect \$13 $not$libresoc.v:193625$12969_Y
+ connect \$15 $or$libresoc.v:193626$12970_Y
+ connect \$1 $not$libresoc.v:193627$12971_Y
+ connect \$3 $and$libresoc.v:193628$12972_Y
+ connect \$5 $or$libresoc.v:193629$12973_Y
+ connect \$7 $not$libresoc.v:193630$12974_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193753.1-193811.10"
+attribute \src "libresoc.v:193649.1-193707.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l"
attribute \generator "nMigen"
module \src_l$67
- attribute \src "libresoc.v:193754.7-193754.20"
+ attribute \src "libresoc.v:193650.7-193650.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193799.3-193807.6"
- wire width 6 $0\q_int$next[5:0]$13199
- attribute \src "libresoc.v:193797.3-193798.27"
+ attribute \src "libresoc.v:193695.3-193703.6"
+ wire width 6 $0\q_int$next[5:0]$12991
+ attribute \src "libresoc.v:193693.3-193694.27"
wire width 6 $0\q_int[5:0]
- attribute \src "libresoc.v:193799.3-193807.6"
- wire width 6 $1\q_int$next[5:0]$13200
- attribute \src "libresoc.v:193776.13-193776.26"
+ attribute \src "libresoc.v:193695.3-193703.6"
+ wire width 6 $1\q_int$next[5:0]$12992
+ attribute \src "libresoc.v:193672.13-193672.26"
wire width 6 $1\q_int[5:0]
- attribute \src "libresoc.v:193789.17-193789.96"
- wire width 6 $and$libresoc.v:193789$13189_Y
- attribute \src "libresoc.v:193794.17-193794.96"
- wire width 6 $and$libresoc.v:193794$13194_Y
- attribute \src "libresoc.v:193791.18-193791.93"
- wire width 6 $not$libresoc.v:193791$13191_Y
- attribute \src "libresoc.v:193793.17-193793.92"
- wire width 6 $not$libresoc.v:193793$13193_Y
- attribute \src "libresoc.v:193796.17-193796.92"
- wire width 6 $not$libresoc.v:193796$13196_Y
- attribute \src "libresoc.v:193790.18-193790.98"
- wire width 6 $or$libresoc.v:193790$13190_Y
- attribute \src "libresoc.v:193792.18-193792.99"
- wire width 6 $or$libresoc.v:193792$13192_Y
- attribute \src "libresoc.v:193795.17-193795.97"
- wire width 6 $or$libresoc.v:193795$13195_Y
+ attribute \src "libresoc.v:193685.17-193685.96"
+ wire width 6 $and$libresoc.v:193685$12981_Y
+ attribute \src "libresoc.v:193690.17-193690.96"
+ wire width 6 $and$libresoc.v:193690$12986_Y
+ attribute \src "libresoc.v:193687.18-193687.93"
+ wire width 6 $not$libresoc.v:193687$12983_Y
+ attribute \src "libresoc.v:193689.17-193689.92"
+ wire width 6 $not$libresoc.v:193689$12985_Y
+ attribute \src "libresoc.v:193692.17-193692.92"
+ wire width 6 $not$libresoc.v:193692$12988_Y
+ attribute \src "libresoc.v:193686.18-193686.98"
+ wire width 6 $or$libresoc.v:193686$12982_Y
+ attribute \src "libresoc.v:193688.18-193688.99"
+ wire width 6 $or$libresoc.v:193688$12984_Y
+ attribute \src "libresoc.v:193691.17-193691.97"
+ wire width 6 $or$libresoc.v:193691$12987_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 6 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193754.7-193754.15"
+ attribute \src "libresoc.v:193650.7-193650.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193789$13189
+ cell $and $and$libresoc.v:193685$12981
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193789$13189_Y
+ connect \Y $and$libresoc.v:193685$12981_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193794$13194
+ cell $and $and$libresoc.v:193690$12986
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193794$13194_Y
+ connect \Y $and$libresoc.v:193690$12986_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193791$13191
+ cell $not $not$libresoc.v:193687$12983
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \q_src
- connect \Y $not$libresoc.v:193791$13191_Y
+ connect \Y $not$libresoc.v:193687$12983_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193793$13193
+ cell $not $not$libresoc.v:193689$12985
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:193793$13193_Y
+ connect \Y $not$libresoc.v:193689$12985_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193796$13196
+ cell $not $not$libresoc.v:193692$12988
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \r_src
- connect \Y $not$libresoc.v:193796$13196_Y
+ connect \Y $not$libresoc.v:193692$12988_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193790$13190
+ cell $or $or$libresoc.v:193686$12982
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193790$13190_Y
+ connect \Y $or$libresoc.v:193686$12982_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193792$13192
+ cell $or $or$libresoc.v:193688$12984
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193792$13192_Y
+ connect \Y $or$libresoc.v:193688$12984_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193795$13195
+ cell $or $or$libresoc.v:193691$12987
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193795$13195_Y
+ connect \Y $or$libresoc.v:193691$12987_Y
end
- attribute \src "libresoc.v:193754.7-193754.20"
- process $proc$libresoc.v:193754$13201
+ attribute \src "libresoc.v:193650.7-193650.20"
+ process $proc$libresoc.v:193650$12993
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193776.13-193776.26"
- process $proc$libresoc.v:193776$13202
+ attribute \src "libresoc.v:193672.13-193672.26"
+ process $proc$libresoc.v:193672$12994
assign { } { }
assign $1\q_int[5:0] 6'000000
sync always
sync init
update \q_int $1\q_int[5:0]
end
- attribute \src "libresoc.v:193797.3-193798.27"
- process $proc$libresoc.v:193797$13197
+ attribute \src "libresoc.v:193693.3-193694.27"
+ process $proc$libresoc.v:193693$12989
assign { } { }
assign $0\q_int[5:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[5:0]
end
- attribute \src "libresoc.v:193799.3-193807.6"
- process $proc$libresoc.v:193799$13198
+ attribute \src "libresoc.v:193695.3-193703.6"
+ process $proc$libresoc.v:193695$12990
assign { } { }
assign { } { }
- assign $0\q_int$next[5:0]$13199 $1\q_int$next[5:0]$13200
- attribute \src "libresoc.v:193800.5-193800.29"
+ assign $0\q_int$next[5:0]$12991 $1\q_int$next[5:0]$12992
+ attribute \src "libresoc.v:193696.5-193696.29"
switch \initial
- attribute \src "libresoc.v:193800.9-193800.17"
+ attribute \src "libresoc.v:193696.9-193696.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[5:0]$13200 6'000000
+ assign $1\q_int$next[5:0]$12992 6'000000
case
- assign $1\q_int$next[5:0]$13200 \$5
+ assign $1\q_int$next[5:0]$12992 \$5
end
sync always
- update \q_int$next $0\q_int$next[5:0]$13199
+ update \q_int$next $0\q_int$next[5:0]$12991
end
- connect \$9 $and$libresoc.v:193789$13189_Y
- connect \$11 $or$libresoc.v:193790$13190_Y
- connect \$13 $not$libresoc.v:193791$13191_Y
- connect \$15 $or$libresoc.v:193792$13192_Y
- connect \$1 $not$libresoc.v:193793$13193_Y
- connect \$3 $and$libresoc.v:193794$13194_Y
- connect \$5 $or$libresoc.v:193795$13195_Y
- connect \$7 $not$libresoc.v:193796$13196_Y
+ connect \$9 $and$libresoc.v:193685$12981_Y
+ connect \$11 $or$libresoc.v:193686$12982_Y
+ connect \$13 $not$libresoc.v:193687$12983_Y
+ connect \$15 $or$libresoc.v:193688$12984_Y
+ connect \$1 $not$libresoc.v:193689$12985_Y
+ connect \$3 $and$libresoc.v:193690$12986_Y
+ connect \$5 $or$libresoc.v:193691$12987_Y
+ connect \$7 $not$libresoc.v:193692$12988_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193815.1-193873.10"
+attribute \src "libresoc.v:193711.1-193769.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l"
attribute \generator "nMigen"
module \src_l$84
- attribute \src "libresoc.v:193816.7-193816.20"
+ attribute \src "libresoc.v:193712.7-193712.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193861.3-193869.6"
- wire width 3 $0\q_int$next[2:0]$13213
- attribute \src "libresoc.v:193859.3-193860.27"
+ attribute \src "libresoc.v:193757.3-193765.6"
+ wire width 3 $0\q_int$next[2:0]$13005
+ attribute \src "libresoc.v:193755.3-193756.27"
wire width 3 $0\q_int[2:0]
- attribute \src "libresoc.v:193861.3-193869.6"
- wire width 3 $1\q_int$next[2:0]$13214
- attribute \src "libresoc.v:193838.13-193838.25"
+ attribute \src "libresoc.v:193757.3-193765.6"
+ wire width 3 $1\q_int$next[2:0]$13006
+ attribute \src "libresoc.v:193734.13-193734.25"
wire width 3 $1\q_int[2:0]
- attribute \src "libresoc.v:193851.17-193851.96"
- wire width 3 $and$libresoc.v:193851$13203_Y
- attribute \src "libresoc.v:193856.17-193856.96"
- wire width 3 $and$libresoc.v:193856$13208_Y
- attribute \src "libresoc.v:193853.18-193853.93"
- wire width 3 $not$libresoc.v:193853$13205_Y
- attribute \src "libresoc.v:193855.17-193855.92"
- wire width 3 $not$libresoc.v:193855$13207_Y
- attribute \src "libresoc.v:193858.17-193858.92"
- wire width 3 $not$libresoc.v:193858$13210_Y
- attribute \src "libresoc.v:193852.18-193852.98"
- wire width 3 $or$libresoc.v:193852$13204_Y
- attribute \src "libresoc.v:193854.18-193854.99"
- wire width 3 $or$libresoc.v:193854$13206_Y
- attribute \src "libresoc.v:193857.17-193857.97"
- wire width 3 $or$libresoc.v:193857$13209_Y
+ attribute \src "libresoc.v:193747.17-193747.96"
+ wire width 3 $and$libresoc.v:193747$12995_Y
+ attribute \src "libresoc.v:193752.17-193752.96"
+ wire width 3 $and$libresoc.v:193752$13000_Y
+ attribute \src "libresoc.v:193749.18-193749.93"
+ wire width 3 $not$libresoc.v:193749$12997_Y
+ attribute \src "libresoc.v:193751.17-193751.92"
+ wire width 3 $not$libresoc.v:193751$12999_Y
+ attribute \src "libresoc.v:193754.17-193754.92"
+ wire width 3 $not$libresoc.v:193754$13002_Y
+ attribute \src "libresoc.v:193748.18-193748.98"
+ wire width 3 $or$libresoc.v:193748$12996_Y
+ attribute \src "libresoc.v:193750.18-193750.99"
+ wire width 3 $or$libresoc.v:193750$12998_Y
+ attribute \src "libresoc.v:193753.17-193753.97"
+ wire width 3 $or$libresoc.v:193753$13001_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire width 3 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193816.7-193816.15"
+ attribute \src "libresoc.v:193712.7-193712.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193851$13203
+ cell $and $and$libresoc.v:193747$12995
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193851$13203_Y
+ connect \Y $and$libresoc.v:193747$12995_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193856$13208
+ cell $and $and$libresoc.v:193752$13000
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193856$13208_Y
+ connect \Y $and$libresoc.v:193752$13000_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193853$13205
+ cell $not $not$libresoc.v:193749$12997
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \q_src
- connect \Y $not$libresoc.v:193853$13205_Y
+ connect \Y $not$libresoc.v:193749$12997_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193855$13207
+ cell $not $not$libresoc.v:193751$12999
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193855$13207_Y
+ connect \Y $not$libresoc.v:193751$12999_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193858$13210
+ cell $not $not$libresoc.v:193754$13002
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \r_src
- connect \Y $not$libresoc.v:193858$13210_Y
+ connect \Y $not$libresoc.v:193754$13002_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193852$13204
+ cell $or $or$libresoc.v:193748$12996
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$9
connect \B \s_src
- connect \Y $or$libresoc.v:193852$13204_Y
+ connect \Y $or$libresoc.v:193748$12996_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193854$13206
+ cell $or $or$libresoc.v:193750$12998
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
- connect \Y $or$libresoc.v:193854$13206_Y
+ connect \Y $or$libresoc.v:193750$12998_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193857$13209
+ cell $or $or$libresoc.v:193753$13001
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \$3
connect \B \s_src
- connect \Y $or$libresoc.v:193857$13209_Y
+ connect \Y $or$libresoc.v:193753$13001_Y
end
- attribute \src "libresoc.v:193816.7-193816.20"
- process $proc$libresoc.v:193816$13215
+ attribute \src "libresoc.v:193712.7-193712.20"
+ process $proc$libresoc.v:193712$13007
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193838.13-193838.25"
- process $proc$libresoc.v:193838$13216
+ attribute \src "libresoc.v:193734.13-193734.25"
+ process $proc$libresoc.v:193734$13008
assign { } { }
assign $1\q_int[2:0] 3'000
sync always
sync init
update \q_int $1\q_int[2:0]
end
- attribute \src "libresoc.v:193859.3-193860.27"
- process $proc$libresoc.v:193859$13211
+ attribute \src "libresoc.v:193755.3-193756.27"
+ process $proc$libresoc.v:193755$13003
assign { } { }
assign $0\q_int[2:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[2:0]
end
- attribute \src "libresoc.v:193861.3-193869.6"
- process $proc$libresoc.v:193861$13212
+ attribute \src "libresoc.v:193757.3-193765.6"
+ process $proc$libresoc.v:193757$13004
assign { } { }
assign { } { }
- assign $0\q_int$next[2:0]$13213 $1\q_int$next[2:0]$13214
- attribute \src "libresoc.v:193862.5-193862.29"
+ assign $0\q_int$next[2:0]$13005 $1\q_int$next[2:0]$13006
+ attribute \src "libresoc.v:193758.5-193758.29"
switch \initial
- attribute \src "libresoc.v:193862.9-193862.17"
+ attribute \src "libresoc.v:193758.9-193758.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[2:0]$13214 3'000
+ assign $1\q_int$next[2:0]$13006 3'000
case
- assign $1\q_int$next[2:0]$13214 \$5
+ assign $1\q_int$next[2:0]$13006 \$5
end
sync always
- update \q_int$next $0\q_int$next[2:0]$13213
+ update \q_int$next $0\q_int$next[2:0]$13005
end
- connect \$9 $and$libresoc.v:193851$13203_Y
- connect \$11 $or$libresoc.v:193852$13204_Y
- connect \$13 $not$libresoc.v:193853$13205_Y
- connect \$15 $or$libresoc.v:193854$13206_Y
- connect \$1 $not$libresoc.v:193855$13207_Y
- connect \$3 $and$libresoc.v:193856$13208_Y
- connect \$5 $or$libresoc.v:193857$13209_Y
- connect \$7 $not$libresoc.v:193858$13210_Y
+ connect \$9 $and$libresoc.v:193747$12995_Y
+ connect \$11 $or$libresoc.v:193748$12996_Y
+ connect \$13 $not$libresoc.v:193749$12997_Y
+ connect \$15 $or$libresoc.v:193750$12998_Y
+ connect \$1 $not$libresoc.v:193751$12999_Y
+ connect \$3 $and$libresoc.v:193752$13000_Y
+ connect \$5 $or$libresoc.v:193753$13001_Y
+ connect \$7 $not$libresoc.v:193754$13002_Y
connect \qlq_src \$15
connect \qn_src \$13
connect \q_src \$11
end
-attribute \src "libresoc.v:193877.1-193935.10"
+attribute \src "libresoc.v:193773.1-193831.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active"
attribute \generator "nMigen"
module \st_active
- attribute \src "libresoc.v:193878.7-193878.20"
+ attribute \src "libresoc.v:193774.7-193774.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193923.3-193931.6"
- wire $0\q_int$next[0:0]$13227
- attribute \src "libresoc.v:193921.3-193922.27"
+ attribute \src "libresoc.v:193819.3-193827.6"
+ wire $0\q_int$next[0:0]$13019
+ attribute \src "libresoc.v:193817.3-193818.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:193923.3-193931.6"
- wire $1\q_int$next[0:0]$13228
- attribute \src "libresoc.v:193900.7-193900.19"
+ attribute \src "libresoc.v:193819.3-193827.6"
+ wire $1\q_int$next[0:0]$13020
+ attribute \src "libresoc.v:193796.7-193796.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:193913.17-193913.96"
- wire $and$libresoc.v:193913$13217_Y
- attribute \src "libresoc.v:193918.17-193918.96"
- wire $and$libresoc.v:193918$13222_Y
- attribute \src "libresoc.v:193915.18-193915.99"
- wire $not$libresoc.v:193915$13219_Y
- attribute \src "libresoc.v:193917.17-193917.98"
- wire $not$libresoc.v:193917$13221_Y
- attribute \src "libresoc.v:193920.17-193920.98"
- wire $not$libresoc.v:193920$13224_Y
- attribute \src "libresoc.v:193914.18-193914.104"
- wire $or$libresoc.v:193914$13218_Y
- attribute \src "libresoc.v:193916.18-193916.105"
- wire $or$libresoc.v:193916$13220_Y
- attribute \src "libresoc.v:193919.17-193919.103"
- wire $or$libresoc.v:193919$13223_Y
+ attribute \src "libresoc.v:193809.17-193809.96"
+ wire $and$libresoc.v:193809$13009_Y
+ attribute \src "libresoc.v:193814.17-193814.96"
+ wire $and$libresoc.v:193814$13014_Y
+ attribute \src "libresoc.v:193811.18-193811.99"
+ wire $not$libresoc.v:193811$13011_Y
+ attribute \src "libresoc.v:193813.17-193813.98"
+ wire $not$libresoc.v:193813$13013_Y
+ attribute \src "libresoc.v:193816.17-193816.98"
+ wire $not$libresoc.v:193816$13016_Y
+ attribute \src "libresoc.v:193810.18-193810.104"
+ wire $or$libresoc.v:193810$13010_Y
+ attribute \src "libresoc.v:193812.18-193812.105"
+ wire $or$libresoc.v:193812$13012_Y
+ attribute \src "libresoc.v:193815.17-193815.103"
+ wire $or$libresoc.v:193815$13015_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193878.7-193878.15"
+ attribute \src "libresoc.v:193774.7-193774.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 3 \s_st_active
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193913$13217
+ cell $and $and$libresoc.v:193809$13009
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193913$13217_Y
+ connect \Y $and$libresoc.v:193809$13009_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193918$13222
+ cell $and $and$libresoc.v:193814$13014
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193918$13222_Y
+ connect \Y $and$libresoc.v:193814$13014_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193915$13219
+ cell $not $not$libresoc.v:193811$13011
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_active
- connect \Y $not$libresoc.v:193915$13219_Y
+ connect \Y $not$libresoc.v:193811$13011_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193917$13221
+ cell $not $not$libresoc.v:193813$13013
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:193917$13221_Y
+ connect \Y $not$libresoc.v:193813$13013_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193920$13224
+ cell $not $not$libresoc.v:193816$13016
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_active
- connect \Y $not$libresoc.v:193920$13224_Y
+ connect \Y $not$libresoc.v:193816$13016_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193914$13218
+ cell $or $or$libresoc.v:193810$13010
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_active
- connect \Y $or$libresoc.v:193914$13218_Y
+ connect \Y $or$libresoc.v:193810$13010_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193916$13220
+ cell $or $or$libresoc.v:193812$13012
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_active
connect \B \q_int
- connect \Y $or$libresoc.v:193916$13220_Y
+ connect \Y $or$libresoc.v:193812$13012_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193919$13223
+ cell $or $or$libresoc.v:193815$13015
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_active
- connect \Y $or$libresoc.v:193919$13223_Y
+ connect \Y $or$libresoc.v:193815$13015_Y
end
- attribute \src "libresoc.v:193878.7-193878.20"
- process $proc$libresoc.v:193878$13229
+ attribute \src "libresoc.v:193774.7-193774.20"
+ process $proc$libresoc.v:193774$13021
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193900.7-193900.19"
- process $proc$libresoc.v:193900$13230
+ attribute \src "libresoc.v:193796.7-193796.19"
+ process $proc$libresoc.v:193796$13022
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:193921.3-193922.27"
- process $proc$libresoc.v:193921$13225
+ attribute \src "libresoc.v:193817.3-193818.27"
+ process $proc$libresoc.v:193817$13017
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:193923.3-193931.6"
- process $proc$libresoc.v:193923$13226
+ attribute \src "libresoc.v:193819.3-193827.6"
+ process $proc$libresoc.v:193819$13018
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13227 $1\q_int$next[0:0]$13228
- attribute \src "libresoc.v:193924.5-193924.29"
+ assign $0\q_int$next[0:0]$13019 $1\q_int$next[0:0]$13020
+ attribute \src "libresoc.v:193820.5-193820.29"
switch \initial
- attribute \src "libresoc.v:193924.9-193924.17"
+ attribute \src "libresoc.v:193820.9-193820.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13228 1'0
+ assign $1\q_int$next[0:0]$13020 1'0
case
- assign $1\q_int$next[0:0]$13228 \$5
+ assign $1\q_int$next[0:0]$13020 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13227
+ update \q_int$next $0\q_int$next[0:0]$13019
end
- connect \$9 $and$libresoc.v:193913$13217_Y
- connect \$11 $or$libresoc.v:193914$13218_Y
- connect \$13 $not$libresoc.v:193915$13219_Y
- connect \$15 $or$libresoc.v:193916$13220_Y
- connect \$1 $not$libresoc.v:193917$13221_Y
- connect \$3 $and$libresoc.v:193918$13222_Y
- connect \$5 $or$libresoc.v:193919$13223_Y
- connect \$7 $not$libresoc.v:193920$13224_Y
+ connect \$9 $and$libresoc.v:193809$13009_Y
+ connect \$11 $or$libresoc.v:193810$13010_Y
+ connect \$13 $not$libresoc.v:193811$13011_Y
+ connect \$15 $or$libresoc.v:193812$13012_Y
+ connect \$1 $not$libresoc.v:193813$13013_Y
+ connect \$3 $and$libresoc.v:193814$13014_Y
+ connect \$5 $or$libresoc.v:193815$13015_Y
+ connect \$7 $not$libresoc.v:193816$13016_Y
connect \qlq_st_active \$15
connect \qn_st_active \$13
connect \q_st_active \$11
end
-attribute \src "libresoc.v:193939.1-193997.10"
+attribute \src "libresoc.v:193835.1-193893.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done"
attribute \generator "nMigen"
module \st_done
- attribute \src "libresoc.v:193940.7-193940.20"
+ attribute \src "libresoc.v:193836.7-193836.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:193985.3-193993.6"
- wire $0\q_int$next[0:0]$13241
- attribute \src "libresoc.v:193983.3-193984.27"
+ attribute \src "libresoc.v:193881.3-193889.6"
+ wire $0\q_int$next[0:0]$13033
+ attribute \src "libresoc.v:193879.3-193880.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:193985.3-193993.6"
- wire $1\q_int$next[0:0]$13242
- attribute \src "libresoc.v:193962.7-193962.19"
+ attribute \src "libresoc.v:193881.3-193889.6"
+ wire $1\q_int$next[0:0]$13034
+ attribute \src "libresoc.v:193858.7-193858.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:193975.17-193975.96"
- wire $and$libresoc.v:193975$13231_Y
- attribute \src "libresoc.v:193980.17-193980.96"
- wire $and$libresoc.v:193980$13236_Y
- attribute \src "libresoc.v:193977.18-193977.97"
- wire $not$libresoc.v:193977$13233_Y
- attribute \src "libresoc.v:193979.17-193979.96"
- wire $not$libresoc.v:193979$13235_Y
- attribute \src "libresoc.v:193982.17-193982.96"
- wire $not$libresoc.v:193982$13238_Y
- attribute \src "libresoc.v:193976.18-193976.102"
- wire $or$libresoc.v:193976$13232_Y
- attribute \src "libresoc.v:193978.18-193978.103"
- wire $or$libresoc.v:193978$13234_Y
- attribute \src "libresoc.v:193981.17-193981.101"
- wire $or$libresoc.v:193981$13237_Y
+ attribute \src "libresoc.v:193871.17-193871.96"
+ wire $and$libresoc.v:193871$13023_Y
+ attribute \src "libresoc.v:193876.17-193876.96"
+ wire $and$libresoc.v:193876$13028_Y
+ attribute \src "libresoc.v:193873.18-193873.97"
+ wire $not$libresoc.v:193873$13025_Y
+ attribute \src "libresoc.v:193875.17-193875.96"
+ wire $not$libresoc.v:193875$13027_Y
+ attribute \src "libresoc.v:193878.17-193878.96"
+ wire $not$libresoc.v:193878$13030_Y
+ attribute \src "libresoc.v:193872.18-193872.102"
+ wire $or$libresoc.v:193872$13024_Y
+ attribute \src "libresoc.v:193874.18-193874.103"
+ wire $or$libresoc.v:193874$13026_Y
+ attribute \src "libresoc.v:193877.17-193877.101"
+ wire $or$libresoc.v:193877$13029_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:193940.7-193940.15"
+ attribute \src "libresoc.v:193836.7-193836.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_st_done
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:193975$13231
+ cell $and $and$libresoc.v:193871$13023
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:193975$13231_Y
+ connect \Y $and$libresoc.v:193871$13023_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:193980$13236
+ cell $and $and$libresoc.v:193876$13028
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:193980$13236_Y
+ connect \Y $and$libresoc.v:193876$13028_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:193977$13233
+ cell $not $not$libresoc.v:193873$13025
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_st_done
- connect \Y $not$libresoc.v:193977$13233_Y
+ connect \Y $not$libresoc.v:193873$13025_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:193979$13235
+ cell $not $not$libresoc.v:193875$13027
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:193979$13235_Y
+ connect \Y $not$libresoc.v:193875$13027_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:193982$13238
+ cell $not $not$libresoc.v:193878$13030
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_st_done
- connect \Y $not$libresoc.v:193982$13238_Y
+ connect \Y $not$libresoc.v:193878$13030_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:193976$13232
+ cell $or $or$libresoc.v:193872$13024
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_st_done
- connect \Y $or$libresoc.v:193976$13232_Y
+ connect \Y $or$libresoc.v:193872$13024_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:193978$13234
+ cell $or $or$libresoc.v:193874$13026
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_st_done
connect \B \q_int
- connect \Y $or$libresoc.v:193978$13234_Y
+ connect \Y $or$libresoc.v:193874$13026_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:193981$13237
+ cell $or $or$libresoc.v:193877$13029
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_st_done
- connect \Y $or$libresoc.v:193981$13237_Y
+ connect \Y $or$libresoc.v:193877$13029_Y
end
- attribute \src "libresoc.v:193940.7-193940.20"
- process $proc$libresoc.v:193940$13243
+ attribute \src "libresoc.v:193836.7-193836.20"
+ process $proc$libresoc.v:193836$13035
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:193962.7-193962.19"
- process $proc$libresoc.v:193962$13244
+ attribute \src "libresoc.v:193858.7-193858.19"
+ process $proc$libresoc.v:193858$13036
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:193983.3-193984.27"
- process $proc$libresoc.v:193983$13239
+ attribute \src "libresoc.v:193879.3-193880.27"
+ process $proc$libresoc.v:193879$13031
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:193985.3-193993.6"
- process $proc$libresoc.v:193985$13240
+ attribute \src "libresoc.v:193881.3-193889.6"
+ process $proc$libresoc.v:193881$13032
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13241 $1\q_int$next[0:0]$13242
- attribute \src "libresoc.v:193986.5-193986.29"
+ assign $0\q_int$next[0:0]$13033 $1\q_int$next[0:0]$13034
+ attribute \src "libresoc.v:193882.5-193882.29"
switch \initial
- attribute \src "libresoc.v:193986.9-193986.17"
+ attribute \src "libresoc.v:193882.9-193882.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13242 1'0
+ assign $1\q_int$next[0:0]$13034 1'0
case
- assign $1\q_int$next[0:0]$13242 \$5
+ assign $1\q_int$next[0:0]$13034 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13241
+ update \q_int$next $0\q_int$next[0:0]$13033
end
- connect \$9 $and$libresoc.v:193975$13231_Y
- connect \$11 $or$libresoc.v:193976$13232_Y
- connect \$13 $not$libresoc.v:193977$13233_Y
- connect \$15 $or$libresoc.v:193978$13234_Y
- connect \$1 $not$libresoc.v:193979$13235_Y
- connect \$3 $and$libresoc.v:193980$13236_Y
- connect \$5 $or$libresoc.v:193981$13237_Y
- connect \$7 $not$libresoc.v:193982$13238_Y
+ connect \$9 $and$libresoc.v:193871$13023_Y
+ connect \$11 $or$libresoc.v:193872$13024_Y
+ connect \$13 $not$libresoc.v:193873$13025_Y
+ connect \$15 $or$libresoc.v:193874$13026_Y
+ connect \$1 $not$libresoc.v:193875$13027_Y
+ connect \$3 $and$libresoc.v:193876$13028_Y
+ connect \$5 $or$libresoc.v:193877$13029_Y
+ connect \$7 $not$libresoc.v:193878$13030_Y
connect \qlq_st_done \$15
connect \qn_st_done \$13
connect \q_st_done \$11
end
-attribute \src "libresoc.v:194001.1-194297.10"
+attribute \src "libresoc.v:193897.1-194193.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.state"
attribute \generator "nMigen"
module \state
- attribute \src "libresoc.v:194249.3-194258.6"
+ attribute \src "libresoc.v:194145.3-194154.6"
wire width 64 $0\cia__data_o[63:0]
- attribute \src "libresoc.v:194002.7-194002.20"
+ attribute \src "libresoc.v:193898.7-193898.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194268.3-194277.6"
+ attribute \src "libresoc.v:194164.3-194173.6"
wire width 64 $0\msr__data_o[63:0]
- attribute \src "libresoc.v:194259.3-194267.6"
- wire width 3 $0\ren_delay$12$next[2:0]$13268
- attribute \src "libresoc.v:194163.3-194164.43"
- wire width 3 $0\ren_delay$12[2:0]$13257
- attribute \src "libresoc.v:194130.13-194130.34"
- wire width 3 $0\ren_delay$12[2:0]$13274
- attribute \src "libresoc.v:194221.3-194229.6"
- wire width 3 $0\ren_delay$19$next[2:0]$13260
- attribute \src "libresoc.v:194161.3-194162.43"
- wire width 3 $0\ren_delay$19[2:0]$13255
- attribute \src "libresoc.v:194134.13-194134.34"
- wire width 3 $0\ren_delay$19[2:0]$13276
- attribute \src "libresoc.v:194240.3-194248.6"
- wire width 3 $0\ren_delay$next[2:0]$13264
- attribute \src "libresoc.v:194165.3-194166.35"
+ attribute \src "libresoc.v:194155.3-194163.6"
+ wire width 3 $0\ren_delay$12$next[2:0]$13060
+ attribute \src "libresoc.v:194059.3-194060.43"
+ wire width 3 $0\ren_delay$12[2:0]$13049
+ attribute \src "libresoc.v:194026.13-194026.34"
+ wire width 3 $0\ren_delay$12[2:0]$13066
+ attribute \src "libresoc.v:194117.3-194125.6"
+ wire width 3 $0\ren_delay$19$next[2:0]$13052
+ attribute \src "libresoc.v:194057.3-194058.43"
+ wire width 3 $0\ren_delay$19[2:0]$13047
+ attribute \src "libresoc.v:194030.13-194030.34"
+ wire width 3 $0\ren_delay$19[2:0]$13068
+ attribute \src "libresoc.v:194136.3-194144.6"
+ wire width 3 $0\ren_delay$next[2:0]$13056
+ attribute \src "libresoc.v:194061.3-194062.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:194230.3-194239.6"
+ attribute \src "libresoc.v:194126.3-194135.6"
wire width 64 $0\sv__data_o[63:0]
- attribute \src "libresoc.v:194249.3-194258.6"
+ attribute \src "libresoc.v:194145.3-194154.6"
wire width 64 $1\cia__data_o[63:0]
- attribute \src "libresoc.v:194268.3-194277.6"
+ attribute \src "libresoc.v:194164.3-194173.6"
wire width 64 $1\msr__data_o[63:0]
- attribute \src "libresoc.v:194259.3-194267.6"
- wire width 3 $1\ren_delay$12$next[2:0]$13269
- attribute \src "libresoc.v:194221.3-194229.6"
- wire width 3 $1\ren_delay$19$next[2:0]$13261
- attribute \src "libresoc.v:194240.3-194248.6"
- wire width 3 $1\ren_delay$next[2:0]$13265
- attribute \src "libresoc.v:194128.13-194128.29"
+ attribute \src "libresoc.v:194155.3-194163.6"
+ wire width 3 $1\ren_delay$12$next[2:0]$13061
+ attribute \src "libresoc.v:194117.3-194125.6"
+ wire width 3 $1\ren_delay$19$next[2:0]$13053
+ attribute \src "libresoc.v:194136.3-194144.6"
+ wire width 3 $1\ren_delay$next[2:0]$13057
+ attribute \src "libresoc.v:194024.13-194024.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:194230.3-194239.6"
+ attribute \src "libresoc.v:194126.3-194135.6"
wire width 64 $1\sv__data_o[63:0]
- attribute \src "libresoc.v:194152.18-194152.109"
- wire width 64 $or$libresoc.v:194152$13245_Y
- attribute \src "libresoc.v:194154.18-194154.124"
- wire width 64 $or$libresoc.v:194154$13247_Y
- attribute \src "libresoc.v:194155.18-194155.110"
- wire width 64 $or$libresoc.v:194155$13248_Y
- attribute \src "libresoc.v:194157.18-194157.122"
- wire width 64 $or$libresoc.v:194157$13250_Y
- attribute \src "libresoc.v:194158.18-194158.109"
- wire width 64 $or$libresoc.v:194158$13251_Y
- attribute \src "libresoc.v:194160.17-194160.123"
- wire width 64 $or$libresoc.v:194160$13253_Y
- attribute \src "libresoc.v:194153.18-194153.100"
- wire $reduce_or$libresoc.v:194153$13246_Y
- attribute \src "libresoc.v:194156.18-194156.100"
- wire $reduce_or$libresoc.v:194156$13249_Y
- attribute \src "libresoc.v:194159.17-194159.95"
- wire $reduce_or$libresoc.v:194159$13252_Y
+ attribute \src "libresoc.v:194048.18-194048.109"
+ wire width 64 $or$libresoc.v:194048$13037_Y
+ attribute \src "libresoc.v:194050.18-194050.124"
+ wire width 64 $or$libresoc.v:194050$13039_Y
+ attribute \src "libresoc.v:194051.18-194051.110"
+ wire width 64 $or$libresoc.v:194051$13040_Y
+ attribute \src "libresoc.v:194053.18-194053.122"
+ wire width 64 $or$libresoc.v:194053$13042_Y
+ attribute \src "libresoc.v:194054.18-194054.109"
+ wire width 64 $or$libresoc.v:194054$13043_Y
+ attribute \src "libresoc.v:194056.17-194056.123"
+ wire width 64 $or$libresoc.v:194056$13045_Y
+ attribute \src "libresoc.v:194049.18-194049.100"
+ wire $reduce_or$libresoc.v:194049$13038_Y
+ attribute \src "libresoc.v:194052.18-194052.100"
+ wire $reduce_or$libresoc.v:194052$13041_Y
+ attribute \src "libresoc.v:194055.17-194055.95"
+ wire $reduce_or$libresoc.v:194055$13044_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 64 \$10
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 64 output 3 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 2 \cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 7 \data_i
wire width 64 input 13 \data_i$3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 input 14 \data_i$4
- attribute \src "libresoc.v:194002.7-194002.15"
+ attribute \src "libresoc.v:193898.7-193898.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 output 9 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:194152$13245
+ cell $or $or$libresoc.v:194048$13037
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_cia0__data_o
connect \B \$8
- connect \Y $or$libresoc.v:194152$13245_Y
+ connect \Y $or$libresoc.v:194048$13037_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:194154$13247
+ cell $or $or$libresoc.v:194050$13039
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_msr1__data_o
connect \B \reg_2_msr2__data_o
- connect \Y $or$libresoc.v:194154$13247_Y
+ connect \Y $or$libresoc.v:194050$13039_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:194155$13248
+ cell $or $or$libresoc.v:194051$13040
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_msr0__data_o
connect \B \$15
- connect \Y $or$libresoc.v:194155$13248_Y
+ connect \Y $or$libresoc.v:194051$13040_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:194157$13250
+ cell $or $or$libresoc.v:194053$13042
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_sv1__data_o
connect \B \reg_2_sv2__data_o
- connect \Y $or$libresoc.v:194157$13250_Y
+ connect \Y $or$libresoc.v:194053$13042_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:194158$13251
+ cell $or $or$libresoc.v:194054$13043
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_0_sv0__data_o
connect \B \$22
- connect \Y $or$libresoc.v:194158$13251_Y
+ connect \Y $or$libresoc.v:194054$13043_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:194160$13253
+ cell $or $or$libresoc.v:194056$13045
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \reg_1_cia1__data_o
connect \B \reg_2_cia2__data_o
- connect \Y $or$libresoc.v:194160$13253_Y
+ connect \Y $or$libresoc.v:194056$13045_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:194153$13246
+ cell $reduce_or $reduce_or$libresoc.v:194049$13038
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$12
- connect \Y $reduce_or$libresoc.v:194153$13246_Y
+ connect \Y $reduce_or$libresoc.v:194049$13038_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:194156$13249
+ cell $reduce_or $reduce_or$libresoc.v:194052$13041
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$19
- connect \Y $reduce_or$libresoc.v:194156$13249_Y
+ connect \Y $reduce_or$libresoc.v:194052$13041_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:194159$13252
+ cell $reduce_or $reduce_or$libresoc.v:194055$13044
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:194159$13252_Y
+ connect \Y $reduce_or$libresoc.v:194055$13044_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:194167.15-194184.4"
+ attribute \src "libresoc.v:194063.15-194080.4"
cell \reg_0$135 \reg_0
connect \cia0__data_o \reg_0_cia0__data_o
connect \cia0__ren \reg_0_cia0__ren
connect \sv0__wen \reg_0_sv0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:194185.15-194202.4"
+ attribute \src "libresoc.v:194081.15-194098.4"
cell \reg_1$136 \reg_1
connect \cia1__data_o \reg_1_cia1__data_o
connect \cia1__ren \reg_1_cia1__ren
connect \sv1__wen \reg_1_sv1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:194203.15-194220.4"
+ attribute \src "libresoc.v:194099.15-194116.4"
cell \reg_2$137 \reg_2
connect \cia2__data_o \reg_2_cia2__data_o
connect \cia2__ren \reg_2_cia2__ren
connect \sv2__ren \reg_2_sv2__ren
connect \sv2__wen \reg_2_sv2__wen
end
- attribute \src "libresoc.v:194002.7-194002.20"
- process $proc$libresoc.v:194002$13271
+ attribute \src "libresoc.v:193898.7-193898.20"
+ process $proc$libresoc.v:193898$13063
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194128.13-194128.29"
- process $proc$libresoc.v:194128$13272
+ attribute \src "libresoc.v:194024.13-194024.29"
+ process $proc$libresoc.v:194024$13064
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:194130.13-194130.34"
- process $proc$libresoc.v:194130$13273
+ attribute \src "libresoc.v:194026.13-194026.34"
+ process $proc$libresoc.v:194026$13065
assign { } { }
- assign $0\ren_delay$12[2:0]$13274 3'000
+ assign $0\ren_delay$12[2:0]$13066 3'000
sync always
sync init
- update \ren_delay$12 $0\ren_delay$12[2:0]$13274
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13066
end
- attribute \src "libresoc.v:194134.13-194134.34"
- process $proc$libresoc.v:194134$13275
+ attribute \src "libresoc.v:194030.13-194030.34"
+ process $proc$libresoc.v:194030$13067
assign { } { }
- assign $0\ren_delay$19[2:0]$13276 3'000
+ assign $0\ren_delay$19[2:0]$13068 3'000
sync always
sync init
- update \ren_delay$19 $0\ren_delay$19[2:0]$13276
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13068
end
- attribute \src "libresoc.v:194161.3-194162.43"
- process $proc$libresoc.v:194161$13254
+ attribute \src "libresoc.v:194057.3-194058.43"
+ process $proc$libresoc.v:194057$13046
assign { } { }
- assign $0\ren_delay$19[2:0]$13255 \ren_delay$19$next
+ assign $0\ren_delay$19[2:0]$13047 \ren_delay$19$next
sync posedge \coresync_clk
- update \ren_delay$19 $0\ren_delay$19[2:0]$13255
+ update \ren_delay$19 $0\ren_delay$19[2:0]$13047
end
- attribute \src "libresoc.v:194163.3-194164.43"
- process $proc$libresoc.v:194163$13256
+ attribute \src "libresoc.v:194059.3-194060.43"
+ process $proc$libresoc.v:194059$13048
assign { } { }
- assign $0\ren_delay$12[2:0]$13257 \ren_delay$12$next
+ assign $0\ren_delay$12[2:0]$13049 \ren_delay$12$next
sync posedge \coresync_clk
- update \ren_delay$12 $0\ren_delay$12[2:0]$13257
+ update \ren_delay$12 $0\ren_delay$12[2:0]$13049
end
- attribute \src "libresoc.v:194165.3-194166.35"
- process $proc$libresoc.v:194165$13258
+ attribute \src "libresoc.v:194061.3-194062.35"
+ process $proc$libresoc.v:194061$13050
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:194221.3-194229.6"
- process $proc$libresoc.v:194221$13259
+ attribute \src "libresoc.v:194117.3-194125.6"
+ process $proc$libresoc.v:194117$13051
assign { } { }
assign { } { }
- assign $0\ren_delay$19$next[2:0]$13260 $1\ren_delay$19$next[2:0]$13261
- attribute \src "libresoc.v:194222.5-194222.29"
+ assign $0\ren_delay$19$next[2:0]$13052 $1\ren_delay$19$next[2:0]$13053
+ attribute \src "libresoc.v:194118.5-194118.29"
switch \initial
- attribute \src "libresoc.v:194222.9-194222.17"
+ attribute \src "libresoc.v:194118.9-194118.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$19$next[2:0]$13261 3'000
+ assign $1\ren_delay$19$next[2:0]$13053 3'000
case
- assign $1\ren_delay$19$next[2:0]$13261 \sv__ren
+ assign $1\ren_delay$19$next[2:0]$13053 \sv__ren
end
sync always
- update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13260
+ update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13052
end
- attribute \src "libresoc.v:194230.3-194239.6"
- process $proc$libresoc.v:194230$13262
+ attribute \src "libresoc.v:194126.3-194135.6"
+ process $proc$libresoc.v:194126$13054
assign { } { }
assign { } { }
assign $0\sv__data_o[63:0] $1\sv__data_o[63:0]
- attribute \src "libresoc.v:194231.5-194231.29"
+ attribute \src "libresoc.v:194127.5-194127.29"
switch \initial
- attribute \src "libresoc.v:194231.9-194231.17"
+ attribute \src "libresoc.v:194127.9-194127.17"
case 1'1
case
end
sync always
update \sv__data_o $0\sv__data_o[63:0]
end
- attribute \src "libresoc.v:194240.3-194248.6"
- process $proc$libresoc.v:194240$13263
+ attribute \src "libresoc.v:194136.3-194144.6"
+ process $proc$libresoc.v:194136$13055
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$13264 $1\ren_delay$next[2:0]$13265
- attribute \src "libresoc.v:194241.5-194241.29"
+ assign $0\ren_delay$next[2:0]$13056 $1\ren_delay$next[2:0]$13057
+ attribute \src "libresoc.v:194137.5-194137.29"
switch \initial
- attribute \src "libresoc.v:194241.9-194241.17"
+ attribute \src "libresoc.v:194137.9-194137.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$13265 3'000
+ assign $1\ren_delay$next[2:0]$13057 3'000
case
- assign $1\ren_delay$next[2:0]$13265 \cia__ren
+ assign $1\ren_delay$next[2:0]$13057 \cia__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$13264
+ update \ren_delay$next $0\ren_delay$next[2:0]$13056
end
- attribute \src "libresoc.v:194249.3-194258.6"
- process $proc$libresoc.v:194249$13266
+ attribute \src "libresoc.v:194145.3-194154.6"
+ process $proc$libresoc.v:194145$13058
assign { } { }
assign { } { }
assign $0\cia__data_o[63:0] $1\cia__data_o[63:0]
- attribute \src "libresoc.v:194250.5-194250.29"
+ attribute \src "libresoc.v:194146.5-194146.29"
switch \initial
- attribute \src "libresoc.v:194250.9-194250.17"
+ attribute \src "libresoc.v:194146.9-194146.17"
case 1'1
case
end
sync always
update \cia__data_o $0\cia__data_o[63:0]
end
- attribute \src "libresoc.v:194259.3-194267.6"
- process $proc$libresoc.v:194259$13267
+ attribute \src "libresoc.v:194155.3-194163.6"
+ process $proc$libresoc.v:194155$13059
assign { } { }
assign { } { }
- assign $0\ren_delay$12$next[2:0]$13268 $1\ren_delay$12$next[2:0]$13269
- attribute \src "libresoc.v:194260.5-194260.29"
+ assign $0\ren_delay$12$next[2:0]$13060 $1\ren_delay$12$next[2:0]$13061
+ attribute \src "libresoc.v:194156.5-194156.29"
switch \initial
- attribute \src "libresoc.v:194260.9-194260.17"
+ attribute \src "libresoc.v:194156.9-194156.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$12$next[2:0]$13269 3'000
+ assign $1\ren_delay$12$next[2:0]$13061 3'000
case
- assign $1\ren_delay$12$next[2:0]$13269 \msr__ren
+ assign $1\ren_delay$12$next[2:0]$13061 \msr__ren
end
sync always
- update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13268
+ update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13060
end
- attribute \src "libresoc.v:194268.3-194277.6"
- process $proc$libresoc.v:194268$13270
+ attribute \src "libresoc.v:194164.3-194173.6"
+ process $proc$libresoc.v:194164$13062
assign { } { }
assign { } { }
assign $0\msr__data_o[63:0] $1\msr__data_o[63:0]
- attribute \src "libresoc.v:194269.5-194269.29"
+ attribute \src "libresoc.v:194165.5-194165.29"
switch \initial
- attribute \src "libresoc.v:194269.9-194269.17"
+ attribute \src "libresoc.v:194165.9-194165.17"
case 1'1
case
end
sync always
update \msr__data_o $0\msr__data_o[63:0]
end
- connect \$10 $or$libresoc.v:194152$13245_Y
- connect \$13 $reduce_or$libresoc.v:194153$13246_Y
- connect \$15 $or$libresoc.v:194154$13247_Y
- connect \$17 $or$libresoc.v:194155$13248_Y
- connect \$20 $reduce_or$libresoc.v:194156$13249_Y
- connect \$22 $or$libresoc.v:194157$13250_Y
- connect \$24 $or$libresoc.v:194158$13251_Y
- connect \$6 $reduce_or$libresoc.v:194159$13252_Y
- connect \$8 $or$libresoc.v:194160$13253_Y
+ connect \$10 $or$libresoc.v:194048$13037_Y
+ connect \$13 $reduce_or$libresoc.v:194049$13038_Y
+ connect \$15 $or$libresoc.v:194050$13039_Y
+ connect \$17 $or$libresoc.v:194051$13040_Y
+ connect \$20 $reduce_or$libresoc.v:194052$13041_Y
+ connect \$22 $or$libresoc.v:194053$13042_Y
+ connect \$24 $or$libresoc.v:194054$13043_Y
+ connect \$6 $reduce_or$libresoc.v:194055$13044_Y
+ connect \$8 $or$libresoc.v:194056$13045_Y
connect \reg_2_d_wr12__data_i \data_i
connect \reg_1_d_wr11__data_i \data_i
connect \reg_0_d_wr10__data_i \data_i
connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
end
-attribute \src "libresoc.v:194301.1-194359.10"
+attribute \src "libresoc.v:194197.1-194255.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l"
attribute \generator "nMigen"
module \sto_l
- attribute \src "libresoc.v:194302.7-194302.20"
+ attribute \src "libresoc.v:194198.7-194198.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:194347.3-194355.6"
- wire $0\q_int$next[0:0]$13287
- attribute \src "libresoc.v:194345.3-194346.27"
+ attribute \src "libresoc.v:194243.3-194251.6"
+ wire $0\q_int$next[0:0]$13079
+ attribute \src "libresoc.v:194241.3-194242.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:194347.3-194355.6"
- wire $1\q_int$next[0:0]$13288
- attribute \src "libresoc.v:194324.7-194324.19"
+ attribute \src "libresoc.v:194243.3-194251.6"
+ wire $1\q_int$next[0:0]$13080
+ attribute \src "libresoc.v:194220.7-194220.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:194337.17-194337.96"
- wire $and$libresoc.v:194337$13277_Y
- attribute \src "libresoc.v:194342.17-194342.96"
- wire $and$libresoc.v:194342$13282_Y
- attribute \src "libresoc.v:194339.18-194339.93"
- wire $not$libresoc.v:194339$13279_Y
- attribute \src "libresoc.v:194341.17-194341.92"
- wire $not$libresoc.v:194341$13281_Y
- attribute \src "libresoc.v:194344.17-194344.92"
- wire $not$libresoc.v:194344$13284_Y
- attribute \src "libresoc.v:194338.18-194338.98"
- wire $or$libresoc.v:194338$13278_Y
- attribute \src "libresoc.v:194340.18-194340.99"
- wire $or$libresoc.v:194340$13280_Y
- attribute \src "libresoc.v:194343.17-194343.97"
- wire $or$libresoc.v:194343$13283_Y
+ attribute \src "libresoc.v:194233.17-194233.96"
+ wire $and$libresoc.v:194233$13069_Y
+ attribute \src "libresoc.v:194238.17-194238.96"
+ wire $and$libresoc.v:194238$13074_Y
+ attribute \src "libresoc.v:194235.18-194235.93"
+ wire $not$libresoc.v:194235$13071_Y
+ attribute \src "libresoc.v:194237.17-194237.92"
+ wire $not$libresoc.v:194237$13073_Y
+ attribute \src "libresoc.v:194240.17-194240.92"
+ wire $not$libresoc.v:194240$13076_Y
+ attribute \src "libresoc.v:194234.18-194234.98"
+ wire $or$libresoc.v:194234$13070_Y
+ attribute \src "libresoc.v:194236.18-194236.99"
+ wire $or$libresoc.v:194236$13072_Y
+ attribute \src "libresoc.v:194239.17-194239.97"
+ wire $or$libresoc.v:194239$13075_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:194302.7-194302.15"
+ attribute \src "libresoc.v:194198.7-194198.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_sto
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:194337$13277
+ cell $and $and$libresoc.v:194233$13069
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:194337$13277_Y
+ connect \Y $and$libresoc.v:194233$13069_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:194342$13282
+ cell $and $and$libresoc.v:194238$13074
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:194342$13282_Y
+ connect \Y $and$libresoc.v:194238$13074_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:194339$13279
+ cell $not $not$libresoc.v:194235$13071
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_sto
- connect \Y $not$libresoc.v:194339$13279_Y
+ connect \Y $not$libresoc.v:194235$13071_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:194341$13281
+ cell $not $not$libresoc.v:194237$13073
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:194341$13281_Y
+ connect \Y $not$libresoc.v:194237$13073_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:194344$13284
+ cell $not $not$libresoc.v:194240$13076
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_sto
- connect \Y $not$libresoc.v:194344$13284_Y
+ connect \Y $not$libresoc.v:194240$13076_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:194338$13278
+ cell $or $or$libresoc.v:194234$13070
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_sto
- connect \Y $or$libresoc.v:194338$13278_Y
+ connect \Y $or$libresoc.v:194234$13070_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:194340$13280
+ cell $or $or$libresoc.v:194236$13072
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_sto
connect \B \q_int
- connect \Y $or$libresoc.v:194340$13280_Y
+ connect \Y $or$libresoc.v:194236$13072_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:194343$13283
+ cell $or $or$libresoc.v:194239$13075
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_sto
- connect \Y $or$libresoc.v:194343$13283_Y
+ connect \Y $or$libresoc.v:194239$13075_Y
end
- attribute \src "libresoc.v:194302.7-194302.20"
- process $proc$libresoc.v:194302$13289
+ attribute \src "libresoc.v:194198.7-194198.20"
+ process $proc$libresoc.v:194198$13081
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:194324.7-194324.19"
- process $proc$libresoc.v:194324$13290
+ attribute \src "libresoc.v:194220.7-194220.19"
+ process $proc$libresoc.v:194220$13082
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:194345.3-194346.27"
- process $proc$libresoc.v:194345$13285
+ attribute \src "libresoc.v:194241.3-194242.27"
+ process $proc$libresoc.v:194241$13077
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:194347.3-194355.6"
- process $proc$libresoc.v:194347$13286
+ attribute \src "libresoc.v:194243.3-194251.6"
+ process $proc$libresoc.v:194243$13078
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$13287 $1\q_int$next[0:0]$13288
- attribute \src "libresoc.v:194348.5-194348.29"
+ assign $0\q_int$next[0:0]$13079 $1\q_int$next[0:0]$13080
+ attribute \src "libresoc.v:194244.5-194244.29"
switch \initial
- attribute \src "libresoc.v:194348.9-194348.17"
+ attribute \src "libresoc.v:194244.9-194244.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$13288 1'0
+ assign $1\q_int$next[0:0]$13080 1'0
case
- assign $1\q_int$next[0:0]$13288 \$5
+ assign $1\q_int$next[0:0]$13080 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$13287
+ update \q_int$next $0\q_int$next[0:0]$13079
end
- connect \$9 $and$libresoc.v:194337$13277_Y
- connect \$11 $or$libresoc.v:194338$13278_Y
- connect \$13 $not$libresoc.v:194339$13279_Y
- connect \$15 $or$libresoc.v:194340$13280_Y
- connect \$1 $not$libresoc.v:194341$13281_Y
- connect \$3 $and$libresoc.v:194342$13282_Y
- connect \$5 $or$libresoc.v:194343$13283_Y
- connect \$7 $not$libresoc.v:194344$13284_Y
+ connect \$9 $and$libresoc.v:194233$13069_Y
+ connect \$11 $or$libresoc.v:194234$13070_Y
+ connect \$13 $not$libresoc.v:194235$13071_Y
+ connect \$15 $or$libresoc.v:194236$13072_Y
+ connect \$1 $not$libresoc.v:194237$13073_Y
+ connect \$3 $and$libresoc.v:194238$13074_Y
+ connect \$5 $or$libresoc.v:194239$13075_Y
+ connect \$7 $not$libresoc.v:194240$13076_Y
connect \qlq_sto \$15
connect \qn_sto \$13
connect \q_sto \$11
end
-attribute \src "libresoc.v:194364.1-195353.10"
+attribute \src "libresoc.v:194260.1-195249.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
wire output 6 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire input 8 \TAP_bus__tms
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230"
wire output 5 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 320 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10"
wire width 2 input 322 \clk_sel_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229"
wire input 4 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire input 296 \dbus__ack
wire output 15 \jtag_wb__stb
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740"
wire output 16 \jtag_wb__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231"
wire input 3 \memerr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 121 \mspi0_clk__core__o
wire output 133 \mtwi_sda__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 134 \mtwi_sda__pad__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 325 \pc_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 1 \pc_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226"
wire width 64 output 2 \pc_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1088"
wire output 323 \pll_18_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
wire \pll_clk_24_i
wire output 324 \pll_lck_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12"
wire \pll_pll_18_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1098"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103"
wire \pllclk_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1098"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103"
wire \pllclk_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 321 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 187 \sdr_a_0__core__o
wire input 219 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 220 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire \ti_coresync_clk
attribute \module_not_derived 1
- attribute \src "libresoc.v:195027.7-195033.4"
+ attribute \src "libresoc.v:194923.7-194929.4"
cell \pll \pll
connect \clk_24_i \pll_clk_24_i
connect \clk_pll_o \pll_clk_pll_o
connect \pll_lck_o \pll_lck_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:195034.6-195347.4"
+ attribute \src "libresoc.v:194930.6-195243.4"
cell \ti \ti
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \pll_clk_24_i \clk
connect \pllclk_clk \pll_clk_pll_o
end
-attribute \src "libresoc.v:195357.1-200679.10"
+attribute \src "libresoc.v:195253.1-200575.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti"
attribute \generator "nMigen"
module \ti
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $0\core_asmcode$next[7:0]$13782
- attribute \src "libresoc.v:197787.3-197788.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $0\core_asmcode$next[7:0]$13574
+ attribute \src "libresoc.v:197683.3-197684.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:198598.3-198642.6"
- wire $0\core_bigendian_i$10$next[0:0]$13577
- attribute \src "libresoc.v:197917.3-197918.57"
- wire $0\core_bigendian_i$10[0:0]$13502
- attribute \src "libresoc.v:195632.7-195632.35"
- wire $0\core_bigendian_i$10[0:0]$13995
- attribute \src "libresoc.v:199361.3-199373.6"
+ attribute \src "libresoc.v:198494.3-198538.6"
+ wire $0\core_bigendian_i$10$next[0:0]$13369
+ attribute \src "libresoc.v:197813.3-197814.57"
+ wire $0\core_bigendian_i$10[0:0]$13294
+ attribute \src "libresoc.v:195528.7-195528.35"
+ wire $0\core_bigendian_i$10[0:0]$13787
+ attribute \src "libresoc.v:199257.3-199269.6"
wire width 3 $0\core_cia__ren[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $0\core_core_core_cia$next[63:0]$13783
- attribute \src "libresoc.v:197861.3-197862.53"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $0\core_core_core_cia$next[63:0]$13575
+ attribute \src "libresoc.v:197757.3-197758.53"
wire width 64 $0\core_core_core_cia[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $0\core_core_core_cr_rd$next[7:0]$13784
- attribute \src "libresoc.v:197905.3-197906.57"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $0\core_core_core_cr_rd$next[7:0]$13576
+ attribute \src "libresoc.v:197801.3-197802.57"
wire width 8 $0\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_cr_rd_ok$next[0:0]$13785
- attribute \src "libresoc.v:197907.3-197908.63"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_cr_rd_ok$next[0:0]$13577
+ attribute \src "libresoc.v:197803.3-197804.63"
wire $0\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $0\core_core_core_cr_wr$next[7:0]$13786
- attribute \src "libresoc.v:197909.3-197910.57"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $0\core_core_core_cr_wr$next[7:0]$13578
+ attribute \src "libresoc.v:197805.3-197806.57"
wire width 8 $0\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$3$next[0:0]$13787
- attribute \src "libresoc.v:197887.3-197888.75"
- wire $0\core_core_core_exc_$signal$3[0:0]$13480
- attribute \src "libresoc.v:195658.7-195658.44"
- wire $0\core_core_core_exc_$signal$3[0:0]$14003
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$4$next[0:0]$13788
- attribute \src "libresoc.v:197889.3-197890.75"
- wire $0\core_core_core_exc_$signal$4[0:0]$13482
- attribute \src "libresoc.v:195662.7-195662.44"
- wire $0\core_core_core_exc_$signal$4[0:0]$14005
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$5$next[0:0]$13789
- attribute \src "libresoc.v:197891.3-197892.75"
- wire $0\core_core_core_exc_$signal$5[0:0]$13484
- attribute \src "libresoc.v:195666.7-195666.44"
- wire $0\core_core_core_exc_$signal$5[0:0]$14007
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$6$next[0:0]$13790
- attribute \src "libresoc.v:197893.3-197894.75"
- wire $0\core_core_core_exc_$signal$6[0:0]$13486
- attribute \src "libresoc.v:195670.7-195670.44"
- wire $0\core_core_core_exc_$signal$6[0:0]$14009
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$7$next[0:0]$13791
- attribute \src "libresoc.v:197897.3-197898.75"
- wire $0\core_core_core_exc_$signal$7[0:0]$13489
- attribute \src "libresoc.v:195674.7-195674.44"
- wire $0\core_core_core_exc_$signal$7[0:0]$14011
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$8$next[0:0]$13792
- attribute \src "libresoc.v:197899.3-197900.75"
- wire $0\core_core_core_exc_$signal$8[0:0]$13491
- attribute \src "libresoc.v:195678.7-195678.44"
- wire $0\core_core_core_exc_$signal$8[0:0]$14013
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$9$next[0:0]$13793
- attribute \src "libresoc.v:197901.3-197902.75"
- wire $0\core_core_core_exc_$signal$9[0:0]$13493
- attribute \src "libresoc.v:195682.7-195682.44"
- wire $0\core_core_core_exc_$signal$9[0:0]$14015
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_exc_$signal$next[0:0]$13794
- attribute \src "libresoc.v:197885.3-197886.71"
- wire $0\core_core_core_exc_$signal[0:0]$13478
- attribute \src "libresoc.v:195656.7-195656.42"
- wire $0\core_core_core_exc_$signal[0:0]$14001
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 14 $0\core_core_core_fn_unit$next[13:0]$13795
- attribute \src "libresoc.v:197867.3-197868.61"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$3$next[0:0]$13579
+ attribute \src "libresoc.v:197783.3-197784.75"
+ wire $0\core_core_core_exc_$signal$3[0:0]$13272
+ attribute \src "libresoc.v:195554.7-195554.44"
+ wire $0\core_core_core_exc_$signal$3[0:0]$13795
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$4$next[0:0]$13580
+ attribute \src "libresoc.v:197785.3-197786.75"
+ wire $0\core_core_core_exc_$signal$4[0:0]$13274
+ attribute \src "libresoc.v:195558.7-195558.44"
+ wire $0\core_core_core_exc_$signal$4[0:0]$13797
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$5$next[0:0]$13581
+ attribute \src "libresoc.v:197787.3-197788.75"
+ wire $0\core_core_core_exc_$signal$5[0:0]$13276
+ attribute \src "libresoc.v:195562.7-195562.44"
+ wire $0\core_core_core_exc_$signal$5[0:0]$13799
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$6$next[0:0]$13582
+ attribute \src "libresoc.v:197789.3-197790.75"
+ wire $0\core_core_core_exc_$signal$6[0:0]$13278
+ attribute \src "libresoc.v:195566.7-195566.44"
+ wire $0\core_core_core_exc_$signal$6[0:0]$13801
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$7$next[0:0]$13583
+ attribute \src "libresoc.v:197793.3-197794.75"
+ wire $0\core_core_core_exc_$signal$7[0:0]$13281
+ attribute \src "libresoc.v:195570.7-195570.44"
+ wire $0\core_core_core_exc_$signal$7[0:0]$13803
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$8$next[0:0]$13584
+ attribute \src "libresoc.v:197795.3-197796.75"
+ wire $0\core_core_core_exc_$signal$8[0:0]$13283
+ attribute \src "libresoc.v:195574.7-195574.44"
+ wire $0\core_core_core_exc_$signal$8[0:0]$13805
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$9$next[0:0]$13585
+ attribute \src "libresoc.v:197797.3-197798.75"
+ wire $0\core_core_core_exc_$signal$9[0:0]$13285
+ attribute \src "libresoc.v:195578.7-195578.44"
+ wire $0\core_core_core_exc_$signal$9[0:0]$13807
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_exc_$signal$next[0:0]$13586
+ attribute \src "libresoc.v:197781.3-197782.71"
+ wire $0\core_core_core_exc_$signal[0:0]$13270
+ attribute \src "libresoc.v:195552.7-195552.42"
+ wire $0\core_core_core_exc_$signal[0:0]$13793
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 14 $0\core_core_core_fn_unit$next[13:0]$13587
+ attribute \src "libresoc.v:197763.3-197764.61"
wire width 14 $0\core_core_core_fn_unit[13:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 2 $0\core_core_core_input_carry$next[1:0]$13796
- attribute \src "libresoc.v:197881.3-197882.69"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 2 $0\core_core_core_input_carry$next[1:0]$13588
+ attribute \src "libresoc.v:197777.3-197778.69"
wire width 2 $0\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 32 $0\core_core_core_insn$next[31:0]$13797
- attribute \src "libresoc.v:197863.3-197864.55"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 32 $0\core_core_core_insn$next[31:0]$13589
+ attribute \src "libresoc.v:197759.3-197760.55"
wire width 32 $0\core_core_core_insn[31:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_core_insn_type$next[6:0]$13798
- attribute \src "libresoc.v:197865.3-197866.65"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_core_insn_type$next[6:0]$13590
+ attribute \src "libresoc.v:197761.3-197762.65"
wire width 7 $0\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_is_32bit$next[0:0]$13799
- attribute \src "libresoc.v:197913.3-197914.63"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_is_32bit$next[0:0]$13591
+ attribute \src "libresoc.v:197809.3-197810.63"
wire $0\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $0\core_core_core_msr$next[63:0]$13800
- attribute \src "libresoc.v:197859.3-197860.53"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $0\core_core_core_msr$next[63:0]$13592
+ attribute \src "libresoc.v:197755.3-197756.53"
wire width 64 $0\core_core_core_msr[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_oe$next[0:0]$13801
- attribute \src "libresoc.v:197877.3-197878.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_oe$next[0:0]$13593
+ attribute \src "libresoc.v:197773.3-197774.51"
wire $0\core_core_core_oe[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_oe_ok$next[0:0]$13802
- attribute \src "libresoc.v:197879.3-197880.57"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_oe_ok$next[0:0]$13594
+ attribute \src "libresoc.v:197775.3-197776.57"
wire $0\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_rc$next[0:0]$13803
- attribute \src "libresoc.v:197871.3-197872.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_rc$next[0:0]$13595
+ attribute \src "libresoc.v:197767.3-197768.51"
wire $0\core_core_core_rc[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_core_rc_ok$next[0:0]$13804
- attribute \src "libresoc.v:197875.3-197876.57"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_core_rc_ok$next[0:0]$13596
+ attribute \src "libresoc.v:197771.3-197772.57"
wire $0\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 13 $0\core_core_core_trapaddr$next[12:0]$13805
- attribute \src "libresoc.v:197903.3-197904.63"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 13 $0\core_core_core_trapaddr$next[12:0]$13597
+ attribute \src "libresoc.v:197799.3-197800.63"
wire width 13 $0\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $0\core_core_core_traptype$next[7:0]$13806
- attribute \src "libresoc.v:197883.3-197884.63"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $0\core_core_core_traptype$next[7:0]$13598
+ attribute \src "libresoc.v:197779.3-197780.63"
wire width 8 $0\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_cr_in1$next[6:0]$13807
- attribute \src "libresoc.v:197841.3-197842.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_cr_in1$next[6:0]$13599
+ attribute \src "libresoc.v:197737.3-197738.49"
wire width 7 $0\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_cr_in1_ok$next[0:0]$13808
- attribute \src "libresoc.v:197843.3-197844.55"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_cr_in1_ok$next[0:0]$13600
+ attribute \src "libresoc.v:197739.3-197740.55"
wire $0\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_cr_in2$1$next[6:0]$13809
- attribute \src "libresoc.v:197849.3-197850.55"
- wire width 7 $0\core_core_cr_in2$1[6:0]$13458
- attribute \src "libresoc.v:195840.13-195840.41"
- wire width 7 $0\core_core_cr_in2$1[6:0]$14032
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_cr_in2$next[6:0]$13810
- attribute \src "libresoc.v:197845.3-197846.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_cr_in2$1$next[6:0]$13601
+ attribute \src "libresoc.v:197745.3-197746.55"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$13250
+ attribute \src "libresoc.v:195736.13-195736.41"
+ wire width 7 $0\core_core_cr_in2$1[6:0]$13824
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_cr_in2$next[6:0]$13602
+ attribute \src "libresoc.v:197741.3-197742.49"
wire width 7 $0\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_cr_in2_ok$2$next[0:0]$13811
- attribute \src "libresoc.v:197853.3-197854.61"
- wire $0\core_core_cr_in2_ok$2[0:0]$13461
- attribute \src "libresoc.v:195848.7-195848.37"
- wire $0\core_core_cr_in2_ok$2[0:0]$14035
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_cr_in2_ok$next[0:0]$13812
- attribute \src "libresoc.v:197847.3-197848.55"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_cr_in2_ok$2$next[0:0]$13603
+ attribute \src "libresoc.v:197749.3-197750.61"
+ wire $0\core_core_cr_in2_ok$2[0:0]$13253
+ attribute \src "libresoc.v:195744.7-195744.37"
+ wire $0\core_core_cr_in2_ok$2[0:0]$13827
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_cr_in2_ok$next[0:0]$13604
+ attribute \src "libresoc.v:197743.3-197744.55"
wire $0\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_cr_out$next[6:0]$13813
- attribute \src "libresoc.v:197855.3-197856.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_cr_out$next[6:0]$13605
+ attribute \src "libresoc.v:197751.3-197752.49"
wire width 7 $0\core_core_cr_out[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_cr_wr_ok$next[0:0]$13814
- attribute \src "libresoc.v:197911.3-197912.53"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_cr_wr_ok$next[0:0]$13606
+ attribute \src "libresoc.v:197807.3-197808.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $0\core_core_dststep$next[6:0]$13531
- attribute \src "libresoc.v:197777.3-197778.51"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $0\core_core_dststep$next[6:0]$13323
+ attribute \src "libresoc.v:197673.3-197674.51"
wire width 7 $0\core_core_dststep[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_ea$next[6:0]$13815
- attribute \src "libresoc.v:197793.3-197794.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_ea$next[6:0]$13607
+ attribute \src "libresoc.v:197689.3-197690.41"
wire width 7 $0\core_core_ea[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $0\core_core_fast1$next[2:0]$13816
- attribute \src "libresoc.v:197823.3-197824.47"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $0\core_core_fast1$next[2:0]$13608
+ attribute \src "libresoc.v:197719.3-197720.47"
wire width 3 $0\core_core_fast1[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_fast1_ok$next[0:0]$13817
- attribute \src "libresoc.v:197825.3-197826.53"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_fast1_ok$next[0:0]$13609
+ attribute \src "libresoc.v:197721.3-197722.53"
wire $0\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $0\core_core_fast2$next[2:0]$13818
- attribute \src "libresoc.v:197827.3-197828.47"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $0\core_core_fast2$next[2:0]$13610
+ attribute \src "libresoc.v:197723.3-197724.47"
wire width 3 $0\core_core_fast2[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_fast2_ok$next[0:0]$13819
- attribute \src "libresoc.v:197831.3-197832.53"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_fast2_ok$next[0:0]$13611
+ attribute \src "libresoc.v:197727.3-197728.53"
wire $0\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $0\core_core_fasto1$next[2:0]$13820
- attribute \src "libresoc.v:197833.3-197834.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $0\core_core_fasto1$next[2:0]$13612
+ attribute \src "libresoc.v:197729.3-197730.49"
wire width 3 $0\core_core_fasto1[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $0\core_core_fasto2$next[2:0]$13821
- attribute \src "libresoc.v:197837.3-197838.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $0\core_core_fasto2$next[2:0]$13613
+ attribute \src "libresoc.v:197733.3-197734.49"
wire width 3 $0\core_core_fasto2[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_lk$next[0:0]$13822
- attribute \src "libresoc.v:197869.3-197870.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_lk$next[0:0]$13614
+ attribute \src "libresoc.v:197765.3-197766.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $0\core_core_maxvl$next[6:0]$13532
- attribute \src "libresoc.v:197783.3-197784.47"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $0\core_core_maxvl$next[6:0]$13324
+ attribute \src "libresoc.v:197679.3-197680.47"
wire width 7 $0\core_core_maxvl[6:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $0\core_core_pc$next[63:0]$13533
- attribute \src "libresoc.v:197755.3-197756.41"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $0\core_core_pc$next[63:0]$13325
+ attribute \src "libresoc.v:197651.3-197652.41"
wire width 64 $0\core_core_pc[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_reg1$next[6:0]$13823
- attribute \src "libresoc.v:197797.3-197798.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_reg1$next[6:0]$13615
+ attribute \src "libresoc.v:197693.3-197694.45"
wire width 7 $0\core_core_reg1[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_reg1_ok$next[0:0]$13824
- attribute \src "libresoc.v:197799.3-197800.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_reg1_ok$next[0:0]$13616
+ attribute \src "libresoc.v:197695.3-197696.51"
wire $0\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_reg2$next[6:0]$13825
- attribute \src "libresoc.v:197801.3-197802.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_reg2$next[6:0]$13617
+ attribute \src "libresoc.v:197697.3-197698.45"
wire width 7 $0\core_core_reg2[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_reg2_ok$next[0:0]$13826
- attribute \src "libresoc.v:197803.3-197804.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_reg2_ok$next[0:0]$13618
+ attribute \src "libresoc.v:197699.3-197700.51"
wire $0\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_reg3$next[6:0]$13827
- attribute \src "libresoc.v:197805.3-197806.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_reg3$next[6:0]$13619
+ attribute \src "libresoc.v:197701.3-197702.45"
wire width 7 $0\core_core_reg3[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_reg3_ok$next[0:0]$13828
- attribute \src "libresoc.v:197809.3-197810.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_reg3_ok$next[0:0]$13620
+ attribute \src "libresoc.v:197705.3-197706.51"
wire $0\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $0\core_core_rego$next[6:0]$13829
- attribute \src "libresoc.v:197789.3-197790.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $0\core_core_rego$next[6:0]$13621
+ attribute \src "libresoc.v:197685.3-197686.45"
wire width 7 $0\core_core_rego[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $0\core_core_spr1$next[9:0]$13830
- attribute \src "libresoc.v:197815.3-197816.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $0\core_core_spr1$next[9:0]$13622
+ attribute \src "libresoc.v:197711.3-197712.45"
wire width 10 $0\core_core_spr1[9:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_core_spr1_ok$next[0:0]$13831
- attribute \src "libresoc.v:197817.3-197818.51"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_core_spr1_ok$next[0:0]$13623
+ attribute \src "libresoc.v:197713.3-197714.51"
wire $0\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $0\core_core_spro$next[9:0]$13832
- attribute \src "libresoc.v:197811.3-197812.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $0\core_core_spro$next[9:0]$13624
+ attribute \src "libresoc.v:197707.3-197708.45"
wire width 10 $0\core_core_spro[9:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $0\core_core_srcstep$next[6:0]$13534
- attribute \src "libresoc.v:197779.3-197780.51"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $0\core_core_srcstep$next[6:0]$13326
+ attribute \src "libresoc.v:197675.3-197676.51"
wire width 7 $0\core_core_srcstep[6:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $0\core_core_subvl$next[1:0]$13535
- attribute \src "libresoc.v:197775.3-197776.47"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $0\core_core_subvl$next[1:0]$13327
+ attribute \src "libresoc.v:197671.3-197672.47"
wire width 2 $0\core_core_subvl[1:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $0\core_core_svstep$next[1:0]$13536
- attribute \src "libresoc.v:197773.3-197774.49"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $0\core_core_svstep$next[1:0]$13328
+ attribute \src "libresoc.v:197669.3-197670.49"
wire width 2 $0\core_core_svstep[1:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $0\core_core_vl$next[6:0]$13537
- attribute \src "libresoc.v:197781.3-197782.41"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $0\core_core_vl$next[6:0]$13329
+ attribute \src "libresoc.v:197677.3-197678.41"
wire width 7 $0\core_core_vl[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $0\core_core_xer_in$next[2:0]$13833
- attribute \src "libresoc.v:197819.3-197820.49"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $0\core_core_xer_in$next[2:0]$13625
+ attribute \src "libresoc.v:197715.3-197716.49"
wire width 3 $0\core_core_xer_in[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_cr_out_ok$next[0:0]$13834
- attribute \src "libresoc.v:197857.3-197858.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_cr_out_ok$next[0:0]$13626
+ attribute \src "libresoc.v:197753.3-197754.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:198890.3-198899.6"
- wire width 64 $0\core_data_i$12[63:0]$13596
- attribute \src "libresoc.v:199492.3-199571.6"
+ attribute \src "libresoc.v:198786.3-198795.6"
+ wire width 64 $0\core_data_i$12[63:0]$13388
+ attribute \src "libresoc.v:199388.3-199467.6"
wire width 64 $0\core_data_i[63:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $0\core_dec$next[63:0]$13538
- attribute \src "libresoc.v:197771.3-197772.33"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $0\core_dec$next[63:0]$13330
+ attribute \src "libresoc.v:197667.3-197668.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:199007.3-199016.6"
+ attribute \src "libresoc.v:198903.3-198912.6"
wire width 5 $0\core_dmi__addr[4:0]
- attribute \src "libresoc.v:199017.3-199026.6"
+ attribute \src "libresoc.v:198913.3-198922.6"
wire $0\core_dmi__ren[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_ea_ok$next[0:0]$13835
- attribute \src "libresoc.v:197795.3-197796.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_ea_ok$next[0:0]$13627
+ attribute \src "libresoc.v:197691.3-197692.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire $0\core_eint$next[0:0]$13539
- attribute \src "libresoc.v:197769.3-197770.35"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire $0\core_eint$next[0:0]$13331
+ attribute \src "libresoc.v:197665.3-197666.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_fasto1_ok$next[0:0]$13836
- attribute \src "libresoc.v:197835.3-197836.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_fasto1_ok$next[0:0]$13628
+ attribute \src "libresoc.v:197731.3-197732.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_fasto2_ok$next[0:0]$13837
- attribute \src "libresoc.v:197839.3-197840.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_fasto2_ok$next[0:0]$13629
+ attribute \src "libresoc.v:197735.3-197736.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:199056.3-199065.6"
+ attribute \src "libresoc.v:198952.3-198961.6"
wire width 8 $0\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:199095.3-199104.6"
+ attribute \src "libresoc.v:198991.3-199000.6"
wire width 3 $0\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:199215.3-199237.6"
- wire width 3 $0\core_issue__addr$13[2:0]$13636
- attribute \src "libresoc.v:199134.3-199152.6"
+ attribute \src "libresoc.v:199111.3-199133.6"
+ wire width 3 $0\core_issue__addr$13[2:0]$13428
+ attribute \src "libresoc.v:199030.3-199048.6"
wire width 3 $0\core_issue__addr[2:0]
- attribute \src "libresoc.v:199261.3-199283.6"
+ attribute \src "libresoc.v:199157.3-199179.6"
wire width 64 $0\core_issue__data_i[63:0]
- attribute \src "libresoc.v:199153.3-199171.6"
+ attribute \src "libresoc.v:199049.3-199067.6"
wire $0\core_issue__ren[0:0]
- attribute \src "libresoc.v:199238.3-199260.6"
+ attribute \src "libresoc.v:199134.3-199156.6"
wire $0\core_issue__wen[0:0]
- attribute \src "libresoc.v:198936.3-198951.6"
+ attribute \src "libresoc.v:198832.3-198847.6"
wire $0\core_issue_i[0:0]
- attribute \src "libresoc.v:198911.3-198935.6"
+ attribute \src "libresoc.v:198807.3-198831.6"
wire $0\core_ivalid_i[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $0\core_msr$next[63:0]$13540
- attribute \src "libresoc.v:197767.3-197768.33"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $0\core_msr$next[63:0]$13332
+ attribute \src "libresoc.v:197663.3-197664.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:199572.3-199587.6"
+ attribute \src "libresoc.v:199468.3-199483.6"
wire width 3 $0\core_msr__ren[2:0]
- attribute \src "libresoc.v:198573.3-198597.6"
- wire width 32 $0\core_raw_insn_i$next[31:0]$13572
- attribute \src "libresoc.v:197939.3-197940.47"
+ attribute \src "libresoc.v:198469.3-198493.6"
+ wire width 32 $0\core_raw_insn_i$next[31:0]$13364
+ attribute \src "libresoc.v:197835.3-197836.47"
wire width 32 $0\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_rego_ok$next[0:0]$13838
- attribute \src "libresoc.v:197791.3-197792.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_rego_ok$next[0:0]$13630
+ attribute \src "libresoc.v:197687.3-197688.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_spro_ok$next[0:0]$13839
- attribute \src "libresoc.v:197813.3-197814.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_spro_ok$next[0:0]$13631
+ attribute \src "libresoc.v:197709.3-197710.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:200151.3-200197.6"
+ attribute \src "libresoc.v:200047.3-200093.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:199399.3-199411.6"
+ attribute \src "libresoc.v:199295.3-199307.6"
wire width 3 $0\core_sv__ren[2:0]
- attribute \src "libresoc.v:198643.3-198687.6"
- wire $0\core_sv_a_nz$next[0:0]$13582
- attribute \src "libresoc.v:197895.3-197896.41"
+ attribute \src "libresoc.v:198539.3-198583.6"
+ wire $0\core_sv_a_nz$next[0:0]$13374
+ attribute \src "libresoc.v:197791.3-197792.41"
wire $0\core_sv_a_nz[0:0]
- attribute \src "libresoc.v:198880.3-198889.6"
- wire width 3 $0\core_wen$11[2:0]$13593
- attribute \src "libresoc.v:199412.3-199491.6"
+ attribute \src "libresoc.v:198776.3-198785.6"
+ wire width 3 $0\core_wen$11[2:0]$13385
+ attribute \src "libresoc.v:199308.3-199387.6"
wire width 3 $0\core_wen[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $0\core_xer_out$next[0:0]$13840
- attribute \src "libresoc.v:197821.3-197822.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $0\core_xer_out$next[0:0]$13632
+ attribute \src "libresoc.v:197717.3-197718.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:197953.3-197954.43"
+ attribute \src "libresoc.v:197849.3-197850.43"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $0\cur_cur_dststep$next[6:0]$13677
- attribute \src "libresoc.v:197937.3-197938.47"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $0\cur_cur_dststep$next[6:0]$13469
+ attribute \src "libresoc.v:197833.3-197834.47"
wire width 7 $0\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $0\cur_cur_maxvl$next[6:0]$13678
- attribute \src "libresoc.v:197945.3-197946.43"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $0\cur_cur_maxvl$next[6:0]$13470
+ attribute \src "libresoc.v:197841.3-197842.43"
wire width 7 $0\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $0\cur_cur_srcstep$next[6:0]$13679
- attribute \src "libresoc.v:197941.3-197942.47"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $0\cur_cur_srcstep$next[6:0]$13471
+ attribute \src "libresoc.v:197837.3-197838.47"
wire width 7 $0\cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $0\cur_cur_subvl$next[1:0]$13680
- attribute \src "libresoc.v:197935.3-197936.43"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $0\cur_cur_subvl$next[1:0]$13472
+ attribute \src "libresoc.v:197831.3-197832.43"
wire width 2 $0\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $0\cur_cur_svstep$next[1:0]$13681
- attribute \src "libresoc.v:197933.3-197934.45"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $0\cur_cur_svstep$next[1:0]$13473
+ attribute \src "libresoc.v:197829.3-197830.45"
wire width 2 $0\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $0\cur_cur_vl$next[6:0]$13682
- attribute \src "libresoc.v:197943.3-197944.37"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $0\cur_cur_vl$next[6:0]$13474
+ attribute \src "libresoc.v:197839.3-197840.37"
wire width 7 $0\cur_cur_vl[6:0]
- attribute \src "libresoc.v:199066.3-199074.6"
- wire $0\d_cr_delay$next[0:0]$13618
- attribute \src "libresoc.v:197829.3-197830.37"
+ attribute \src "libresoc.v:198962.3-198970.6"
+ wire $0\d_cr_delay$next[0:0]$13410
+ attribute \src "libresoc.v:197725.3-197726.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:199027.3-199035.6"
- wire $0\d_reg_delay$next[0:0]$13612
- attribute \src "libresoc.v:197851.3-197852.39"
+ attribute \src "libresoc.v:198923.3-198931.6"
+ wire $0\d_reg_delay$next[0:0]$13404
+ attribute \src "libresoc.v:197747.3-197748.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:199105.3-199113.6"
- wire $0\d_xer_delay$next[0:0]$13624
- attribute \src "libresoc.v:197807.3-197808.39"
+ attribute \src "libresoc.v:199001.3-199009.6"
+ wire $0\d_xer_delay$next[0:0]$13416
+ attribute \src "libresoc.v:197703.3-197704.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:200198.3-200244.6"
+ attribute \src "libresoc.v:200094.3-200140.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:199085.3-199094.6"
+ attribute \src "libresoc.v:198981.3-198990.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:199075.3-199084.6"
+ attribute \src "libresoc.v:198971.3-198980.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:199046.3-199055.6"
+ attribute \src "libresoc.v:198942.3-198951.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:199036.3-199045.6"
+ attribute \src "libresoc.v:198932.3-198941.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:199124.3-199133.6"
+ attribute \src "libresoc.v:199020.3-199029.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:199114.3-199123.6"
+ attribute \src "libresoc.v:199010.3-199019.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:198490.3-198498.6"
- wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13525
- attribute \src "libresoc.v:197765.3-197766.45"
+ attribute \src "libresoc.v:198386.3-198394.6"
+ wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13317
+ attribute \src "libresoc.v:197661.3-197662.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:199588.3-199596.6"
- wire width 64 $0\dbg_dmi_din$next[63:0]$13662
- attribute \src "libresoc.v:197759.3-197760.39"
+ attribute \src "libresoc.v:199484.3-199492.6"
+ wire width 64 $0\dbg_dmi_din$next[63:0]$13454
+ attribute \src "libresoc.v:197655.3-197656.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:198499.3-198507.6"
- wire $0\dbg_dmi_req_i$next[0:0]$13528
- attribute \src "libresoc.v:197763.3-197764.43"
+ attribute \src "libresoc.v:198395.3-198403.6"
+ wire $0\dbg_dmi_req_i$next[0:0]$13320
+ attribute \src "libresoc.v:197659.3-197660.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:199327.3-199335.6"
- wire $0\dbg_dmi_we_i$next[0:0]$13646
- attribute \src "libresoc.v:197761.3-197762.41"
+ attribute \src "libresoc.v:199223.3-199231.6"
+ wire $0\dbg_dmi_we_i$next[0:0]$13438
+ attribute \src "libresoc.v:197657.3-197658.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:199284.3-199303.6"
- wire width 64 $0\dec2_cur_dec$next[63:0]$13641
- attribute \src "libresoc.v:197753.3-197754.41"
+ attribute \src "libresoc.v:199180.3-199199.6"
+ wire width 64 $0\dec2_cur_dec$next[63:0]$13433
+ attribute \src "libresoc.v:197649.3-197650.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:200630.3-200638.6"
- wire $0\dec2_cur_eint$next[0:0]$13987
- attribute \src "libresoc.v:197957.3-197958.43"
+ attribute \src "libresoc.v:200526.3-200534.6"
+ wire $0\dec2_cur_eint$next[0:0]$13779
+ attribute \src "libresoc.v:197853.3-197854.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:199854.3-199878.6"
- wire width 64 $0\dec2_cur_msr$next[63:0]$13725
- attribute \src "libresoc.v:197927.3-197928.41"
+ attribute \src "libresoc.v:199750.3-199774.6"
+ wire width 64 $0\dec2_cur_msr$next[63:0]$13517
+ attribute \src "libresoc.v:197823.3-197824.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:199701.3-199721.6"
- wire width 64 $0\dec2_cur_pc$next[63:0]$13672
- attribute \src "libresoc.v:197947.3-197948.39"
+ attribute \src "libresoc.v:199597.3-199617.6"
+ wire width 64 $0\dec2_cur_pc$next[63:0]$13464
+ attribute \src "libresoc.v:197843.3-197844.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:199902.3-199936.6"
- wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13734
- attribute \src "libresoc.v:197923.3-197924.53"
+ attribute \src "libresoc.v:199798.3-199832.6"
+ wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13526
+ attribute \src "libresoc.v:197819.3-197820.53"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:200639.3-200648.6"
- wire width 2 $0\delay$next[1:0]$13990
- attribute \src "libresoc.v:197955.3-197956.27"
+ attribute \src "libresoc.v:200535.3-200544.6"
+ wire width 2 $0\delay$next[1:0]$13782
+ attribute \src "libresoc.v:197851.3-197852.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:198952.3-198986.6"
- wire $0\exec_fsm_state$next[0:0]$13602
- attribute \src "libresoc.v:197873.3-197874.45"
+ attribute \src "libresoc.v:198848.3-198882.6"
+ wire $0\exec_fsm_state$next[0:0]$13394
+ attribute \src "libresoc.v:197769.3-197770.45"
wire $0\exec_fsm_state[0:0]
- attribute \src "libresoc.v:198900.3-198910.6"
+ attribute \src "libresoc.v:198796.3-198806.6"
wire $0\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:198776.3-198802.6"
+ attribute \src "libresoc.v:198672.3-198698.6"
wire $0\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:198803.3-198838.6"
+ attribute \src "libresoc.v:198699.3-198734.6"
wire $0\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:198987.3-199006.6"
+ attribute \src "libresoc.v:198883.3-198902.6"
wire $0\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:199800.3-199853.6"
- wire width 2 $0\fetch_fsm_state$next[1:0]$13717
- attribute \src "libresoc.v:197929.3-197930.47"
+ attribute \src "libresoc.v:199696.3-199749.6"
+ wire width 2 $0\fetch_fsm_state$next[1:0]$13509
+ attribute \src "libresoc.v:197825.3-197826.47"
wire width 2 $0\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:200484.3-200498.6"
+ attribute \src "libresoc.v:200380.3-200394.6"
wire $0\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:199937.3-199959.6"
+ attribute \src "libresoc.v:199833.3-199855.6"
wire $0\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:199597.3-199607.6"
+ attribute \src "libresoc.v:199493.3-199503.6"
wire $0\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:200036.3-200051.6"
+ attribute \src "libresoc.v:199932.3-199947.6"
wire $0\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:199172.3-199199.6"
- wire width 2 $0\fsm_state$next[1:0]$13631
- attribute \src "libresoc.v:197785.3-197786.35"
+ attribute \src "libresoc.v:199068.3-199095.6"
+ wire width 2 $0\fsm_state$next[1:0]$13423
+ attribute \src "libresoc.v:197681.3-197682.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:199608.3-199623.6"
+ attribute \src "libresoc.v:199504.3-199519.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:199633.3-199666.6"
+ attribute \src "libresoc.v:199529.3-199562.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199667.3-199700.6"
+ attribute \src "libresoc.v:199563.3-199596.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:195358.7-195358.20"
+ attribute \src "libresoc.v:195254.7-195254.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:198688.3-198733.6"
+ attribute \src "libresoc.v:198584.3-198629.6"
wire $0\insn_done[0:0]
- attribute \src "libresoc.v:198839.3-198879.6"
+ attribute \src "libresoc.v:198735.3-198775.6"
wire $0\is_last[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $0\issue_fsm_state$next[2:0]$13742
- attribute \src "libresoc.v:197921.3-197922.47"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $0\issue_fsm_state$next[2:0]$13534
+ attribute \src "libresoc.v:197817.3-197818.47"
wire width 3 $0\issue_fsm_state[2:0]
- attribute \src "libresoc.v:199624.3-199632.6"
- wire $0\jtag_dmi0__ack_o$next[0:0]$13667
- attribute \src "libresoc.v:197757.3-197758.49"
+ attribute \src "libresoc.v:199520.3-199528.6"
+ wire $0\jtag_dmi0__ack_o$next[0:0]$13459
+ attribute \src "libresoc.v:197653.3-197654.49"
wire $0\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:199791.3-199799.6"
- wire width 64 $0\jtag_dmi0__dout$next[63:0]$13714
- attribute \src "libresoc.v:197959.3-197960.47"
+ attribute \src "libresoc.v:199687.3-199695.6"
+ wire width 64 $0\jtag_dmi0__dout$next[63:0]$13506
+ attribute \src "libresoc.v:197855.3-197856.47"
wire width 64 $0\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:199761.3-199790.6"
- wire $0\msr_read$next[0:0]$13708
- attribute \src "libresoc.v:197931.3-197932.33"
+ attribute \src "libresoc.v:199657.3-199686.6"
+ wire $0\msr_read$next[0:0]$13500
+ attribute \src "libresoc.v:197827.3-197828.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:199200.3-199214.6"
+ attribute \src "libresoc.v:199096.3-199110.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $0\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $0\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $0\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $0\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $0\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $0\new_svstate_vl[6:0]
- attribute \src "libresoc.v:199304.3-199326.6"
+ attribute \src "libresoc.v:199200.3-199222.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:199879.3-199901.6"
- wire width 64 $0\nia$next[63:0]$13730
- attribute \src "libresoc.v:197925.3-197926.23"
+ attribute \src "libresoc.v:199775.3-199797.6"
+ wire width 64 $0\nia$next[63:0]$13522
+ attribute \src "libresoc.v:197821.3-197822.23"
wire width 64 $0\nia[63:0]
- attribute \src "libresoc.v:199345.3-199360.6"
+ attribute \src "libresoc.v:199241.3-199256.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:200245.3-200327.6"
- wire $0\pc_changed$next[0:0]$13758
- attribute \src "libresoc.v:197919.3-197920.37"
+ attribute \src "libresoc.v:200141.3-200223.6"
+ wire $0\pc_changed$next[0:0]$13550
+ attribute \src "libresoc.v:197815.3-197816.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:199336.3-199344.6"
- wire $0\pc_ok_delay$next[0:0]$13649
- attribute \src "libresoc.v:197951.3-197952.39"
+ attribute \src "libresoc.v:199232.3-199240.6"
+ wire $0\pc_ok_delay$next[0:0]$13441
+ attribute \src "libresoc.v:197847.3-197848.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:198734.3-198752.6"
+ attribute \src "libresoc.v:198630.3-198648.6"
wire $0\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:198753.3-198775.6"
+ attribute \src "libresoc.v:198649.3-198671.6"
wire $0\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:200401.3-200483.6"
- wire $0\sv_changed$next[0:0]$13770
- attribute \src "libresoc.v:197915.3-197916.37"
+ attribute \src "libresoc.v:200297.3-200379.6"
+ wire $0\sv_changed$next[0:0]$13562
+ attribute \src "libresoc.v:197811.3-197812.37"
wire $0\sv_changed[0:0]
- attribute \src "libresoc.v:199383.3-199398.6"
+ attribute \src "libresoc.v:199279.3-199294.6"
wire width 64 $0\svstate[63:0]
- attribute \src "libresoc.v:199374.3-199382.6"
- wire $0\svstate_ok_delay$next[0:0]$13654
- attribute \src "libresoc.v:197949.3-197950.49"
+ attribute \src "libresoc.v:199270.3-199278.6"
+ wire $0\svstate_ok_delay$next[0:0]$13446
+ attribute \src "libresoc.v:197845.3-197846.49"
wire $0\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:200328.3-200400.6"
+ attribute \src "libresoc.v:200224.3-200296.6"
wire $0\update_svstate[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $10\issue_fsm_state$next[2:0]$13752
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $11\issue_fsm_state$next[2:0]$13753
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $12\issue_fsm_state$next[2:0]$13754
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $1\core_asmcode$next[7:0]$13841
- attribute \src "libresoc.v:195626.13-195626.33"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $10\issue_fsm_state$next[2:0]$13544
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $11\issue_fsm_state$next[2:0]$13545
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $12\issue_fsm_state$next[2:0]$13546
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $1\core_asmcode$next[7:0]$13633
+ attribute \src "libresoc.v:195522.13-195522.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:198598.3-198642.6"
- wire $1\core_bigendian_i$10$next[0:0]$13578
- attribute \src "libresoc.v:199361.3-199373.6"
+ attribute \src "libresoc.v:198494.3-198538.6"
+ wire $1\core_bigendian_i$10$next[0:0]$13370
+ attribute \src "libresoc.v:199257.3-199269.6"
wire width 3 $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $1\core_core_core_cia$next[63:0]$13842
- attribute \src "libresoc.v:195640.14-195640.55"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $1\core_core_core_cia$next[63:0]$13634
+ attribute \src "libresoc.v:195536.14-195536.55"
wire width 64 $1\core_core_core_cia[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $1\core_core_core_cr_rd$next[7:0]$13843
- attribute \src "libresoc.v:195644.13-195644.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $1\core_core_core_cr_rd$next[7:0]$13635
+ attribute \src "libresoc.v:195540.13-195540.41"
wire width 8 $1\core_core_core_cr_rd[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_cr_rd_ok$next[0:0]$13844
- attribute \src "libresoc.v:195648.7-195648.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_cr_rd_ok$next[0:0]$13636
+ attribute \src "libresoc.v:195544.7-195544.37"
wire $1\core_core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $1\core_core_core_cr_wr$next[7:0]$13845
- attribute \src "libresoc.v:195652.13-195652.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $1\core_core_core_cr_wr$next[7:0]$13637
+ attribute \src "libresoc.v:195548.13-195548.41"
wire width 8 $1\core_core_core_cr_wr[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$3$next[0:0]$13846
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$4$next[0:0]$13847
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$5$next[0:0]$13848
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$6$next[0:0]$13849
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$7$next[0:0]$13850
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$8$next[0:0]$13851
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$9$next[0:0]$13852
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_exc_$signal$next[0:0]$13853
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 14 $1\core_core_core_fn_unit$next[13:0]$13854
- attribute \src "libresoc.v:195703.14-195703.47"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$3$next[0:0]$13638
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$4$next[0:0]$13639
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$5$next[0:0]$13640
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$6$next[0:0]$13641
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$7$next[0:0]$13642
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$8$next[0:0]$13643
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$9$next[0:0]$13644
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_exc_$signal$next[0:0]$13645
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 14 $1\core_core_core_fn_unit$next[13:0]$13646
+ attribute \src "libresoc.v:195599.14-195599.47"
wire width 14 $1\core_core_core_fn_unit[13:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 2 $1\core_core_core_input_carry$next[1:0]$13855
- attribute \src "libresoc.v:195711.13-195711.46"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 2 $1\core_core_core_input_carry$next[1:0]$13647
+ attribute \src "libresoc.v:195607.13-195607.46"
wire width 2 $1\core_core_core_input_carry[1:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 32 $1\core_core_core_insn$next[31:0]$13856
- attribute \src "libresoc.v:195715.14-195715.41"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 32 $1\core_core_core_insn$next[31:0]$13648
+ attribute \src "libresoc.v:195611.14-195611.41"
wire width 32 $1\core_core_core_insn[31:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_core_insn_type$next[6:0]$13857
- attribute \src "libresoc.v:195794.13-195794.45"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_core_insn_type$next[6:0]$13649
+ attribute \src "libresoc.v:195690.13-195690.45"
wire width 7 $1\core_core_core_insn_type[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_is_32bit$next[0:0]$13858
- attribute \src "libresoc.v:195798.7-195798.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_is_32bit$next[0:0]$13650
+ attribute \src "libresoc.v:195694.7-195694.37"
wire $1\core_core_core_is_32bit[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $1\core_core_core_msr$next[63:0]$13859
- attribute \src "libresoc.v:195802.14-195802.55"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $1\core_core_core_msr$next[63:0]$13651
+ attribute \src "libresoc.v:195698.14-195698.55"
wire width 64 $1\core_core_core_msr[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_oe$next[0:0]$13860
- attribute \src "libresoc.v:195806.7-195806.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_oe$next[0:0]$13652
+ attribute \src "libresoc.v:195702.7-195702.31"
wire $1\core_core_core_oe[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_oe_ok$next[0:0]$13861
- attribute \src "libresoc.v:195810.7-195810.34"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_oe_ok$next[0:0]$13653
+ attribute \src "libresoc.v:195706.7-195706.34"
wire $1\core_core_core_oe_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_rc$next[0:0]$13862
- attribute \src "libresoc.v:195814.7-195814.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_rc$next[0:0]$13654
+ attribute \src "libresoc.v:195710.7-195710.31"
wire $1\core_core_core_rc[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_core_rc_ok$next[0:0]$13863
- attribute \src "libresoc.v:195818.7-195818.34"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_core_rc_ok$next[0:0]$13655
+ attribute \src "libresoc.v:195714.7-195714.34"
wire $1\core_core_core_rc_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 13 $1\core_core_core_trapaddr$next[12:0]$13864
- attribute \src "libresoc.v:195822.14-195822.48"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 13 $1\core_core_core_trapaddr$next[12:0]$13656
+ attribute \src "libresoc.v:195718.14-195718.48"
wire width 13 $1\core_core_core_trapaddr[12:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $1\core_core_core_traptype$next[7:0]$13865
- attribute \src "libresoc.v:195826.13-195826.44"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $1\core_core_core_traptype$next[7:0]$13657
+ attribute \src "libresoc.v:195722.13-195722.44"
wire width 8 $1\core_core_core_traptype[7:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_cr_in1$next[6:0]$13866
- attribute \src "libresoc.v:195830.13-195830.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_cr_in1$next[6:0]$13658
+ attribute \src "libresoc.v:195726.13-195726.37"
wire width 7 $1\core_core_cr_in1[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_cr_in1_ok$next[0:0]$13867
- attribute \src "libresoc.v:195834.7-195834.33"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_cr_in1_ok$next[0:0]$13659
+ attribute \src "libresoc.v:195730.7-195730.33"
wire $1\core_core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_cr_in2$1$next[6:0]$13868
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_cr_in2$next[6:0]$13869
- attribute \src "libresoc.v:195838.13-195838.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_cr_in2$1$next[6:0]$13660
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_cr_in2$next[6:0]$13661
+ attribute \src "libresoc.v:195734.13-195734.37"
wire width 7 $1\core_core_cr_in2[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_cr_in2_ok$2$next[0:0]$13870
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_cr_in2_ok$next[0:0]$13871
- attribute \src "libresoc.v:195846.7-195846.33"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_cr_in2_ok$2$next[0:0]$13662
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_cr_in2_ok$next[0:0]$13663
+ attribute \src "libresoc.v:195742.7-195742.33"
wire $1\core_core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_cr_out$next[6:0]$13872
- attribute \src "libresoc.v:195854.13-195854.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_cr_out$next[6:0]$13664
+ attribute \src "libresoc.v:195750.13-195750.37"
wire width 7 $1\core_core_cr_out[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_cr_wr_ok$next[0:0]$13873
- attribute \src "libresoc.v:195858.7-195858.32"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_cr_wr_ok$next[0:0]$13665
+ attribute \src "libresoc.v:195754.7-195754.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $1\core_core_dststep$next[6:0]$13541
- attribute \src "libresoc.v:195862.13-195862.38"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $1\core_core_dststep$next[6:0]$13333
+ attribute \src "libresoc.v:195758.13-195758.38"
wire width 7 $1\core_core_dststep[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_ea$next[6:0]$13874
- attribute \src "libresoc.v:195866.13-195866.33"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_ea$next[6:0]$13666
+ attribute \src "libresoc.v:195762.13-195762.33"
wire width 7 $1\core_core_ea[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $1\core_core_fast1$next[2:0]$13875
- attribute \src "libresoc.v:195870.13-195870.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $1\core_core_fast1$next[2:0]$13667
+ attribute \src "libresoc.v:195766.13-195766.35"
wire width 3 $1\core_core_fast1[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_fast1_ok$next[0:0]$13876
- attribute \src "libresoc.v:195874.7-195874.32"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_fast1_ok$next[0:0]$13668
+ attribute \src "libresoc.v:195770.7-195770.32"
wire $1\core_core_fast1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $1\core_core_fast2$next[2:0]$13877
- attribute \src "libresoc.v:195878.13-195878.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $1\core_core_fast2$next[2:0]$13669
+ attribute \src "libresoc.v:195774.13-195774.35"
wire width 3 $1\core_core_fast2[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_fast2_ok$next[0:0]$13878
- attribute \src "libresoc.v:195882.7-195882.32"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_fast2_ok$next[0:0]$13670
+ attribute \src "libresoc.v:195778.7-195778.32"
wire $1\core_core_fast2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $1\core_core_fasto1$next[2:0]$13879
- attribute \src "libresoc.v:195886.13-195886.36"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $1\core_core_fasto1$next[2:0]$13671
+ attribute \src "libresoc.v:195782.13-195782.36"
wire width 3 $1\core_core_fasto1[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $1\core_core_fasto2$next[2:0]$13880
- attribute \src "libresoc.v:195890.13-195890.36"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $1\core_core_fasto2$next[2:0]$13672
+ attribute \src "libresoc.v:195786.13-195786.36"
wire width 3 $1\core_core_fasto2[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_lk$next[0:0]$13881
- attribute \src "libresoc.v:195894.7-195894.26"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_lk$next[0:0]$13673
+ attribute \src "libresoc.v:195790.7-195790.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $1\core_core_maxvl$next[6:0]$13542
- attribute \src "libresoc.v:195898.13-195898.36"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $1\core_core_maxvl$next[6:0]$13334
+ attribute \src "libresoc.v:195794.13-195794.36"
wire width 7 $1\core_core_maxvl[6:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $1\core_core_pc$next[63:0]$13543
- attribute \src "libresoc.v:195902.14-195902.49"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $1\core_core_pc$next[63:0]$13335
+ attribute \src "libresoc.v:195798.14-195798.49"
wire width 64 $1\core_core_pc[63:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_reg1$next[6:0]$13882
- attribute \src "libresoc.v:195906.13-195906.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_reg1$next[6:0]$13674
+ attribute \src "libresoc.v:195802.13-195802.35"
wire width 7 $1\core_core_reg1[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_reg1_ok$next[0:0]$13883
- attribute \src "libresoc.v:195910.7-195910.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_reg1_ok$next[0:0]$13675
+ attribute \src "libresoc.v:195806.7-195806.31"
wire $1\core_core_reg1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_reg2$next[6:0]$13884
- attribute \src "libresoc.v:195914.13-195914.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_reg2$next[6:0]$13676
+ attribute \src "libresoc.v:195810.13-195810.35"
wire width 7 $1\core_core_reg2[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_reg2_ok$next[0:0]$13885
- attribute \src "libresoc.v:195918.7-195918.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_reg2_ok$next[0:0]$13677
+ attribute \src "libresoc.v:195814.7-195814.31"
wire $1\core_core_reg2_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_reg3$next[6:0]$13886
- attribute \src "libresoc.v:195922.13-195922.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_reg3$next[6:0]$13678
+ attribute \src "libresoc.v:195818.13-195818.35"
wire width 7 $1\core_core_reg3[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_reg3_ok$next[0:0]$13887
- attribute \src "libresoc.v:195926.7-195926.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_reg3_ok$next[0:0]$13679
+ attribute \src "libresoc.v:195822.7-195822.31"
wire $1\core_core_reg3_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $1\core_core_rego$next[6:0]$13888
- attribute \src "libresoc.v:195930.13-195930.35"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $1\core_core_rego$next[6:0]$13680
+ attribute \src "libresoc.v:195826.13-195826.35"
wire width 7 $1\core_core_rego[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $1\core_core_spr1$next[9:0]$13889
- attribute \src "libresoc.v:196048.13-196048.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $1\core_core_spr1$next[9:0]$13681
+ attribute \src "libresoc.v:195944.13-195944.37"
wire width 10 $1\core_core_spr1[9:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_core_spr1_ok$next[0:0]$13890
- attribute \src "libresoc.v:196052.7-196052.31"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_core_spr1_ok$next[0:0]$13682
+ attribute \src "libresoc.v:195948.7-195948.31"
wire $1\core_core_spr1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $1\core_core_spro$next[9:0]$13891
- attribute \src "libresoc.v:196170.13-196170.37"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $1\core_core_spro$next[9:0]$13683
+ attribute \src "libresoc.v:196066.13-196066.37"
wire width 10 $1\core_core_spro[9:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $1\core_core_srcstep$next[6:0]$13544
- attribute \src "libresoc.v:196174.13-196174.38"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $1\core_core_srcstep$next[6:0]$13336
+ attribute \src "libresoc.v:196070.13-196070.38"
wire width 7 $1\core_core_srcstep[6:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $1\core_core_subvl$next[1:0]$13545
- attribute \src "libresoc.v:196178.13-196178.35"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $1\core_core_subvl$next[1:0]$13337
+ attribute \src "libresoc.v:196074.13-196074.35"
wire width 2 $1\core_core_subvl[1:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $1\core_core_svstep$next[1:0]$13546
- attribute \src "libresoc.v:196182.13-196182.36"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $1\core_core_svstep$next[1:0]$13338
+ attribute \src "libresoc.v:196078.13-196078.36"
wire width 2 $1\core_core_svstep[1:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $1\core_core_vl$next[6:0]$13547
- attribute \src "libresoc.v:196188.13-196188.33"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $1\core_core_vl$next[6:0]$13339
+ attribute \src "libresoc.v:196084.13-196084.33"
wire width 7 $1\core_core_vl[6:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $1\core_core_xer_in$next[2:0]$13892
- attribute \src "libresoc.v:196192.13-196192.36"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $1\core_core_xer_in$next[2:0]$13684
+ attribute \src "libresoc.v:196088.13-196088.36"
wire width 3 $1\core_core_xer_in[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_cr_out_ok$next[0:0]$13893
- attribute \src "libresoc.v:196200.7-196200.28"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_cr_out_ok$next[0:0]$13685
+ attribute \src "libresoc.v:196096.7-196096.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:198890.3-198899.6"
- wire width 64 $1\core_data_i$12[63:0]$13597
- attribute \src "libresoc.v:199492.3-199571.6"
+ attribute \src "libresoc.v:198786.3-198795.6"
+ wire width 64 $1\core_data_i$12[63:0]$13389
+ attribute \src "libresoc.v:199388.3-199467.6"
wire width 64 $1\core_data_i[63:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $1\core_dec$next[63:0]$13548
- attribute \src "libresoc.v:196216.14-196216.45"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $1\core_dec$next[63:0]$13340
+ attribute \src "libresoc.v:196112.14-196112.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:199007.3-199016.6"
+ attribute \src "libresoc.v:198903.3-198912.6"
wire width 5 $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:199017.3-199026.6"
+ attribute \src "libresoc.v:198913.3-198922.6"
wire $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_ea_ok$next[0:0]$13894
- attribute \src "libresoc.v:196226.7-196226.24"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_ea_ok$next[0:0]$13686
+ attribute \src "libresoc.v:196122.7-196122.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire $1\core_eint$next[0:0]$13549
- attribute \src "libresoc.v:196230.7-196230.23"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire $1\core_eint$next[0:0]$13341
+ attribute \src "libresoc.v:196126.7-196126.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_fasto1_ok$next[0:0]$13895
- attribute \src "libresoc.v:196234.7-196234.28"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_fasto1_ok$next[0:0]$13687
+ attribute \src "libresoc.v:196130.7-196130.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_fasto2_ok$next[0:0]$13896
- attribute \src "libresoc.v:196238.7-196238.28"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_fasto2_ok$next[0:0]$13688
+ attribute \src "libresoc.v:196134.7-196134.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:199056.3-199065.6"
+ attribute \src "libresoc.v:198952.3-198961.6"
wire width 8 $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:199095.3-199104.6"
+ attribute \src "libresoc.v:198991.3-199000.6"
wire width 3 $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:199215.3-199237.6"
- wire width 3 $1\core_issue__addr$13[2:0]$13637
- attribute \src "libresoc.v:199134.3-199152.6"
+ attribute \src "libresoc.v:199111.3-199133.6"
+ wire width 3 $1\core_issue__addr$13[2:0]$13429
+ attribute \src "libresoc.v:199030.3-199048.6"
wire width 3 $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:199261.3-199283.6"
+ attribute \src "libresoc.v:199157.3-199179.6"
wire width 64 $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:199153.3-199171.6"
+ attribute \src "libresoc.v:199049.3-199067.6"
wire $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:199238.3-199260.6"
+ attribute \src "libresoc.v:199134.3-199156.6"
wire $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:198936.3-198951.6"
+ attribute \src "libresoc.v:198832.3-198847.6"
wire $1\core_issue_i[0:0]
- attribute \src "libresoc.v:198911.3-198935.6"
+ attribute \src "libresoc.v:198807.3-198831.6"
wire $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $1\core_msr$next[63:0]$13550
- attribute \src "libresoc.v:196266.14-196266.45"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $1\core_msr$next[63:0]$13342
+ attribute \src "libresoc.v:196162.14-196162.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:199572.3-199587.6"
+ attribute \src "libresoc.v:199468.3-199483.6"
wire width 3 $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:198573.3-198597.6"
- wire width 32 $1\core_raw_insn_i$next[31:0]$13573
- attribute \src "libresoc.v:196274.14-196274.37"
+ attribute \src "libresoc.v:198469.3-198493.6"
+ wire width 32 $1\core_raw_insn_i$next[31:0]$13365
+ attribute \src "libresoc.v:196170.14-196170.37"
wire width 32 $1\core_raw_insn_i[31:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_rego_ok$next[0:0]$13897
- attribute \src "libresoc.v:196278.7-196278.26"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_rego_ok$next[0:0]$13689
+ attribute \src "libresoc.v:196174.7-196174.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_spro_ok$next[0:0]$13898
- attribute \src "libresoc.v:196282.7-196282.26"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_spro_ok$next[0:0]$13690
+ attribute \src "libresoc.v:196178.7-196178.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:200151.3-200197.6"
+ attribute \src "libresoc.v:200047.3-200093.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:199399.3-199411.6"
+ attribute \src "libresoc.v:199295.3-199307.6"
wire width 3 $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:198643.3-198687.6"
- wire $1\core_sv_a_nz$next[0:0]$13583
- attribute \src "libresoc.v:196294.7-196294.26"
+ attribute \src "libresoc.v:198539.3-198583.6"
+ wire $1\core_sv_a_nz$next[0:0]$13375
+ attribute \src "libresoc.v:196190.7-196190.26"
wire $1\core_sv_a_nz[0:0]
- attribute \src "libresoc.v:198880.3-198889.6"
- wire width 3 $1\core_wen$11[2:0]$13594
- attribute \src "libresoc.v:199412.3-199491.6"
+ attribute \src "libresoc.v:198776.3-198785.6"
+ wire width 3 $1\core_wen$11[2:0]$13386
+ attribute \src "libresoc.v:199308.3-199387.6"
wire width 3 $1\core_wen[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $1\core_xer_out$next[0:0]$13899
- attribute \src "libresoc.v:196304.7-196304.26"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $1\core_xer_out$next[0:0]$13691
+ attribute \src "libresoc.v:196200.7-196200.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:196310.7-196310.30"
+ attribute \src "libresoc.v:196206.7-196206.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $1\cur_cur_dststep$next[6:0]$13683
- attribute \src "libresoc.v:196316.13-196316.36"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $1\cur_cur_dststep$next[6:0]$13475
+ attribute \src "libresoc.v:196212.13-196212.36"
wire width 7 $1\cur_cur_dststep[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $1\cur_cur_maxvl$next[6:0]$13684
- attribute \src "libresoc.v:196320.13-196320.34"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $1\cur_cur_maxvl$next[6:0]$13476
+ attribute \src "libresoc.v:196216.13-196216.34"
wire width 7 $1\cur_cur_maxvl[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $1\cur_cur_srcstep$next[6:0]$13685
- attribute \src "libresoc.v:196324.13-196324.36"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $1\cur_cur_srcstep$next[6:0]$13477
+ attribute \src "libresoc.v:196220.13-196220.36"
wire width 7 $1\cur_cur_srcstep[6:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $1\cur_cur_subvl$next[1:0]$13686
- attribute \src "libresoc.v:196328.13-196328.33"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $1\cur_cur_subvl$next[1:0]$13478
+ attribute \src "libresoc.v:196224.13-196224.33"
wire width 2 $1\cur_cur_subvl[1:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $1\cur_cur_svstep$next[1:0]$13687
- attribute \src "libresoc.v:196332.13-196332.34"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $1\cur_cur_svstep$next[1:0]$13479
+ attribute \src "libresoc.v:196228.13-196228.34"
wire width 2 $1\cur_cur_svstep[1:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $1\cur_cur_vl$next[6:0]$13688
- attribute \src "libresoc.v:196336.13-196336.31"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $1\cur_cur_vl$next[6:0]$13480
+ attribute \src "libresoc.v:196232.13-196232.31"
wire width 7 $1\cur_cur_vl[6:0]
- attribute \src "libresoc.v:199066.3-199074.6"
- wire $1\d_cr_delay$next[0:0]$13619
- attribute \src "libresoc.v:196340.7-196340.24"
+ attribute \src "libresoc.v:198962.3-198970.6"
+ wire $1\d_cr_delay$next[0:0]$13411
+ attribute \src "libresoc.v:196236.7-196236.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:199027.3-199035.6"
- wire $1\d_reg_delay$next[0:0]$13613
- attribute \src "libresoc.v:196344.7-196344.25"
+ attribute \src "libresoc.v:198923.3-198931.6"
+ wire $1\d_reg_delay$next[0:0]$13405
+ attribute \src "libresoc.v:196240.7-196240.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:199105.3-199113.6"
- wire $1\d_xer_delay$next[0:0]$13625
- attribute \src "libresoc.v:196348.7-196348.25"
+ attribute \src "libresoc.v:199001.3-199009.6"
+ wire $1\d_xer_delay$next[0:0]$13417
+ attribute \src "libresoc.v:196244.7-196244.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:200198.3-200244.6"
+ attribute \src "libresoc.v:200094.3-200140.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:199085.3-199094.6"
+ attribute \src "libresoc.v:198981.3-198990.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:199075.3-199084.6"
+ attribute \src "libresoc.v:198971.3-198980.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:199046.3-199055.6"
+ attribute \src "libresoc.v:198942.3-198951.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:199036.3-199045.6"
+ attribute \src "libresoc.v:198932.3-198941.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:199124.3-199133.6"
+ attribute \src "libresoc.v:199020.3-199029.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:199114.3-199123.6"
+ attribute \src "libresoc.v:199010.3-199019.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:198490.3-198498.6"
- wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13526
- attribute \src "libresoc.v:196396.13-196396.34"
+ attribute \src "libresoc.v:198386.3-198394.6"
+ wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13318
+ attribute \src "libresoc.v:196292.13-196292.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:199588.3-199596.6"
- wire width 64 $1\dbg_dmi_din$next[63:0]$13663
- attribute \src "libresoc.v:196400.14-196400.48"
+ attribute \src "libresoc.v:199484.3-199492.6"
+ wire width 64 $1\dbg_dmi_din$next[63:0]$13455
+ attribute \src "libresoc.v:196296.14-196296.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:198499.3-198507.6"
- wire $1\dbg_dmi_req_i$next[0:0]$13529
- attribute \src "libresoc.v:196406.7-196406.27"
+ attribute \src "libresoc.v:198395.3-198403.6"
+ wire $1\dbg_dmi_req_i$next[0:0]$13321
+ attribute \src "libresoc.v:196302.7-196302.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:199327.3-199335.6"
- wire $1\dbg_dmi_we_i$next[0:0]$13647
- attribute \src "libresoc.v:196410.7-196410.26"
+ attribute \src "libresoc.v:199223.3-199231.6"
+ wire $1\dbg_dmi_we_i$next[0:0]$13439
+ attribute \src "libresoc.v:196306.7-196306.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:199284.3-199303.6"
- wire width 64 $1\dec2_cur_dec$next[63:0]$13642
- attribute \src "libresoc.v:196464.14-196464.49"
+ attribute \src "libresoc.v:199180.3-199199.6"
+ wire width 64 $1\dec2_cur_dec$next[63:0]$13434
+ attribute \src "libresoc.v:196360.14-196360.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:200630.3-200638.6"
- wire $1\dec2_cur_eint$next[0:0]$13988
- attribute \src "libresoc.v:196468.7-196468.27"
+ attribute \src "libresoc.v:200526.3-200534.6"
+ wire $1\dec2_cur_eint$next[0:0]$13780
+ attribute \src "libresoc.v:196364.7-196364.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:199854.3-199878.6"
- wire width 64 $1\dec2_cur_msr$next[63:0]$13726
- attribute \src "libresoc.v:196472.14-196472.49"
+ attribute \src "libresoc.v:199750.3-199774.6"
+ wire width 64 $1\dec2_cur_msr$next[63:0]$13518
+ attribute \src "libresoc.v:196368.14-196368.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:199701.3-199721.6"
- wire width 64 $1\dec2_cur_pc$next[63:0]$13673
- attribute \src "libresoc.v:196476.14-196476.48"
+ attribute \src "libresoc.v:199597.3-199617.6"
+ wire width 64 $1\dec2_cur_pc$next[63:0]$13465
+ attribute \src "libresoc.v:196372.14-196372.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:199902.3-199936.6"
- wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13735
- attribute \src "libresoc.v:196628.14-196628.40"
+ attribute \src "libresoc.v:199798.3-199832.6"
+ wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13527
+ attribute \src "libresoc.v:196524.14-196524.40"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:200639.3-200648.6"
- wire width 2 $1\delay$next[1:0]$13991
- attribute \src "libresoc.v:196898.13-196898.25"
+ attribute \src "libresoc.v:200535.3-200544.6"
+ wire width 2 $1\delay$next[1:0]$13783
+ attribute \src "libresoc.v:196794.13-196794.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:198952.3-198986.6"
- wire $1\exec_fsm_state$next[0:0]$13603
- attribute \src "libresoc.v:196914.7-196914.28"
+ attribute \src "libresoc.v:198848.3-198882.6"
+ wire $1\exec_fsm_state$next[0:0]$13395
+ attribute \src "libresoc.v:196810.7-196810.28"
wire $1\exec_fsm_state[0:0]
- attribute \src "libresoc.v:198900.3-198910.6"
+ attribute \src "libresoc.v:198796.3-198806.6"
wire $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:198776.3-198802.6"
+ attribute \src "libresoc.v:198672.3-198698.6"
wire $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:198803.3-198838.6"
+ attribute \src "libresoc.v:198699.3-198734.6"
wire $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:198987.3-199006.6"
+ attribute \src "libresoc.v:198883.3-198902.6"
wire $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:199800.3-199853.6"
- wire width 2 $1\fetch_fsm_state$next[1:0]$13718
- attribute \src "libresoc.v:196926.13-196926.35"
+ attribute \src "libresoc.v:199696.3-199749.6"
+ wire width 2 $1\fetch_fsm_state$next[1:0]$13510
+ attribute \src "libresoc.v:196822.13-196822.35"
wire width 2 $1\fetch_fsm_state[1:0]
- attribute \src "libresoc.v:200484.3-200498.6"
+ attribute \src "libresoc.v:200380.3-200394.6"
wire $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:199937.3-199959.6"
+ attribute \src "libresoc.v:199833.3-199855.6"
wire $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:199597.3-199607.6"
+ attribute \src "libresoc.v:199493.3-199503.6"
wire $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:200036.3-200051.6"
+ attribute \src "libresoc.v:199932.3-199947.6"
wire $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:199172.3-199199.6"
- wire width 2 $1\fsm_state$next[1:0]$13632
- attribute \src "libresoc.v:196938.13-196938.29"
+ attribute \src "libresoc.v:199068.3-199095.6"
+ wire width 2 $1\fsm_state$next[1:0]$13424
+ attribute \src "libresoc.v:196834.13-196834.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:199608.3-199623.6"
+ attribute \src "libresoc.v:199504.3-199519.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:199633.3-199666.6"
+ attribute \src "libresoc.v:199529.3-199562.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199667.3-199700.6"
+ attribute \src "libresoc.v:199563.3-199596.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:198688.3-198733.6"
+ attribute \src "libresoc.v:198584.3-198629.6"
wire $1\insn_done[0:0]
- attribute \src "libresoc.v:198839.3-198879.6"
+ attribute \src "libresoc.v:198735.3-198775.6"
wire $1\is_last[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $1\issue_fsm_state$next[2:0]$13743
- attribute \src "libresoc.v:197198.13-197198.35"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $1\issue_fsm_state$next[2:0]$13535
+ attribute \src "libresoc.v:197094.13-197094.35"
wire width 3 $1\issue_fsm_state[2:0]
- attribute \src "libresoc.v:199624.3-199632.6"
- wire $1\jtag_dmi0__ack_o$next[0:0]$13668
- attribute \src "libresoc.v:197202.7-197202.30"
+ attribute \src "libresoc.v:199520.3-199528.6"
+ wire $1\jtag_dmi0__ack_o$next[0:0]$13460
+ attribute \src "libresoc.v:197098.7-197098.30"
wire $1\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:199791.3-199799.6"
- wire width 64 $1\jtag_dmi0__dout$next[63:0]$13715
- attribute \src "libresoc.v:197210.14-197210.52"
+ attribute \src "libresoc.v:199687.3-199695.6"
+ wire width 64 $1\jtag_dmi0__dout$next[63:0]$13507
+ attribute \src "libresoc.v:197106.14-197106.52"
wire width 64 $1\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:199761.3-199790.6"
- wire $1\msr_read$next[0:0]$13709
- attribute \src "libresoc.v:197250.7-197250.22"
+ attribute \src "libresoc.v:199657.3-199686.6"
+ wire $1\msr_read$next[0:0]$13501
+ attribute \src "libresoc.v:197146.7-197146.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:199200.3-199214.6"
+ attribute \src "libresoc.v:199096.3-199110.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $1\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $1\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $1\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $1\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $1\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $1\new_svstate_vl[6:0]
- attribute \src "libresoc.v:199304.3-199326.6"
+ attribute \src "libresoc.v:199200.3-199222.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:199879.3-199901.6"
- wire width 64 $1\nia$next[63:0]$13731
- attribute \src "libresoc.v:197290.14-197290.40"
+ attribute \src "libresoc.v:199775.3-199797.6"
+ wire width 64 $1\nia$next[63:0]$13523
+ attribute \src "libresoc.v:197186.14-197186.40"
wire width 64 $1\nia[63:0]
- attribute \src "libresoc.v:199345.3-199360.6"
+ attribute \src "libresoc.v:199241.3-199256.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:200245.3-200327.6"
- wire $1\pc_changed$next[0:0]$13759
- attribute \src "libresoc.v:197296.7-197296.24"
+ attribute \src "libresoc.v:200141.3-200223.6"
+ wire $1\pc_changed$next[0:0]$13551
+ attribute \src "libresoc.v:197192.7-197192.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:199336.3-199344.6"
- wire $1\pc_ok_delay$next[0:0]$13650
- attribute \src "libresoc.v:197306.7-197306.25"
+ attribute \src "libresoc.v:199232.3-199240.6"
+ wire $1\pc_ok_delay$next[0:0]$13442
+ attribute \src "libresoc.v:197202.7-197202.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:198734.3-198752.6"
+ attribute \src "libresoc.v:198630.3-198648.6"
wire $1\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:198753.3-198775.6"
+ attribute \src "libresoc.v:198649.3-198671.6"
wire $1\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:200401.3-200483.6"
- wire $1\sv_changed$next[0:0]$13771
- attribute \src "libresoc.v:197606.7-197606.24"
+ attribute \src "libresoc.v:200297.3-200379.6"
+ wire $1\sv_changed$next[0:0]$13563
+ attribute \src "libresoc.v:197502.7-197502.24"
wire $1\sv_changed[0:0]
- attribute \src "libresoc.v:199383.3-199398.6"
+ attribute \src "libresoc.v:199279.3-199294.6"
wire width 64 $1\svstate[63:0]
- attribute \src "libresoc.v:199374.3-199382.6"
- wire $1\svstate_ok_delay$next[0:0]$13655
- attribute \src "libresoc.v:197616.7-197616.30"
+ attribute \src "libresoc.v:199270.3-199278.6"
+ wire $1\svstate_ok_delay$next[0:0]$13447
+ attribute \src "libresoc.v:197512.7-197512.30"
wire $1\svstate_ok_delay[0:0]
- attribute \src "libresoc.v:200328.3-200400.6"
+ attribute \src "libresoc.v:200224.3-200296.6"
wire $1\update_svstate[0:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $2\core_asmcode$next[7:0]$13900
- attribute \src "libresoc.v:198598.3-198642.6"
- wire $2\core_bigendian_i$10$next[0:0]$13579
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $2\core_core_core_cia$next[63:0]$13901
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $2\core_core_core_cr_rd$next[7:0]$13902
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_cr_rd_ok$next[0:0]$13903
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $2\core_core_core_cr_wr$next[7:0]$13904
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$3$next[0:0]$13905
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$4$next[0:0]$13906
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$5$next[0:0]$13907
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$6$next[0:0]$13908
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$7$next[0:0]$13909
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$8$next[0:0]$13910
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$9$next[0:0]$13911
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_exc_$signal$next[0:0]$13912
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 14 $2\core_core_core_fn_unit$next[13:0]$13913
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 2 $2\core_core_core_input_carry$next[1:0]$13914
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 32 $2\core_core_core_insn$next[31:0]$13915
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_core_insn_type$next[6:0]$13916
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_is_32bit$next[0:0]$13917
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 64 $2\core_core_core_msr$next[63:0]$13918
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_oe$next[0:0]$13919
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_oe_ok$next[0:0]$13920
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_rc$next[0:0]$13921
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_core_rc_ok$next[0:0]$13922
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 13 $2\core_core_core_trapaddr$next[12:0]$13923
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 8 $2\core_core_core_traptype$next[7:0]$13924
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_cr_in1$next[6:0]$13925
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_cr_in1_ok$next[0:0]$13926
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_cr_in2$1$next[6:0]$13927
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_cr_in2$next[6:0]$13928
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_cr_in2_ok$2$next[0:0]$13929
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_cr_in2_ok$next[0:0]$13930
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_cr_out$next[6:0]$13931
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_cr_wr_ok$next[0:0]$13932
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $2\core_core_dststep$next[6:0]$13551
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_ea$next[6:0]$13933
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $2\core_core_fast1$next[2:0]$13934
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_fast1_ok$next[0:0]$13935
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $2\core_core_fast2$next[2:0]$13936
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_fast2_ok$next[0:0]$13937
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $2\core_core_fasto1$next[2:0]$13938
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $2\core_core_fasto2$next[2:0]$13939
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_lk$next[0:0]$13940
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $2\core_core_maxvl$next[6:0]$13552
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $2\core_core_pc$next[63:0]$13553
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_reg1$next[6:0]$13941
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_reg1_ok$next[0:0]$13942
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_reg2$next[6:0]$13943
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_reg2_ok$next[0:0]$13944
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_reg3$next[6:0]$13945
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_reg3_ok$next[0:0]$13946
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 7 $2\core_core_rego$next[6:0]$13947
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $2\core_core_spr1$next[9:0]$13948
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_core_spr1_ok$next[0:0]$13949
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 10 $2\core_core_spro$next[9:0]$13950
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $2\core_core_srcstep$next[6:0]$13554
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $2\core_core_subvl$next[1:0]$13555
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $2\core_core_svstep$next[1:0]$13556
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $2\core_core_vl$next[6:0]$13557
- attribute \src "libresoc.v:200499.3-200629.6"
- wire width 3 $2\core_core_xer_in$next[2:0]$13951
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_cr_out_ok$next[0:0]$13952
- attribute \src "libresoc.v:199492.3-199571.6"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $2\core_asmcode$next[7:0]$13692
+ attribute \src "libresoc.v:198494.3-198538.6"
+ wire $2\core_bigendian_i$10$next[0:0]$13371
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $2\core_core_core_cia$next[63:0]$13693
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $2\core_core_core_cr_rd$next[7:0]$13694
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_cr_rd_ok$next[0:0]$13695
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $2\core_core_core_cr_wr$next[7:0]$13696
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$3$next[0:0]$13697
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$4$next[0:0]$13698
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$5$next[0:0]$13699
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$6$next[0:0]$13700
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$7$next[0:0]$13701
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$8$next[0:0]$13702
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$9$next[0:0]$13703
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_exc_$signal$next[0:0]$13704
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 14 $2\core_core_core_fn_unit$next[13:0]$13705
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 2 $2\core_core_core_input_carry$next[1:0]$13706
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 32 $2\core_core_core_insn$next[31:0]$13707
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_core_insn_type$next[6:0]$13708
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_is_32bit$next[0:0]$13709
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 64 $2\core_core_core_msr$next[63:0]$13710
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_oe$next[0:0]$13711
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_oe_ok$next[0:0]$13712
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_rc$next[0:0]$13713
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_core_rc_ok$next[0:0]$13714
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 13 $2\core_core_core_trapaddr$next[12:0]$13715
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 8 $2\core_core_core_traptype$next[7:0]$13716
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_cr_in1$next[6:0]$13717
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_cr_in1_ok$next[0:0]$13718
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_cr_in2$1$next[6:0]$13719
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_cr_in2$next[6:0]$13720
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_cr_in2_ok$2$next[0:0]$13721
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_cr_in2_ok$next[0:0]$13722
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_cr_out$next[6:0]$13723
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_cr_wr_ok$next[0:0]$13724
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $2\core_core_dststep$next[6:0]$13343
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_ea$next[6:0]$13725
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $2\core_core_fast1$next[2:0]$13726
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_fast1_ok$next[0:0]$13727
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $2\core_core_fast2$next[2:0]$13728
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_fast2_ok$next[0:0]$13729
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $2\core_core_fasto1$next[2:0]$13730
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $2\core_core_fasto2$next[2:0]$13731
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_lk$next[0:0]$13732
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $2\core_core_maxvl$next[6:0]$13344
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $2\core_core_pc$next[63:0]$13345
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_reg1$next[6:0]$13733
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_reg1_ok$next[0:0]$13734
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_reg2$next[6:0]$13735
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_reg2_ok$next[0:0]$13736
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_reg3$next[6:0]$13737
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_reg3_ok$next[0:0]$13738
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 7 $2\core_core_rego$next[6:0]$13739
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $2\core_core_spr1$next[9:0]$13740
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_core_spr1_ok$next[0:0]$13741
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 10 $2\core_core_spro$next[9:0]$13742
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $2\core_core_srcstep$next[6:0]$13346
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $2\core_core_subvl$next[1:0]$13347
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $2\core_core_svstep$next[1:0]$13348
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $2\core_core_vl$next[6:0]$13349
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire width 3 $2\core_core_xer_in$next[2:0]$13743
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_cr_out_ok$next[0:0]$13744
+ attribute \src "libresoc.v:199388.3-199467.6"
wire width 64 $2\core_data_i[63:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $2\core_dec$next[63:0]$13558
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_ea_ok$next[0:0]$13953
- attribute \src "libresoc.v:198508.3-198572.6"
- wire $2\core_eint$next[0:0]$13559
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_fasto1_ok$next[0:0]$13954
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_fasto2_ok$next[0:0]$13955
- attribute \src "libresoc.v:198936.3-198951.6"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $2\core_dec$next[63:0]$13350
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_ea_ok$next[0:0]$13745
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire $2\core_eint$next[0:0]$13351
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_fasto1_ok$next[0:0]$13746
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_fasto2_ok$next[0:0]$13747
+ attribute \src "libresoc.v:198832.3-198847.6"
wire $2\core_issue_i[0:0]
- attribute \src "libresoc.v:198911.3-198935.6"
+ attribute \src "libresoc.v:198807.3-198831.6"
wire $2\core_ivalid_i[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $2\core_msr$next[63:0]$13560
- attribute \src "libresoc.v:199572.3-199587.6"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $2\core_msr$next[63:0]$13352
+ attribute \src "libresoc.v:199468.3-199483.6"
wire width 3 $2\core_msr__ren[2:0]
- attribute \src "libresoc.v:198573.3-198597.6"
- wire width 32 $2\core_raw_insn_i$next[31:0]$13574
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_rego_ok$next[0:0]$13956
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_spro_ok$next[0:0]$13957
- attribute \src "libresoc.v:200151.3-200197.6"
+ attribute \src "libresoc.v:198469.3-198493.6"
+ wire width 32 $2\core_raw_insn_i$next[31:0]$13366
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_rego_ok$next[0:0]$13748
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_spro_ok$next[0:0]$13749
+ attribute \src "libresoc.v:200047.3-200093.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:198643.3-198687.6"
- wire $2\core_sv_a_nz$next[0:0]$13584
- attribute \src "libresoc.v:199412.3-199491.6"
+ attribute \src "libresoc.v:198539.3-198583.6"
+ wire $2\core_sv_a_nz$next[0:0]$13376
+ attribute \src "libresoc.v:199308.3-199387.6"
wire width 3 $2\core_wen[2:0]
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $2\core_xer_out$next[0:0]$13958
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $2\cur_cur_dststep$next[6:0]$13689
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $2\cur_cur_maxvl$next[6:0]$13690
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $2\cur_cur_srcstep$next[6:0]$13691
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $2\cur_cur_subvl$next[1:0]$13692
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $2\cur_cur_svstep$next[1:0]$13693
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $2\cur_cur_vl$next[6:0]$13694
- attribute \src "libresoc.v:200198.3-200244.6"
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $2\core_xer_out$next[0:0]$13750
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $2\cur_cur_dststep$next[6:0]$13481
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $2\cur_cur_maxvl$next[6:0]$13482
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $2\cur_cur_srcstep$next[6:0]$13483
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $2\cur_cur_subvl$next[1:0]$13484
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $2\cur_cur_svstep$next[1:0]$13485
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $2\cur_cur_vl$next[6:0]$13486
+ attribute \src "libresoc.v:200094.3-200140.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:199284.3-199303.6"
- wire width 64 $2\dec2_cur_dec$next[63:0]$13643
- attribute \src "libresoc.v:199854.3-199878.6"
- wire width 64 $2\dec2_cur_msr$next[63:0]$13727
- attribute \src "libresoc.v:199701.3-199721.6"
- wire width 64 $2\dec2_cur_pc$next[63:0]$13674
- attribute \src "libresoc.v:199902.3-199936.6"
- wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13736
- attribute \src "libresoc.v:198952.3-198986.6"
- wire $2\exec_fsm_state$next[0:0]$13604
- attribute \src "libresoc.v:198803.3-198838.6"
+ attribute \src "libresoc.v:199180.3-199199.6"
+ wire width 64 $2\dec2_cur_dec$next[63:0]$13435
+ attribute \src "libresoc.v:199750.3-199774.6"
+ wire width 64 $2\dec2_cur_msr$next[63:0]$13519
+ attribute \src "libresoc.v:199597.3-199617.6"
+ wire width 64 $2\dec2_cur_pc$next[63:0]$13466
+ attribute \src "libresoc.v:199798.3-199832.6"
+ wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13528
+ attribute \src "libresoc.v:198848.3-198882.6"
+ wire $2\exec_fsm_state$next[0:0]$13396
+ attribute \src "libresoc.v:198699.3-198734.6"
wire $2\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:198987.3-199006.6"
+ attribute \src "libresoc.v:198883.3-198902.6"
wire $2\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:199800.3-199853.6"
- wire width 2 $2\fetch_fsm_state$next[1:0]$13719
- attribute \src "libresoc.v:200036.3-200051.6"
+ attribute \src "libresoc.v:199696.3-199749.6"
+ wire width 2 $2\fetch_fsm_state$next[1:0]$13511
+ attribute \src "libresoc.v:199932.3-199947.6"
wire $2\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:199172.3-199199.6"
- wire width 2 $2\fsm_state$next[1:0]$13633
- attribute \src "libresoc.v:199608.3-199623.6"
+ attribute \src "libresoc.v:199068.3-199095.6"
+ wire width 2 $2\fsm_state$next[1:0]$13425
+ attribute \src "libresoc.v:199504.3-199519.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:199633.3-199666.6"
+ attribute \src "libresoc.v:199529.3-199562.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199667.3-199700.6"
+ attribute \src "libresoc.v:199563.3-199596.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:198688.3-198733.6"
+ attribute \src "libresoc.v:198584.3-198629.6"
wire $2\insn_done[0:0]
- attribute \src "libresoc.v:198839.3-198879.6"
+ attribute \src "libresoc.v:198735.3-198775.6"
wire $2\is_last[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $2\issue_fsm_state$next[2:0]$13744
- attribute \src "libresoc.v:199761.3-199790.6"
- wire $2\msr_read$next[0:0]$13710
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $2\issue_fsm_state$next[2:0]$13536
+ attribute \src "libresoc.v:199657.3-199686.6"
+ wire $2\msr_read$next[0:0]$13502
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $2\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $2\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $2\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $2\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $2\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $2\new_svstate_vl[6:0]
- attribute \src "libresoc.v:199879.3-199901.6"
- wire width 64 $2\nia$next[63:0]$13732
- attribute \src "libresoc.v:199345.3-199360.6"
+ attribute \src "libresoc.v:199775.3-199797.6"
+ wire width 64 $2\nia$next[63:0]$13524
+ attribute \src "libresoc.v:199241.3-199256.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:200245.3-200327.6"
- wire $2\pc_changed$next[0:0]$13760
- attribute \src "libresoc.v:200401.3-200483.6"
- wire $2\sv_changed$next[0:0]$13772
- attribute \src "libresoc.v:199383.3-199398.6"
+ attribute \src "libresoc.v:200141.3-200223.6"
+ wire $2\pc_changed$next[0:0]$13552
+ attribute \src "libresoc.v:200297.3-200379.6"
+ wire $2\sv_changed$next[0:0]$13564
+ attribute \src "libresoc.v:199279.3-199294.6"
wire width 64 $2\svstate[63:0]
- attribute \src "libresoc.v:200328.3-200400.6"
+ attribute \src "libresoc.v:200224.3-200296.6"
wire $2\update_svstate[0:0]
- attribute \src "libresoc.v:198598.3-198642.6"
- wire $3\core_bigendian_i$10$next[0:0]$13580
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_cr_rd_ok$next[0:0]$13959
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$3$next[0:0]$13960
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$4$next[0:0]$13961
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$5$next[0:0]$13962
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$6$next[0:0]$13963
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$7$next[0:0]$13964
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$8$next[0:0]$13965
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$9$next[0:0]$13966
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_exc_$signal$next[0:0]$13967
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_oe_ok$next[0:0]$13968
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_core_rc_ok$next[0:0]$13969
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_cr_in1_ok$next[0:0]$13970
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_cr_in2_ok$2$next[0:0]$13971
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_cr_in2_ok$next[0:0]$13972
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_cr_wr_ok$next[0:0]$13973
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $3\core_core_dststep$next[6:0]$13561
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_fast1_ok$next[0:0]$13974
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_fast2_ok$next[0:0]$13975
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $3\core_core_maxvl$next[6:0]$13562
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $3\core_core_pc$next[63:0]$13563
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_reg1_ok$next[0:0]$13976
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_reg2_ok$next[0:0]$13977
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_reg3_ok$next[0:0]$13978
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_core_spr1_ok$next[0:0]$13979
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $3\core_core_srcstep$next[6:0]$13564
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $3\core_core_subvl$next[1:0]$13565
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 2 $3\core_core_svstep$next[1:0]$13566
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 7 $3\core_core_vl$next[6:0]$13567
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_cr_out_ok$next[0:0]$13980
- attribute \src "libresoc.v:199492.3-199571.6"
+ attribute \src "libresoc.v:198494.3-198538.6"
+ wire $3\core_bigendian_i$10$next[0:0]$13372
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_cr_rd_ok$next[0:0]$13751
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$3$next[0:0]$13752
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$4$next[0:0]$13753
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$5$next[0:0]$13754
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$6$next[0:0]$13755
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$7$next[0:0]$13756
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$8$next[0:0]$13757
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$9$next[0:0]$13758
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_exc_$signal$next[0:0]$13759
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_oe_ok$next[0:0]$13760
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_core_rc_ok$next[0:0]$13761
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_cr_in1_ok$next[0:0]$13762
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_cr_in2_ok$2$next[0:0]$13763
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_cr_in2_ok$next[0:0]$13764
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_cr_wr_ok$next[0:0]$13765
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $3\core_core_dststep$next[6:0]$13353
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_fast1_ok$next[0:0]$13766
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_fast2_ok$next[0:0]$13767
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $3\core_core_maxvl$next[6:0]$13354
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $3\core_core_pc$next[63:0]$13355
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_reg1_ok$next[0:0]$13768
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_reg2_ok$next[0:0]$13769
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_reg3_ok$next[0:0]$13770
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_core_spr1_ok$next[0:0]$13771
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $3\core_core_srcstep$next[6:0]$13356
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $3\core_core_subvl$next[1:0]$13357
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 2 $3\core_core_svstep$next[1:0]$13358
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 7 $3\core_core_vl$next[6:0]$13359
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_cr_out_ok$next[0:0]$13772
+ attribute \src "libresoc.v:199388.3-199467.6"
wire width 64 $3\core_data_i[63:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $3\core_dec$next[63:0]$13568
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_ea_ok$next[0:0]$13981
- attribute \src "libresoc.v:198508.3-198572.6"
- wire $3\core_eint$next[0:0]$13569
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_fasto1_ok$next[0:0]$13982
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_fasto2_ok$next[0:0]$13983
- attribute \src "libresoc.v:198911.3-198935.6"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $3\core_dec$next[63:0]$13360
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_ea_ok$next[0:0]$13773
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire $3\core_eint$next[0:0]$13361
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_fasto1_ok$next[0:0]$13774
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_fasto2_ok$next[0:0]$13775
+ attribute \src "libresoc.v:198807.3-198831.6"
wire $3\core_ivalid_i[0:0]
- attribute \src "libresoc.v:198508.3-198572.6"
- wire width 64 $3\core_msr$next[63:0]$13570
- attribute \src "libresoc.v:198573.3-198597.6"
- wire width 32 $3\core_raw_insn_i$next[31:0]$13575
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_rego_ok$next[0:0]$13984
- attribute \src "libresoc.v:200499.3-200629.6"
- wire $3\core_spro_ok$next[0:0]$13985
- attribute \src "libresoc.v:200151.3-200197.6"
+ attribute \src "libresoc.v:198404.3-198468.6"
+ wire width 64 $3\core_msr$next[63:0]$13362
+ attribute \src "libresoc.v:198469.3-198493.6"
+ wire width 32 $3\core_raw_insn_i$next[31:0]$13367
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_rego_ok$next[0:0]$13776
+ attribute \src "libresoc.v:200395.3-200525.6"
+ wire $3\core_spro_ok$next[0:0]$13777
+ attribute \src "libresoc.v:200047.3-200093.6"
wire $3\core_stopped_i[0:0]
- attribute \src "libresoc.v:198643.3-198687.6"
- wire $3\core_sv_a_nz$next[0:0]$13585
- attribute \src "libresoc.v:199412.3-199491.6"
+ attribute \src "libresoc.v:198539.3-198583.6"
+ wire $3\core_sv_a_nz$next[0:0]$13377
+ attribute \src "libresoc.v:199308.3-199387.6"
wire width 3 $3\core_wen[2:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $3\cur_cur_dststep$next[6:0]$13695
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $3\cur_cur_maxvl$next[6:0]$13696
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $3\cur_cur_srcstep$next[6:0]$13697
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $3\cur_cur_subvl$next[1:0]$13698
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $3\cur_cur_svstep$next[1:0]$13699
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $3\cur_cur_vl$next[6:0]$13700
- attribute \src "libresoc.v:200198.3-200244.6"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $3\cur_cur_dststep$next[6:0]$13487
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $3\cur_cur_maxvl$next[6:0]$13488
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $3\cur_cur_srcstep$next[6:0]$13489
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $3\cur_cur_subvl$next[1:0]$13490
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $3\cur_cur_svstep$next[1:0]$13491
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $3\cur_cur_vl$next[6:0]$13492
+ attribute \src "libresoc.v:200094.3-200140.6"
wire $3\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:199854.3-199878.6"
- wire width 64 $3\dec2_cur_msr$next[63:0]$13728
- attribute \src "libresoc.v:199701.3-199721.6"
- wire width 64 $3\dec2_cur_pc$next[63:0]$13675
- attribute \src "libresoc.v:199902.3-199936.6"
- wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13737
- attribute \src "libresoc.v:198952.3-198986.6"
- wire $3\exec_fsm_state$next[0:0]$13605
- attribute \src "libresoc.v:199800.3-199853.6"
- wire width 2 $3\fetch_fsm_state$next[1:0]$13720
- attribute \src "libresoc.v:199633.3-199666.6"
+ attribute \src "libresoc.v:199750.3-199774.6"
+ wire width 64 $3\dec2_cur_msr$next[63:0]$13520
+ attribute \src "libresoc.v:199597.3-199617.6"
+ wire width 64 $3\dec2_cur_pc$next[63:0]$13467
+ attribute \src "libresoc.v:199798.3-199832.6"
+ wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13529
+ attribute \src "libresoc.v:198848.3-198882.6"
+ wire $3\exec_fsm_state$next[0:0]$13397
+ attribute \src "libresoc.v:199696.3-199749.6"
+ wire width 2 $3\fetch_fsm_state$next[1:0]$13512
+ attribute \src "libresoc.v:199529.3-199562.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199667.3-199700.6"
+ attribute \src "libresoc.v:199563.3-199596.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:198688.3-198733.6"
+ attribute \src "libresoc.v:198584.3-198629.6"
wire $3\insn_done[0:0]
- attribute \src "libresoc.v:198839.3-198879.6"
+ attribute \src "libresoc.v:198735.3-198775.6"
wire $3\is_last[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $3\issue_fsm_state$next[2:0]$13745
- attribute \src "libresoc.v:199761.3-199790.6"
- wire $3\msr_read$next[0:0]$13711
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $3\issue_fsm_state$next[2:0]$13537
+ attribute \src "libresoc.v:199657.3-199686.6"
+ wire $3\msr_read$next[0:0]$13503
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $3\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $3\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $3\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $3\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $3\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $3\new_svstate_vl[6:0]
- attribute \src "libresoc.v:200245.3-200327.6"
- wire $3\pc_changed$next[0:0]$13761
- attribute \src "libresoc.v:200401.3-200483.6"
- wire $3\sv_changed$next[0:0]$13773
- attribute \src "libresoc.v:200328.3-200400.6"
+ attribute \src "libresoc.v:200141.3-200223.6"
+ wire $3\pc_changed$next[0:0]$13553
+ attribute \src "libresoc.v:200297.3-200379.6"
+ wire $3\sv_changed$next[0:0]$13565
+ attribute \src "libresoc.v:200224.3-200296.6"
wire $3\update_svstate[0:0]
- attribute \src "libresoc.v:199492.3-199571.6"
+ attribute \src "libresoc.v:199388.3-199467.6"
wire width 64 $4\core_data_i[63:0]
- attribute \src "libresoc.v:199412.3-199491.6"
+ attribute \src "libresoc.v:199308.3-199387.6"
wire width 3 $4\core_wen[2:0]
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $4\cur_cur_dststep$next[6:0]$13701
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $4\cur_cur_maxvl$next[6:0]$13702
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $4\cur_cur_srcstep$next[6:0]$13703
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $4\cur_cur_subvl$next[1:0]$13704
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 2 $4\cur_cur_svstep$next[1:0]$13705
- attribute \src "libresoc.v:199722.3-199760.6"
- wire width 7 $4\cur_cur_vl$next[6:0]$13706
- attribute \src "libresoc.v:198952.3-198986.6"
- wire $4\exec_fsm_state$next[0:0]$13606
- attribute \src "libresoc.v:199800.3-199853.6"
- wire width 2 $4\fetch_fsm_state$next[1:0]$13721
- attribute \src "libresoc.v:199633.3-199666.6"
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $4\cur_cur_dststep$next[6:0]$13493
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $4\cur_cur_maxvl$next[6:0]$13494
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $4\cur_cur_srcstep$next[6:0]$13495
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $4\cur_cur_subvl$next[1:0]$13496
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 2 $4\cur_cur_svstep$next[1:0]$13497
+ attribute \src "libresoc.v:199618.3-199656.6"
+ wire width 7 $4\cur_cur_vl$next[6:0]$13498
+ attribute \src "libresoc.v:198848.3-198882.6"
+ wire $4\exec_fsm_state$next[0:0]$13398
+ attribute \src "libresoc.v:199696.3-199749.6"
+ wire width 2 $4\fetch_fsm_state$next[1:0]$13513
+ attribute \src "libresoc.v:199529.3-199562.6"
wire $4\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199667.3-199700.6"
+ attribute \src "libresoc.v:199563.3-199596.6"
wire $4\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:198688.3-198733.6"
+ attribute \src "libresoc.v:198584.3-198629.6"
wire $4\insn_done[0:0]
- attribute \src "libresoc.v:200052.3-200150.6"
- wire width 3 $4\issue_fsm_state$next[2:0]$13746
- attribute \src "libresoc.v:199761.3-199790.6"
- wire $4\msr_read$next[0:0]$13712
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199948.3-200046.6"
+ wire width 3 $4\issue_fsm_state$next[2:0]$13538
+ attribute \src "libresoc.v:199657.3-199686.6"
+ wire $4\msr_read$next[0:0]$13504
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $4\new_svstate_dststep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $4\new_svstate_maxvl[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $4\new_svstate_srcstep[6:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $4\new_svstate_subvl[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 2 $4\new_svstate_svstep[1:0]
- attribute \src "libresoc.v:199960.3-200035.6"
+ attribute \src "libresoc.v:199856.3-199931.6"
wire width 7 $4\new_svstate_vl[6:0]
- attribute \src "libresoc.v:200245.3-200327.6"
- wire $4\pc_changed$next[0:0]$13762
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wire $4\update_svstate[0:0]
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350"
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+ wire width 64 $extend$libresoc.v:197610$13162_Y
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+ wire width 64 $extend$libresoc.v:197621$13174_Y
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+ wire width 7 $mul$libresoc.v:197530$13084_Y
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+ wire $not$libresoc.v:197536$13090_Y
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+ wire $or$libresoc.v:197643$13195_Y
+ attribute \src "libresoc.v:197605.19-197605.211"
+ wire width 64 $pos$libresoc.v:197605$13156_Y
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+ wire width 64 $pos$libresoc.v:197609$13161_Y
+ attribute \src "libresoc.v:197610.19-197610.113"
+ wire width 64 $pos$libresoc.v:197610$13163_Y
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+ wire width 64 $pos$libresoc.v:197621$13175_Y
+ attribute \src "libresoc.v:197576.19-197576.93"
+ wire $reduce_or$libresoc.v:197576$13128_Y
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+ wire $reduce_or$libresoc.v:197593$13144_Y
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+ wire width 64 $shr$libresoc.v:197531$13085_Y
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+ wire width 64 $shr$libresoc.v:197648$13200_Y
+ attribute \src "libresoc.v:197611.19-197611.116"
+ wire width 65 $sub$libresoc.v:197611$13164_Y
+ attribute \src "libresoc.v:197613.18-197613.101"
+ wire width 3 $sub$libresoc.v:197613$13166_Y
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355"
wire width 65 \$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355"
wire width 65 \$101
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
wire width 7 \$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
wire \$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$120
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
wire width 8 \$124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
wire width 8 \$125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
wire width 8 \$127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
wire width 8 \$128
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$130
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$132
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$134
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$136
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$140
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$142
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$144
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$148
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$150
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
wire \$152
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$154
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$156
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$158
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$160
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$162
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$164
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$166
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$168
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$170
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$172
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$174
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$176
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$178
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$180
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$182
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$184
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$186
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$188
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$190
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$192
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$194
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737"
wire width 3 \$195
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$198
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$200
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$202
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$204
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$206
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$208
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
wire \$210
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$212
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$214
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$216
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$218
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$220
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$222
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$224
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$226
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$228
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735"
wire width 3 \$229
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800"
wire \$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$232
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$234
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
wire \$236
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$238
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$240
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$242
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$244
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$246
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$248
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
wire width 3 \$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
wire \$250
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$252
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
wire \$254
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
wire \$256
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
wire \$258
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
wire width 3 \$26
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$260
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 64 \$262
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010"
wire width 65 \$264
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010"
wire width 65 \$265
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026"
wire width 65 \$267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026"
wire width 65 \$268
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
wire \$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
wire \$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
wire \$32
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
wire \$34
wire \$38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63"
wire \$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
wire \$60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
wire \$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
wire \$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
wire \$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
wire \$82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$84
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
wire \$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
wire \$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
wire \$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
wire width 65 \$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
wire width 65 \$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54"
wire width 32 \$95
wire output 285 \TAP_bus__tdo
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66"
wire input 295 \TAP_bus__tms
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230"
wire output 3 \busy_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 312 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101"
wire width 8 \core_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101"
wire width 8 \core_asmcode$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:229"
wire input 4 \core_bigendian_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98"
wire \core_bigendian_i$10
wire width 64 \core_cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \core_cia__ren
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 \core_core_core_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 \core_core_core_cia$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \core_core_core_cr_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \core_core_core_cr_rd$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \core_core_core_cr_rd_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \core_core_core_cr_rd_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \core_core_core_cr_wr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \core_core_core_cr_wr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \core_core_core_exc_$signal
attribute \enum_value_00100000000000 "MMU"
attribute \enum_value_01000000000000 "SV"
attribute \enum_value_10000000000000 "VL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 \core_core_core_fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 \core_core_core_fn_unit$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 \core_core_core_input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 \core_core_core_input_carry$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 \core_core_core_insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 \core_core_core_insn$next
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \enum_value_1001100 "OP_SETVL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 \core_core_core_insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 \core_core_core_insn_type$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire \core_core_core_is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
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wire \core_core_core_is_32bit$next
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wire width 64 \core_core_core_msr$next
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wire \core_core_core_oe$next
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wire \core_core_core_oe_ok
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wire \core_core_core_oe_ok$next
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wire \core_core_core_rc$next
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wire \core_core_core_rc_ok
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wire \core_core_core_rc_ok$next
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wire width 13 \core_core_core_trapaddr$next
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wire width 8 \core_core_core_traptype$next
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wire width 7 \core_core_cr_in1$next
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wire \core_core_cr_in1_ok$next
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wire width 7 \core_core_cr_in2
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wire width 7 \core_core_cr_in2$1
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wire width 7 \core_core_cr_in2$1$next
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wire width 7 \core_core_cr_in2$next
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wire \core_core_cr_in2_ok
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wire \core_core_cr_in2_ok$2
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wire \core_core_cr_in2_ok$2$next
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wire \core_core_cr_in2_ok$next
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wire width 7 \core_core_cr_out$next
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wire \core_core_cr_wr_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
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wire width 7 \core_core_dststep$next
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wire width 7 \core_core_ea$next
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wire width 3 \core_core_fast1$next
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wire \core_core_fast1_ok
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wire \core_core_fast1_ok$next
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wire width 3 \core_core_fast2$next
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wire \core_core_fast2_ok$next
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wire width 3 \core_core_fasto1$next
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wire width 3 \core_core_fasto2$next
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wire \core_core_lk$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31"
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wire width 64 \core_core_pc$next
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wire width 7 \core_core_reg1$next
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wire \core_core_reg1_ok
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wire \core_core_reg1_ok$next
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wire width 7 \core_core_reg2
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wire width 7 \core_core_reg2$next
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wire \core_core_reg2_ok
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wire \core_core_reg2_ok$next
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wire width 7 \core_core_reg3$next
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wire \core_core_reg3_ok$next
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wire width 7 \core_core_rego
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wire width 7 \core_core_rego$next
attribute \enum_base_type "SPR"
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wire width 10 \core_core_spr1$next
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wire \core_core_spr1_ok
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wire \core_core_spr1_ok$next
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
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attribute \enum_value_1111111111 "PIR"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
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wire \core_coresync_rst
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wire \core_cr_out_ok
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wire \core_cr_out_ok$next
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wire \core_cu_ad__go_i
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wire \core_dmi__ren
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wire \core_ea_ok
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wire \core_ea_ok$next
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wire \core_eint$next
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wire \core_fasto1_ok
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wire \core_fasto1_ok$next
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wire \core_fasto2_ok
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wire \core_fasto2_ok$next
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wire \core_rego_ok
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wire \core_rego_ok$next
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wire \core_spro_ok
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wire \core_spro_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
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wire width 3 \core_wen$11
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wire \core_xer_out
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wire \core_xer_out$next
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wire input 2 \coresync_clk
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wire \d_cr_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:965"
wire \d_cr_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955"
wire \d_reg_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955"
wire \d_reg_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:975"
wire \d_xer_delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:970"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:975"
wire \d_xer_delay$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 \dbg_core_dbg_core_dbg_dststep
wire output 11 \dbus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
wire output 15 \dbus__we
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101"
wire width 8 \dec2_asmcode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466"
wire \dec2_bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
wire width 64 \dec2_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_cr_in1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_in1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_cr_in2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_cr_in2$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_in2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_in2_ok$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_out_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \dec2_cr_rd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_rd_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 8 \dec2_cr_wr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_cr_wr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19"
wire width 64 \dec2_cur_dec
wire width 64 \dec2_cur_pc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16"
wire width 64 \dec2_cur_pc$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_ea
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \dec2_exc_$signal
wire \dec2_exc_$signal$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16"
wire \dec2_exc_$signal$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec2_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec2_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec2_fasto1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_fasto1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 3 \dec2_fasto2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_fasto2_ok
attribute \enum_base_type "Function"
attribute \enum_value_00000000000000 "NONE"
attribute \enum_value_00100000000000 "MMU"
attribute \enum_value_01000000000000 "SV"
attribute \enum_value_10000000000000 "VL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
wire width 14 \dec2_fn_unit
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
wire width 2 \dec2_input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 32 \dec2_insn
attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1001010 "OP_MTMSR"
attribute \enum_value_1001011 "OP_TLBIE"
attribute \enum_value_1001100 "OP_SETVL"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
wire width 7 \dec2_insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire \dec2_is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
wire \dec2_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43"
wire width 64 \dec2_msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_oe_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 \dec2_raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465"
wire width 32 \dec2_raw_opcode_in$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_reg1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_reg1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_reg2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_reg2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_reg3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_reg3_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 7 \dec2_rego
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_rego_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \dec2_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_spr1_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 10 \dec2_spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \dec2_spro_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714"
wire \dec2_sv_a_nz
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
wire width 13 \dec2_trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
wire width 8 \dec2_traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111"
wire width 3 \dec2_xer_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112"
wire \dec2_xer_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799"
wire width 2 \delay
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:799"
wire width 2 \delay$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 155 \eint_0__core__i
wire output 157 \eint_2__core__i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 26 \eint_2__pad__i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
wire \exec_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
wire \exec_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889"
wire \exec_insn_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883"
- wire \exec_insn_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:888"
+ wire \exec_insn_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:893"
wire \exec_pc_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:887"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:892"
wire \exec_pc_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
wire width 2 \fetch_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
wire width 2 \fetch_fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877"
wire \fetch_insn_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876"
wire \fetch_insn_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873"
wire \fetch_pc_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872"
wire \fetch_pc_valid_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
wire width 2 \fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
wire width 2 \fsm_state$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 164 \gpio_e10__core__i
wire \imem_f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93"
wire \imem_wb_icache_en
- attribute \src "libresoc.v:195358.7-195358.15"
+ attribute \src "libresoc.v:195254.7-195254.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:254"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:259"
wire \insn_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 305 \int_level_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632"
wire \is_last
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866"
wire \is_svp64_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
wire width 3 \issue_fsm_state
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
wire width 3 \issue_fsm_state$next
attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15"
wire \jtag_dmi0__ack_o
wire input 77 \mspi0_mosi__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 208 \mspi0_mosi__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
wire \msr_read
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:281"
wire \msr_read$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 82 \mtwi_scl__core__o
wire output 211 \mtwi_sda__pad__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 212 \mtwi_sda__pad__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1008"
wire width 64 \new_dec
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28"
wire width 7 \new_svstate_dststep
wire width 2 \new_svstate_svstep
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30"
wire width 7 \new_svstate_vl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1025"
wire width 64 \new_tb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:509"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514"
wire width 7 \next_dststep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
wire width 7 \next_srcstep
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855"
wire width 64 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855"
wire width 64 \nia$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61"
wire width 64 \pc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836"
wire \pc_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836"
wire \pc_changed$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 input 7 \pc_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire input 6 \pc_i_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:226"
wire width 64 output 5 \pc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \pc_ok_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \pc_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
wire \por_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:881"
wire \pred_insn_ready_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875"
- wire \pred_insn_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880"
+ wire \pred_insn_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885"
wire \pred_mask_ready_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884"
wire \pred_mask_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire input 108 \sdr_a_0__core__o
wire input 124 \sdr_we_n__core__o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74"
wire output 255 \sdr_we_n__pad__o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:832"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837"
wire \sv_changed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:832"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:837"
wire \sv_changed$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61"
wire width 64 \svstate
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 32 \svstate_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire \svstate_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \svstate_ok_delay
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62"
wire \svstate_ok_delay$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798"
wire \ti_rst
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:501"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506"
wire \update_svstate
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire \xics_icp_core_irq_o
wire width 8 \xics_ics_icp_o_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350"
- cell $add $add$libresoc.v:197633$13291
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355"
+ cell $add $add$libresoc.v:197529$13083
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:197633$13291_Y
+ connect \Y $add$libresoc.v:197529$13083_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510"
- cell $add $add$libresoc.v:197645$13302
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515"
+ cell $add $add$libresoc.v:197541$13094
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \cur_cur_srcstep
connect \B 1'1
- connect \Y $add$libresoc.v:197645$13302_Y
+ connect \Y $add$libresoc.v:197541$13094_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:511"
- cell $add $add$libresoc.v:197646$13303
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:516"
+ cell $add $add$libresoc.v:197542$13095
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \cur_cur_dststep
connect \B 1'1
- connect \Y $add$libresoc.v:197646$13303_Y
+ connect \Y $add$libresoc.v:197542$13095_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021"
- cell $add $add$libresoc.v:197716$13373
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026"
+ cell $add $add$libresoc.v:197612$13165
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:197716$13373_Y
+ connect \Y $add$libresoc.v:197612$13165_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339"
- cell $add $add$libresoc.v:197750$13406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ cell $add $add$libresoc.v:197646$13198
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:197750$13406_Y
+ connect \Y $add$libresoc.v:197646$13198_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197638$13296
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197534$13088
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$106
connect \B \$108
- connect \Y $and$libresoc.v:197638$13296_Y
+ connect \Y $and$libresoc.v:197534$13088_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197641$13299
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197537$13091
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$112
connect \B \$114
- connect \Y $and$libresoc.v:197641$13299_Y
+ connect \Y $and$libresoc.v:197537$13091_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197649$13306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197545$13098
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$130
connect \B \$132
- connect \Y $and$libresoc.v:197649$13306_Y
+ connect \Y $and$libresoc.v:197545$13098_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197652$13309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197548$13101
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$136
connect \B \$138
- connect \Y $and$libresoc.v:197652$13309_Y
+ connect \Y $and$libresoc.v:197548$13101_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $and $and$libresoc.v:197654$13311
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $and $and$libresoc.v:197550$13103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$142
- connect \Y $and$libresoc.v:197654$13311_Y
+ connect \Y $and$libresoc.v:197550$13103_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197657$13314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197553$13106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$146
connect \B \$148
- connect \Y $and$libresoc.v:197657$13314_Y
+ connect \Y $and$libresoc.v:197553$13106_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197663$13319
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197559$13111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$158
connect \B \$160
- connect \Y $and$libresoc.v:197663$13319_Y
+ connect \Y $and$libresoc.v:197559$13111_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197666$13322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197562$13114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$164
connect \B \$166
- connect \Y $and$libresoc.v:197666$13322_Y
+ connect \Y $and$libresoc.v:197562$13114_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197669$13325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197565$13117
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$170
connect \B \$172
- connect \Y $and$libresoc.v:197669$13325_Y
+ connect \Y $and$libresoc.v:197565$13117_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197672$13328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197568$13120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$176
connect \B \$178
- connect \Y $and$libresoc.v:197672$13328_Y
+ connect \Y $and$libresoc.v:197568$13120_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197675$13331
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197571$13123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$182
connect \B \$184
- connect \Y $and$libresoc.v:197675$13331_Y
+ connect \Y $and$libresoc.v:197571$13123_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197678$13334
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197574$13126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$188
connect \B \$190
- connect \Y $and$libresoc.v:197678$13334_Y
+ connect \Y $and$libresoc.v:197574$13126_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
- cell $and $and$libresoc.v:197679$13335
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737"
+ cell $and $and$libresoc.v:197575$13127
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
connect \B 1'1
- connect \Y $and$libresoc.v:197679$13335_Y
+ connect \Y $and$libresoc.v:197575$13127_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197683$13339
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197579$13131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$198
connect \B \$200
- connect \Y $and$libresoc.v:197683$13339_Y
+ connect \Y $and$libresoc.v:197579$13131_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197686$13342
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197582$13134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$204
connect \B \$206
- connect \Y $and$libresoc.v:197686$13342_Y
+ connect \Y $and$libresoc.v:197582$13134_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197692$13347
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197588$13139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$216
connect \B \$218
- connect \Y $and$libresoc.v:197692$13347_Y
+ connect \Y $and$libresoc.v:197588$13139_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197695$13350
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197591$13142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$222
connect \B \$224
- connect \Y $and$libresoc.v:197695$13350_Y
+ connect \Y $and$libresoc.v:197591$13142_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
- cell $and $and$libresoc.v:197696$13351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735"
+ cell $and $and$libresoc.v:197592$13143
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \core_state_nia_wen
connect \B 3'100
- connect \Y $and$libresoc.v:197696$13351_Y
+ connect \Y $and$libresoc.v:197592$13143_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $and $and$libresoc.v:197699$13354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $and $and$libresoc.v:197595$13146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$232
- connect \Y $and$libresoc.v:197699$13354_Y
+ connect \Y $and$libresoc.v:197595$13146_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197704$13359
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197600$13151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$238
connect \B \$240
- connect \Y $and$libresoc.v:197704$13359_Y
+ connect \Y $and$libresoc.v:197600$13151_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197707$13362
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197603$13154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$244
connect \B \$246
- connect \Y $and$libresoc.v:197707$13362_Y
+ connect \Y $and$libresoc.v:197603$13154_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:197722$13379
+ cell $and $and$libresoc.v:197618$13171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_cu_st__rel_o
connect \B \$34
- connect \Y $and$libresoc.v:197722$13379_Y
+ connect \Y $and$libresoc.v:197618$13171_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197728$13386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197624$13178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$44
connect \B \$46
- connect \Y $and$libresoc.v:197728$13386_Y
+ connect \Y $and$libresoc.v:197624$13178_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $and $and$libresoc.v:197730$13388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $and $and$libresoc.v:197626$13180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$50
- connect \Y $and$libresoc.v:197730$13388_Y
+ connect \Y $and$libresoc.v:197626$13180_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197733$13391
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197629$13183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$54
connect \B \$56
- connect \Y $and$libresoc.v:197733$13391_Y
+ connect \Y $and$libresoc.v:197629$13183_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $and $and$libresoc.v:197739$13396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $and $and$libresoc.v:197635$13188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$66
connect \B \$68
- connect \Y $and$libresoc.v:197739$13396_Y
+ connect \Y $and$libresoc.v:197635$13188_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $and $and$libresoc.v:197741$13398
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $and $and$libresoc.v:197637$13190
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \is_svp64_mode
connect \B \$72
- connect \Y $and$libresoc.v:197741$13398_Y
+ connect \Y $and$libresoc.v:197637$13190_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $and $and$libresoc.v:197744$13401
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $and $and$libresoc.v:197640$13193
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$76
connect \B \$78
- connect \Y $and$libresoc.v:197744$13401_Y
+ connect \Y $and$libresoc.v:197640$13193_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $eq $eq$libresoc.v:197653$13310
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $eq $eq$libresoc.v:197549$13102
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:197653$13310_Y
+ connect \Y $eq$libresoc.v:197549$13102_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $eq $eq$libresoc.v:197698$13353
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $eq $eq$libresoc.v:197594$13145
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:197698$13353_Y
+ connect \Y $eq$libresoc.v:197594$13145_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
- cell $eq $eq$libresoc.v:197708$13363
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ cell $eq $eq$libresoc.v:197604$13155
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \next_srcstep
connect \B \cur_cur_vl
- connect \Y $eq$libresoc.v:197708$13363_Y
+ connect \Y $eq$libresoc.v:197604$13155_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $eq $eq$libresoc.v:197729$13387
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $eq $eq$libresoc.v:197625$13179
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:197729$13387_Y
+ connect \Y $eq$libresoc.v:197625$13179_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
- cell $eq $eq$libresoc.v:197740$13397
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
+ cell $eq $eq$libresoc.v:197636$13189
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_cur_vl
connect \B 1'0
- connect \Y $eq$libresoc.v:197740$13397_Y
+ connect \Y $eq$libresoc.v:197636$13189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:197713$13368
+ cell $pos $extend$libresoc.v:197609$13160
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \core_full_rd2__data_o
- connect \Y $extend$libresoc.v:197713$13368_Y
+ connect \Y $extend$libresoc.v:197609$13160_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $extend$libresoc.v:197714$13370
+ cell $pos $extend$libresoc.v:197610$13162
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \core_full_rd__data_o
- connect \Y $extend$libresoc.v:197714$13370_Y
+ connect \Y $extend$libresoc.v:197610$13162_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $extend$libresoc.v:197725$13382
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
+ cell $pos $extend$libresoc.v:197621$13174
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \svstate_i
- connect \Y $extend$libresoc.v:197725$13382_Y
+ connect \Y $extend$libresoc.v:197621$13174_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:197634$13292
+ cell $mul $mul$libresoc.v:197530$13084
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \$100 [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:197634$13292_Y
+ connect \Y $mul$libresoc.v:197530$13084_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:197751$13407
+ cell $mul $mul$libresoc.v:197647$13199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:197751$13407_Y
+ connect \Y $mul$libresoc.v:197647$13199_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
- cell $ne $ne$libresoc.v:197702$13357
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800"
+ cell $ne $ne$libresoc.v:197598$13149
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B 1'0
- connect \Y $ne$libresoc.v:197702$13357_Y
+ connect \Y $ne$libresoc.v:197598$13149_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
- cell $ne $ne$libresoc.v:197710$13365
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
+ cell $ne $ne$libresoc.v:197606$13157
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_core_insn_type
connect \B 7'0000001
- connect \Y $ne$libresoc.v:197710$13365_Y
+ connect \Y $ne$libresoc.v:197606$13157_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
- cell $ne $ne$libresoc.v:197720$13377
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
+ cell $ne $ne$libresoc.v:197616$13169
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B \$30
- connect \Y $ne$libresoc.v:197720$13377_Y
+ connect \Y $ne$libresoc.v:197616$13169_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197636$13294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197532$13086
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197636$13294_Y
+ connect \Y $not$libresoc.v:197532$13086_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197637$13295
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197533$13087
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197637$13295_Y
+ connect \Y $not$libresoc.v:197533$13087_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197639$13297
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197535$13089
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197639$13297_Y
+ connect \Y $not$libresoc.v:197535$13089_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197640$13298
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197536$13090
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197640$13298_Y
+ connect \Y $not$libresoc.v:197536$13090_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197647$13304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197543$13096
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197647$13304_Y
+ connect \Y $not$libresoc.v:197543$13096_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197648$13305
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197544$13097
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197648$13305_Y
+ connect \Y $not$libresoc.v:197544$13097_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197650$13307
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197546$13099
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197650$13307_Y
+ connect \Y $not$libresoc.v:197546$13099_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197651$13308
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197547$13100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197651$13308_Y
+ connect \Y $not$libresoc.v:197547$13100_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197655$13312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197551$13104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197655$13312_Y
+ connect \Y $not$libresoc.v:197551$13104_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197656$13313
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197552$13105
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197656$13313_Y
+ connect \Y $not$libresoc.v:197552$13105_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197661$13317
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197557$13109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197661$13317_Y
+ connect \Y $not$libresoc.v:197557$13109_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197662$13318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197558$13110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197662$13318_Y
+ connect \Y $not$libresoc.v:197558$13110_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197664$13320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197560$13112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197664$13320_Y
+ connect \Y $not$libresoc.v:197560$13112_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197665$13321
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197561$13113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197665$13321_Y
+ connect \Y $not$libresoc.v:197561$13113_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197667$13323
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197563$13115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197667$13323_Y
+ connect \Y $not$libresoc.v:197563$13115_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197668$13324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197564$13116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197668$13324_Y
+ connect \Y $not$libresoc.v:197564$13116_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197670$13326
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197566$13118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197670$13326_Y
+ connect \Y $not$libresoc.v:197566$13118_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197671$13327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197567$13119
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197671$13327_Y
+ connect \Y $not$libresoc.v:197567$13119_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197673$13329
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197569$13121
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197673$13329_Y
+ connect \Y $not$libresoc.v:197569$13121_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197674$13330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197570$13122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197674$13330_Y
+ connect \Y $not$libresoc.v:197570$13122_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197676$13332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197572$13124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197676$13332_Y
+ connect \Y $not$libresoc.v:197572$13124_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197677$13333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197573$13125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197677$13333_Y
+ connect \Y $not$libresoc.v:197573$13125_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197681$13337
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197577$13129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197681$13337_Y
+ connect \Y $not$libresoc.v:197577$13129_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197682$13338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197578$13130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197682$13338_Y
+ connect \Y $not$libresoc.v:197578$13130_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197684$13340
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197580$13132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197684$13340_Y
+ connect \Y $not$libresoc.v:197580$13132_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197685$13341
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197581$13133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197685$13341_Y
+ connect \Y $not$libresoc.v:197581$13133_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197690$13345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197586$13137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197690$13345_Y
+ connect \Y $not$libresoc.v:197586$13137_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197691$13346
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197587$13138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197691$13346_Y
+ connect \Y $not$libresoc.v:197587$13138_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197693$13348
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197589$13140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197693$13348_Y
+ connect \Y $not$libresoc.v:197589$13140_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197694$13349
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197590$13141
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197694$13349_Y
+ connect \Y $not$libresoc.v:197590$13141_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
- cell $not $not$libresoc.v:197700$13355
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
+ cell $not $not$libresoc.v:197596$13147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:197700$13355_Y
+ connect \Y $not$libresoc.v:197596$13147_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197701$13356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197597$13148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197701$13356_Y
+ connect \Y $not$libresoc.v:197597$13148_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197703$13358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197599$13150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197703$13358_Y
+ connect \Y $not$libresoc.v:197599$13150_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197705$13360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197601$13152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197705$13360_Y
+ connect \Y $not$libresoc.v:197601$13152_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197706$13361
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197602$13153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197706$13361_Y
+ connect \Y $not$libresoc.v:197602$13153_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
- cell $not $not$libresoc.v:197711$13366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
+ cell $not $not$libresoc.v:197607$13158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:197711$13366_Y
+ connect \Y $not$libresoc.v:197607$13158_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
- cell $not $not$libresoc.v:197712$13367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
+ cell $not $not$libresoc.v:197608$13159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $not$libresoc.v:197712$13367_Y
+ connect \Y $not$libresoc.v:197608$13159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:197721$13378
+ cell $not $not$libresoc.v:197617$13170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o_dly
- connect \Y $not$libresoc.v:197721$13378_Y
+ connect \Y $not$libresoc.v:197617$13170_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63"
- cell $not $not$libresoc.v:197723$13380
+ cell $not $not$libresoc.v:197619$13172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_i_ok
- connect \Y $not$libresoc.v:197723$13380_Y
+ connect \Y $not$libresoc.v:197619$13172_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63"
- cell $not $not$libresoc.v:197724$13381
+ cell $not $not$libresoc.v:197620$13173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \svstate_i_ok
- connect \Y $not$libresoc.v:197724$13381_Y
+ connect \Y $not$libresoc.v:197620$13173_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197726$13384
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197622$13176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197726$13384_Y
+ connect \Y $not$libresoc.v:197622$13176_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197727$13385
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197623$13177
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197727$13385_Y
+ connect \Y $not$libresoc.v:197623$13177_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197731$13389
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197627$13181
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197731$13389_Y
+ connect \Y $not$libresoc.v:197627$13181_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197732$13390
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197628$13182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197732$13390_Y
+ connect \Y $not$libresoc.v:197628$13182_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197737$13394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197633$13186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197737$13394_Y
+ connect \Y $not$libresoc.v:197633$13186_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
- cell $not $not$libresoc.v:197738$13395
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
+ cell $not $not$libresoc.v:197634$13187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197738$13395_Y
+ connect \Y $not$libresoc.v:197634$13187_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197742$13399
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197638$13191
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:197742$13399_Y
+ connect \Y $not$libresoc.v:197638$13191_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
- cell $not $not$libresoc.v:197743$13400
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
+ cell $not $not$libresoc.v:197639$13192
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:197743$13400_Y
+ connect \Y $not$libresoc.v:197639$13192_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
- cell $not $not$libresoc.v:197748$13404
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
+ cell $not $not$libresoc.v:197644$13196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:197748$13404_Y
+ connect \Y $not$libresoc.v:197644$13196_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
- cell $not $not$libresoc.v:197749$13405
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
+ cell $not $not$libresoc.v:197645$13197
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:197749$13405_Y
+ connect \Y $not$libresoc.v:197645$13197_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
- cell $or $or$libresoc.v:197642$13300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+ cell $or $or$libresoc.v:197538$13092
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:197642$13300_Y
+ connect \Y $or$libresoc.v:197538$13092_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
- cell $or $or$libresoc.v:197644$13301
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
+ cell $or $or$libresoc.v:197540$13093
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$120
connect \B \is_last
- connect \Y $or$libresoc.v:197644$13301_Y
+ connect \Y $or$libresoc.v:197540$13093_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
- cell $or $or$libresoc.v:197658$13315
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+ cell $or $or$libresoc.v:197554$13107
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:197658$13315_Y
+ connect \Y $or$libresoc.v:197554$13107_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
- cell $or $or$libresoc.v:197660$13316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
+ cell $or $or$libresoc.v:197556$13108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$154
connect \B \is_last
- connect \Y $or$libresoc.v:197660$13316_Y
+ connect \Y $or$libresoc.v:197556$13108_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
- cell $or $or$libresoc.v:197687$13343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+ cell $or $or$libresoc.v:197583$13135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:197687$13343_Y
+ connect \Y $or$libresoc.v:197583$13135_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
- cell $or $or$libresoc.v:197689$13344
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
+ cell $or $or$libresoc.v:197585$13136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$212
connect \B \is_last
- connect \Y $or$libresoc.v:197689$13344_Y
+ connect \Y $or$libresoc.v:197585$13136_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
- cell $or $or$libresoc.v:197718$13375
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
+ cell $or $or$libresoc.v:197614$13167
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:197718$13375_Y
+ connect \Y $or$libresoc.v:197614$13167_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
- cell $or $or$libresoc.v:197719$13376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:806"
+ cell $or $or$libresoc.v:197615$13168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$28
connect \B \rst
- connect \Y $or$libresoc.v:197719$13376_Y
+ connect \Y $or$libresoc.v:197615$13168_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
- cell $or $or$libresoc.v:197734$13392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+ cell $or $or$libresoc.v:197630$13184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:197734$13392_Y
+ connect \Y $or$libresoc.v:197630$13184_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
- cell $or $or$libresoc.v:197736$13393
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
+ cell $or $or$libresoc.v:197632$13185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$62
connect \B \is_last
- connect \Y $or$libresoc.v:197736$13393_Y
+ connect \Y $or$libresoc.v:197632$13185_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
- cell $or $or$libresoc.v:197745$13402
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
+ cell $or $or$libresoc.v:197641$13194
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \pc_changed
connect \B \sv_changed
- connect \Y $or$libresoc.v:197745$13402_Y
+ connect \Y $or$libresoc.v:197641$13194_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640"
- cell $or $or$libresoc.v:197747$13403
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:645"
+ cell $or $or$libresoc.v:197643$13195
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$84
connect \B \is_last
- connect \Y $or$libresoc.v:197747$13403_Y
+ connect \Y $or$libresoc.v:197643$13195_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:197709$13364
+ cell $pos $pos$libresoc.v:197605$13156
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
- connect \Y $pos$libresoc.v:197709$13364_Y
+ connect \Y $pos$libresoc.v:197605$13156_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:197713$13369
+ cell $pos $pos$libresoc.v:197609$13161
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:197713$13368_Y
- connect \Y $pos$libresoc.v:197713$13369_Y
+ connect \A $extend$libresoc.v:197609$13160_Y
+ connect \Y $pos$libresoc.v:197609$13161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
- cell $pos $pos$libresoc.v:197714$13371
+ cell $pos $pos$libresoc.v:197610$13163
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:197714$13370_Y
- connect \Y $pos$libresoc.v:197714$13371_Y
+ connect \A $extend$libresoc.v:197610$13162_Y
+ connect \Y $pos$libresoc.v:197610$13163_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
- cell $pos $pos$libresoc.v:197725$13383
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
+ cell $pos $pos$libresoc.v:197621$13175
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:197725$13382_Y
- connect \Y $pos$libresoc.v:197725$13383_Y
+ connect \A $extend$libresoc.v:197621$13174_Y
+ connect \Y $pos$libresoc.v:197621$13175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:197680$13336
+ cell $reduce_or $reduce_or$libresoc.v:197576$13128
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$195
- connect \Y $reduce_or$libresoc.v:197680$13336_Y
+ connect \Y $reduce_or$libresoc.v:197576$13128_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:197697$13352
+ cell $reduce_or $reduce_or$libresoc.v:197593$13144
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \$229
- connect \Y $reduce_or$libresoc.v:197697$13352_Y
+ connect \Y $reduce_or$libresoc.v:197593$13144_Y
end
- attribute \src "libresoc.v:197635.18-197635.41"
- cell $shr $shr$libresoc.v:197635$13293
+ attribute \src "libresoc.v:197531.18-197531.41"
+ cell $shr $shr$libresoc.v:197531$13085
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$103
- connect \Y $shr$libresoc.v:197635$13293_Y
+ connect \Y $shr$libresoc.v:197531$13085_Y
end
- attribute \src "libresoc.v:197752.18-197752.40"
- cell $shr $shr$libresoc.v:197752$13408
+ attribute \src "libresoc.v:197648.18-197648.40"
+ cell $shr $shr$libresoc.v:197648$13200
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$96
- connect \Y $shr$libresoc.v:197752$13408_Y
+ connect \Y $shr$libresoc.v:197648$13200_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005"
- cell $sub $sub$libresoc.v:197715$13372
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1010"
+ cell $sub $sub$libresoc.v:197611$13164
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \core_issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:197715$13372_Y
+ connect \Y $sub$libresoc.v:197611$13164_Y
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796"
- cell $sub $sub$libresoc.v:197717$13374
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:801"
+ cell $sub $sub$libresoc.v:197613$13166
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:197717$13374_Y
+ connect \Y $sub$libresoc.v:197613$13166_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:197961.8-198059.4"
+ attribute \src "libresoc.v:197857.8-197955.4"
cell \core \core
connect \bigendian_i \core_bigendian_i$10
connect \cia__data_o \core_cia__data_o
connect \wen$10 \core_wen$11
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198060.7-198091.4"
+ attribute \src "libresoc.v:197956.7-197987.4"
cell \dbg \dbg
connect \clk \clk
connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198092.8-198159.4"
+ attribute \src "libresoc.v:197988.8-198055.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198160.8-198176.4"
+ attribute \src "libresoc.v:198056.8-198072.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198177.8-198460.4"
+ attribute \src "libresoc.v:198073.8-198356.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198461.12-198475.4"
+ attribute \src "libresoc.v:198357.12-198371.4"
cell \xics_icp \xics_icp
connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \rst \rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:198476.12-198489.4"
+ attribute \src "libresoc.v:198372.12-198385.4"
cell \xics_ics \xics_ics
connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \int_level_i \int_level_i
connect \rst \rst
end
- attribute \src "libresoc.v:195358.7-195358.20"
- process $proc$libresoc.v:195358$13992
+ attribute \src "libresoc.v:195254.7-195254.20"
+ process $proc$libresoc.v:195254$13784
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:195626.13-195626.33"
- process $proc$libresoc.v:195626$13993
+ attribute \src "libresoc.v:195522.13-195522.33"
+ process $proc$libresoc.v:195522$13785
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:195632.7-195632.35"
- process $proc$libresoc.v:195632$13994
+ attribute \src "libresoc.v:195528.7-195528.35"
+ process $proc$libresoc.v:195528$13786
assign { } { }
- assign $0\core_bigendian_i$10[0:0]$13995 1'0
+ assign $0\core_bigendian_i$10[0:0]$13787 1'0
sync always
sync init
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13995
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13787
end
- attribute \src "libresoc.v:195640.14-195640.55"
- process $proc$libresoc.v:195640$13996
+ attribute \src "libresoc.v:195536.14-195536.55"
+ process $proc$libresoc.v:195536$13788
assign { } { }
assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_cia $1\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:195644.13-195644.41"
- process $proc$libresoc.v:195644$13997
+ attribute \src "libresoc.v:195540.13-195540.41"
+ process $proc$libresoc.v:195540$13789
assign { } { }
assign $1\core_core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:195648.7-195648.37"
- process $proc$libresoc.v:195648$13998
+ attribute \src "libresoc.v:195544.7-195544.37"
+ process $proc$libresoc.v:195544$13790
assign { } { }
assign $1\core_core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:195652.13-195652.41"
- process $proc$libresoc.v:195652$13999
+ attribute \src "libresoc.v:195548.13-195548.41"
+ process $proc$libresoc.v:195548$13791
assign { } { }
assign $1\core_core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:195656.7-195656.42"
- process $proc$libresoc.v:195656$14000
+ attribute \src "libresoc.v:195552.7-195552.42"
+ process $proc$libresoc.v:195552$13792
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$14001 1'0
+ assign $0\core_core_core_exc_$signal[0:0]$13793 1'0
sync always
sync init
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14001
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13793
end
- attribute \src "libresoc.v:195658.7-195658.44"
- process $proc$libresoc.v:195658$14002
+ attribute \src "libresoc.v:195554.7-195554.44"
+ process $proc$libresoc.v:195554$13794
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$14003 1'0
+ assign $0\core_core_core_exc_$signal$3[0:0]$13795 1'0
sync always
sync init
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14003
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13795
end
- attribute \src "libresoc.v:195662.7-195662.44"
- process $proc$libresoc.v:195662$14004
+ attribute \src "libresoc.v:195558.7-195558.44"
+ process $proc$libresoc.v:195558$13796
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$14005 1'0
+ assign $0\core_core_core_exc_$signal$4[0:0]$13797 1'0
sync always
sync init
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14005
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13797
end
- attribute \src "libresoc.v:195666.7-195666.44"
- process $proc$libresoc.v:195666$14006
+ attribute \src "libresoc.v:195562.7-195562.44"
+ process $proc$libresoc.v:195562$13798
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$14007 1'0
+ assign $0\core_core_core_exc_$signal$5[0:0]$13799 1'0
sync always
sync init
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14007
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13799
end
- attribute \src "libresoc.v:195670.7-195670.44"
- process $proc$libresoc.v:195670$14008
+ attribute \src "libresoc.v:195566.7-195566.44"
+ process $proc$libresoc.v:195566$13800
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$14009 1'0
+ assign $0\core_core_core_exc_$signal$6[0:0]$13801 1'0
sync always
sync init
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14009
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13801
end
- attribute \src "libresoc.v:195674.7-195674.44"
- process $proc$libresoc.v:195674$14010
+ attribute \src "libresoc.v:195570.7-195570.44"
+ process $proc$libresoc.v:195570$13802
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$14011 1'0
+ assign $0\core_core_core_exc_$signal$7[0:0]$13803 1'0
sync always
sync init
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14011
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13803
end
- attribute \src "libresoc.v:195678.7-195678.44"
- process $proc$libresoc.v:195678$14012
+ attribute \src "libresoc.v:195574.7-195574.44"
+ process $proc$libresoc.v:195574$13804
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$14013 1'0
+ assign $0\core_core_core_exc_$signal$8[0:0]$13805 1'0
sync always
sync init
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14013
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13805
end
- attribute \src "libresoc.v:195682.7-195682.44"
- process $proc$libresoc.v:195682$14014
+ attribute \src "libresoc.v:195578.7-195578.44"
+ process $proc$libresoc.v:195578$13806
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$14015 1'0
+ assign $0\core_core_core_exc_$signal$9[0:0]$13807 1'0
sync always
sync init
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14015
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13807
end
- attribute \src "libresoc.v:195703.14-195703.47"
- process $proc$libresoc.v:195703$14016
+ attribute \src "libresoc.v:195599.14-195599.47"
+ process $proc$libresoc.v:195599$13808
assign { } { }
assign $1\core_core_core_fn_unit[13:0] 14'00000000000000
sync always
sync init
update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0]
end
- attribute \src "libresoc.v:195711.13-195711.46"
- process $proc$libresoc.v:195711$14017
+ attribute \src "libresoc.v:195607.13-195607.46"
+ process $proc$libresoc.v:195607$13809
assign { } { }
assign $1\core_core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_core_input_carry $1\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:195715.14-195715.41"
- process $proc$libresoc.v:195715$14018
+ attribute \src "libresoc.v:195611.14-195611.41"
+ process $proc$libresoc.v:195611$13810
assign { } { }
assign $1\core_core_core_insn[31:0] 0
sync always
sync init
update \core_core_core_insn $1\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:195794.13-195794.45"
- process $proc$libresoc.v:195794$14019
+ attribute \src "libresoc.v:195690.13-195690.45"
+ process $proc$libresoc.v:195690$13811
assign { } { }
assign $1\core_core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_core_insn_type $1\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:195798.7-195798.37"
- process $proc$libresoc.v:195798$14020
+ attribute \src "libresoc.v:195694.7-195694.37"
+ process $proc$libresoc.v:195694$13812
assign { } { }
assign $1\core_core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:195802.14-195802.55"
- process $proc$libresoc.v:195802$14021
+ attribute \src "libresoc.v:195698.14-195698.55"
+ process $proc$libresoc.v:195698$13813
assign { } { }
assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_core_msr $1\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:195806.7-195806.31"
- process $proc$libresoc.v:195806$14022
+ attribute \src "libresoc.v:195702.7-195702.31"
+ process $proc$libresoc.v:195702$13814
assign { } { }
assign $1\core_core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_core_oe $1\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:195810.7-195810.34"
- process $proc$libresoc.v:195810$14023
+ attribute \src "libresoc.v:195706.7-195706.34"
+ process $proc$libresoc.v:195706$13815
assign { } { }
assign $1\core_core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:195814.7-195814.31"
- process $proc$libresoc.v:195814$14024
+ attribute \src "libresoc.v:195710.7-195710.31"
+ process $proc$libresoc.v:195710$13816
assign { } { }
assign $1\core_core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_core_rc $1\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:195818.7-195818.34"
- process $proc$libresoc.v:195818$14025
+ attribute \src "libresoc.v:195714.7-195714.34"
+ process $proc$libresoc.v:195714$13817
assign { } { }
assign $1\core_core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:195822.14-195822.48"
- process $proc$libresoc.v:195822$14026
+ attribute \src "libresoc.v:195718.14-195718.48"
+ process $proc$libresoc.v:195718$13818
assign { } { }
assign $1\core_core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:195826.13-195826.44"
- process $proc$libresoc.v:195826$14027
+ attribute \src "libresoc.v:195722.13-195722.44"
+ process $proc$libresoc.v:195722$13819
assign { } { }
assign $1\core_core_core_traptype[7:0] 8'00000000
sync always
sync init
update \core_core_core_traptype $1\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:195830.13-195830.37"
- process $proc$libresoc.v:195830$14028
+ attribute \src "libresoc.v:195726.13-195726.37"
+ process $proc$libresoc.v:195726$13820
assign { } { }
assign $1\core_core_cr_in1[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in1 $1\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:195834.7-195834.33"
- process $proc$libresoc.v:195834$14029
+ attribute \src "libresoc.v:195730.7-195730.33"
+ process $proc$libresoc.v:195730$13821
assign { } { }
assign $1\core_core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:195838.13-195838.37"
- process $proc$libresoc.v:195838$14030
+ attribute \src "libresoc.v:195734.13-195734.37"
+ process $proc$libresoc.v:195734$13822
assign { } { }
assign $1\core_core_cr_in2[6:0] 7'0000000
sync always
sync init
update \core_core_cr_in2 $1\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:195840.13-195840.41"
- process $proc$libresoc.v:195840$14031
+ attribute \src "libresoc.v:195736.13-195736.41"
+ process $proc$libresoc.v:195736$13823
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$14032 7'0000000
+ assign $0\core_core_cr_in2$1[6:0]$13824 7'0000000
sync always
sync init
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14032
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13824
end
- attribute \src "libresoc.v:195846.7-195846.33"
- process $proc$libresoc.v:195846$14033
+ attribute \src "libresoc.v:195742.7-195742.33"
+ process $proc$libresoc.v:195742$13825
assign { } { }
assign $1\core_core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:195848.7-195848.37"
- process $proc$libresoc.v:195848$14034
+ attribute \src "libresoc.v:195744.7-195744.37"
+ process $proc$libresoc.v:195744$13826
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$14035 1'0
+ assign $0\core_core_cr_in2_ok$2[0:0]$13827 1'0
sync always
sync init
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14035
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13827
end
- attribute \src "libresoc.v:195854.13-195854.37"
- process $proc$libresoc.v:195854$14036
+ attribute \src "libresoc.v:195750.13-195750.37"
+ process $proc$libresoc.v:195750$13828
assign { } { }
assign $1\core_core_cr_out[6:0] 7'0000000
sync always
sync init
update \core_core_cr_out $1\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:195858.7-195858.32"
- process $proc$libresoc.v:195858$14037
+ attribute \src "libresoc.v:195754.7-195754.32"
+ process $proc$libresoc.v:195754$13829
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:195862.13-195862.38"
- process $proc$libresoc.v:195862$14038
+ attribute \src "libresoc.v:195758.13-195758.38"
+ process $proc$libresoc.v:195758$13830
assign { } { }
assign $1\core_core_dststep[6:0] 7'0000000
sync always
sync init
update \core_core_dststep $1\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:195866.13-195866.33"
- process $proc$libresoc.v:195866$14039
+ attribute \src "libresoc.v:195762.13-195762.33"
+ process $proc$libresoc.v:195762$13831
assign { } { }
assign $1\core_core_ea[6:0] 7'0000000
sync always
sync init
update \core_core_ea $1\core_core_ea[6:0]
end
- attribute \src "libresoc.v:195870.13-195870.35"
- process $proc$libresoc.v:195870$14040
+ attribute \src "libresoc.v:195766.13-195766.35"
+ process $proc$libresoc.v:195766$13832
assign { } { }
assign $1\core_core_fast1[2:0] 3'000
sync always
sync init
update \core_core_fast1 $1\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:195874.7-195874.32"
- process $proc$libresoc.v:195874$14041
+ attribute \src "libresoc.v:195770.7-195770.32"
+ process $proc$libresoc.v:195770$13833
assign { } { }
assign $1\core_core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_core_fast1_ok $1\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:195878.13-195878.35"
- process $proc$libresoc.v:195878$14042
+ attribute \src "libresoc.v:195774.13-195774.35"
+ process $proc$libresoc.v:195774$13834
assign { } { }
assign $1\core_core_fast2[2:0] 3'000
sync always
sync init
update \core_core_fast2 $1\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:195882.7-195882.32"
- process $proc$libresoc.v:195882$14043
+ attribute \src "libresoc.v:195778.7-195778.32"
+ process $proc$libresoc.v:195778$13835
assign { } { }
assign $1\core_core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_core_fast2_ok $1\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:195886.13-195886.36"
- process $proc$libresoc.v:195886$14044
+ attribute \src "libresoc.v:195782.13-195782.36"
+ process $proc$libresoc.v:195782$13836
assign { } { }
assign $1\core_core_fasto1[2:0] 3'000
sync always
sync init
update \core_core_fasto1 $1\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:195890.13-195890.36"
- process $proc$libresoc.v:195890$14045
+ attribute \src "libresoc.v:195786.13-195786.36"
+ process $proc$libresoc.v:195786$13837
assign { } { }
assign $1\core_core_fasto2[2:0] 3'000
sync always
sync init
update \core_core_fasto2 $1\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:195894.7-195894.26"
- process $proc$libresoc.v:195894$14046
+ attribute \src "libresoc.v:195790.7-195790.26"
+ process $proc$libresoc.v:195790$13838
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:195898.13-195898.36"
- process $proc$libresoc.v:195898$14047
+ attribute \src "libresoc.v:195794.13-195794.36"
+ process $proc$libresoc.v:195794$13839
assign { } { }
assign $1\core_core_maxvl[6:0] 7'0000000
sync always
sync init
update \core_core_maxvl $1\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:195902.14-195902.49"
- process $proc$libresoc.v:195902$14048
+ attribute \src "libresoc.v:195798.14-195798.49"
+ process $proc$libresoc.v:195798$13840
assign { } { }
assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_pc $1\core_core_pc[63:0]
end
- attribute \src "libresoc.v:195906.13-195906.35"
- process $proc$libresoc.v:195906$14049
+ attribute \src "libresoc.v:195802.13-195802.35"
+ process $proc$libresoc.v:195802$13841
assign { } { }
assign $1\core_core_reg1[6:0] 7'0000000
sync always
sync init
update \core_core_reg1 $1\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:195910.7-195910.31"
- process $proc$libresoc.v:195910$14050
+ attribute \src "libresoc.v:195806.7-195806.31"
+ process $proc$libresoc.v:195806$13842
assign { } { }
assign $1\core_core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_core_reg1_ok $1\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:195914.13-195914.35"
- process $proc$libresoc.v:195914$14051
+ attribute \src "libresoc.v:195810.13-195810.35"
+ process $proc$libresoc.v:195810$13843
assign { } { }
assign $1\core_core_reg2[6:0] 7'0000000
sync always
sync init
update \core_core_reg2 $1\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:195918.7-195918.31"
- process $proc$libresoc.v:195918$14052
+ attribute \src "libresoc.v:195814.7-195814.31"
+ process $proc$libresoc.v:195814$13844
assign { } { }
assign $1\core_core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_core_reg2_ok $1\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:195922.13-195922.35"
- process $proc$libresoc.v:195922$14053
+ attribute \src "libresoc.v:195818.13-195818.35"
+ process $proc$libresoc.v:195818$13845
assign { } { }
assign $1\core_core_reg3[6:0] 7'0000000
sync always
sync init
update \core_core_reg3 $1\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:195926.7-195926.31"
- process $proc$libresoc.v:195926$14054
+ attribute \src "libresoc.v:195822.7-195822.31"
+ process $proc$libresoc.v:195822$13846
assign { } { }
assign $1\core_core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_core_reg3_ok $1\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:195930.13-195930.35"
- process $proc$libresoc.v:195930$14055
+ attribute \src "libresoc.v:195826.13-195826.35"
+ process $proc$libresoc.v:195826$13847
assign { } { }
assign $1\core_core_rego[6:0] 7'0000000
sync always
sync init
update \core_core_rego $1\core_core_rego[6:0]
end
- attribute \src "libresoc.v:196048.13-196048.37"
- process $proc$libresoc.v:196048$14056
+ attribute \src "libresoc.v:195944.13-195944.37"
+ process $proc$libresoc.v:195944$13848
assign { } { }
assign $1\core_core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_core_spr1 $1\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:196052.7-196052.31"
- process $proc$libresoc.v:196052$14057
+ attribute \src "libresoc.v:195948.7-195948.31"
+ process $proc$libresoc.v:195948$13849
assign { } { }
assign $1\core_core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_core_spr1_ok $1\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:196170.13-196170.37"
- process $proc$libresoc.v:196170$14058
+ attribute \src "libresoc.v:196066.13-196066.37"
+ process $proc$libresoc.v:196066$13850
assign { } { }
assign $1\core_core_spro[9:0] 10'0000000000
sync always
sync init
update \core_core_spro $1\core_core_spro[9:0]
end
- attribute \src "libresoc.v:196174.13-196174.38"
- process $proc$libresoc.v:196174$14059
+ attribute \src "libresoc.v:196070.13-196070.38"
+ process $proc$libresoc.v:196070$13851
assign { } { }
assign $1\core_core_srcstep[6:0] 7'0000000
sync always
sync init
update \core_core_srcstep $1\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:196178.13-196178.35"
- process $proc$libresoc.v:196178$14060
+ attribute \src "libresoc.v:196074.13-196074.35"
+ process $proc$libresoc.v:196074$13852
assign { } { }
assign $1\core_core_subvl[1:0] 2'00
sync always
sync init
update \core_core_subvl $1\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:196182.13-196182.36"
- process $proc$libresoc.v:196182$14061
+ attribute \src "libresoc.v:196078.13-196078.36"
+ process $proc$libresoc.v:196078$13853
assign { } { }
assign $1\core_core_svstep[1:0] 2'00
sync always
sync init
update \core_core_svstep $1\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:196188.13-196188.33"
- process $proc$libresoc.v:196188$14062
+ attribute \src "libresoc.v:196084.13-196084.33"
+ process $proc$libresoc.v:196084$13854
assign { } { }
assign $1\core_core_vl[6:0] 7'0000000
sync always
sync init
update \core_core_vl $1\core_core_vl[6:0]
end
- attribute \src "libresoc.v:196192.13-196192.36"
- process $proc$libresoc.v:196192$14063
+ attribute \src "libresoc.v:196088.13-196088.36"
+ process $proc$libresoc.v:196088$13855
assign { } { }
assign $1\core_core_xer_in[2:0] 3'000
sync always
sync init
update \core_core_xer_in $1\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:196200.7-196200.28"
- process $proc$libresoc.v:196200$14064
+ attribute \src "libresoc.v:196096.7-196096.28"
+ process $proc$libresoc.v:196096$13856
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:196216.14-196216.45"
- process $proc$libresoc.v:196216$14065
+ attribute \src "libresoc.v:196112.14-196112.45"
+ process $proc$libresoc.v:196112$13857
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:196226.7-196226.24"
- process $proc$libresoc.v:196226$14066
+ attribute \src "libresoc.v:196122.7-196122.24"
+ process $proc$libresoc.v:196122$13858
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:196230.7-196230.23"
- process $proc$libresoc.v:196230$14067
+ attribute \src "libresoc.v:196126.7-196126.23"
+ process $proc$libresoc.v:196126$13859
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:196234.7-196234.28"
- process $proc$libresoc.v:196234$14068
+ attribute \src "libresoc.v:196130.7-196130.28"
+ process $proc$libresoc.v:196130$13860
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:196238.7-196238.28"
- process $proc$libresoc.v:196238$14069
+ attribute \src "libresoc.v:196134.7-196134.28"
+ process $proc$libresoc.v:196134$13861
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:196266.14-196266.45"
- process $proc$libresoc.v:196266$14070
+ attribute \src "libresoc.v:196162.14-196162.45"
+ process $proc$libresoc.v:196162$13862
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:196274.14-196274.37"
- process $proc$libresoc.v:196274$14071
+ attribute \src "libresoc.v:196170.14-196170.37"
+ process $proc$libresoc.v:196170$13863
assign { } { }
assign $1\core_raw_insn_i[31:0] 0
sync always
sync init
update \core_raw_insn_i $1\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:196278.7-196278.26"
- process $proc$libresoc.v:196278$14072
+ attribute \src "libresoc.v:196174.7-196174.26"
+ process $proc$libresoc.v:196174$13864
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:196282.7-196282.26"
- process $proc$libresoc.v:196282$14073
+ attribute \src "libresoc.v:196178.7-196178.26"
+ process $proc$libresoc.v:196178$13865
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:196294.7-196294.26"
- process $proc$libresoc.v:196294$14074
+ attribute \src "libresoc.v:196190.7-196190.26"
+ process $proc$libresoc.v:196190$13866
assign { } { }
assign $1\core_sv_a_nz[0:0] 1'0
sync always
sync init
update \core_sv_a_nz $1\core_sv_a_nz[0:0]
end
- attribute \src "libresoc.v:196304.7-196304.26"
- process $proc$libresoc.v:196304$14075
+ attribute \src "libresoc.v:196200.7-196200.26"
+ process $proc$libresoc.v:196200$13867
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:196310.7-196310.30"
- process $proc$libresoc.v:196310$14076
+ attribute \src "libresoc.v:196206.7-196206.30"
+ process $proc$libresoc.v:196206$13868
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:196316.13-196316.36"
- process $proc$libresoc.v:196316$14077
+ attribute \src "libresoc.v:196212.13-196212.36"
+ process $proc$libresoc.v:196212$13869
assign { } { }
assign $1\cur_cur_dststep[6:0] 7'0000000
sync always
sync init
update \cur_cur_dststep $1\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:196320.13-196320.34"
- process $proc$libresoc.v:196320$14078
+ attribute \src "libresoc.v:196216.13-196216.34"
+ process $proc$libresoc.v:196216$13870
assign { } { }
assign $1\cur_cur_maxvl[6:0] 7'0000000
sync always
sync init
update \cur_cur_maxvl $1\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:196324.13-196324.36"
- process $proc$libresoc.v:196324$14079
+ attribute \src "libresoc.v:196220.13-196220.36"
+ process $proc$libresoc.v:196220$13871
assign { } { }
assign $1\cur_cur_srcstep[6:0] 7'0000000
sync always
sync init
update \cur_cur_srcstep $1\cur_cur_srcstep[6:0]
end
- attribute \src "libresoc.v:196328.13-196328.33"
- process $proc$libresoc.v:196328$14080
+ attribute \src "libresoc.v:196224.13-196224.33"
+ process $proc$libresoc.v:196224$13872
assign { } { }
assign $1\cur_cur_subvl[1:0] 2'00
sync always
sync init
update \cur_cur_subvl $1\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:196332.13-196332.34"
- process $proc$libresoc.v:196332$14081
+ attribute \src "libresoc.v:196228.13-196228.34"
+ process $proc$libresoc.v:196228$13873
assign { } { }
assign $1\cur_cur_svstep[1:0] 2'00
sync always
sync init
update \cur_cur_svstep $1\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:196336.13-196336.31"
- process $proc$libresoc.v:196336$14082
+ attribute \src "libresoc.v:196232.13-196232.31"
+ process $proc$libresoc.v:196232$13874
assign { } { }
assign $1\cur_cur_vl[6:0] 7'0000000
sync always
sync init
update \cur_cur_vl $1\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:196340.7-196340.24"
- process $proc$libresoc.v:196340$14083
+ attribute \src "libresoc.v:196236.7-196236.24"
+ process $proc$libresoc.v:196236$13875
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:196344.7-196344.25"
- process $proc$libresoc.v:196344$14084
+ attribute \src "libresoc.v:196240.7-196240.25"
+ process $proc$libresoc.v:196240$13876
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:196348.7-196348.25"
- process $proc$libresoc.v:196348$14085
+ attribute \src "libresoc.v:196244.7-196244.25"
+ process $proc$libresoc.v:196244$13877
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:196396.13-196396.34"
- process $proc$libresoc.v:196396$14086
+ attribute \src "libresoc.v:196292.13-196292.34"
+ process $proc$libresoc.v:196292$13878
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:196400.14-196400.48"
- process $proc$libresoc.v:196400$14087
+ attribute \src "libresoc.v:196296.14-196296.48"
+ process $proc$libresoc.v:196296$13879
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:196406.7-196406.27"
- process $proc$libresoc.v:196406$14088
+ attribute \src "libresoc.v:196302.7-196302.27"
+ process $proc$libresoc.v:196302$13880
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:196410.7-196410.26"
- process $proc$libresoc.v:196410$14089
+ attribute \src "libresoc.v:196306.7-196306.26"
+ process $proc$libresoc.v:196306$13881
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:196464.14-196464.49"
- process $proc$libresoc.v:196464$14090
+ attribute \src "libresoc.v:196360.14-196360.49"
+ process $proc$libresoc.v:196360$13882
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:196468.7-196468.27"
- process $proc$libresoc.v:196468$14091
+ attribute \src "libresoc.v:196364.7-196364.27"
+ process $proc$libresoc.v:196364$13883
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:196472.14-196472.49"
- process $proc$libresoc.v:196472$14092
+ attribute \src "libresoc.v:196368.14-196368.49"
+ process $proc$libresoc.v:196368$13884
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:196476.14-196476.48"
- process $proc$libresoc.v:196476$14093
+ attribute \src "libresoc.v:196372.14-196372.48"
+ process $proc$libresoc.v:196372$13885
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:196628.14-196628.40"
- process $proc$libresoc.v:196628$14094
+ attribute \src "libresoc.v:196524.14-196524.40"
+ process $proc$libresoc.v:196524$13886
assign { } { }
assign $1\dec2_raw_opcode_in[31:0] 0
sync always
sync init
update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:196898.13-196898.25"
- process $proc$libresoc.v:196898$14095
+ attribute \src "libresoc.v:196794.13-196794.25"
+ process $proc$libresoc.v:196794$13887
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:196914.7-196914.28"
- process $proc$libresoc.v:196914$14096
+ attribute \src "libresoc.v:196810.7-196810.28"
+ process $proc$libresoc.v:196810$13888
assign { } { }
assign $1\exec_fsm_state[0:0] 1'0
sync always
sync init
update \exec_fsm_state $1\exec_fsm_state[0:0]
end
- attribute \src "libresoc.v:196926.13-196926.35"
- process $proc$libresoc.v:196926$14097
+ attribute \src "libresoc.v:196822.13-196822.35"
+ process $proc$libresoc.v:196822$13889
assign { } { }
assign $1\fetch_fsm_state[1:0] 2'00
sync always
sync init
update \fetch_fsm_state $1\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:196938.13-196938.29"
- process $proc$libresoc.v:196938$14098
+ attribute \src "libresoc.v:196834.13-196834.29"
+ process $proc$libresoc.v:196834$13890
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:197198.13-197198.35"
- process $proc$libresoc.v:197198$14099
+ attribute \src "libresoc.v:197094.13-197094.35"
+ process $proc$libresoc.v:197094$13891
assign { } { }
assign $1\issue_fsm_state[2:0] 3'000
sync always
sync init
update \issue_fsm_state $1\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:197202.7-197202.30"
- process $proc$libresoc.v:197202$14100
+ attribute \src "libresoc.v:197098.7-197098.30"
+ process $proc$libresoc.v:197098$13892
assign { } { }
assign $1\jtag_dmi0__ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:197210.14-197210.52"
- process $proc$libresoc.v:197210$14101
+ attribute \src "libresoc.v:197106.14-197106.52"
+ process $proc$libresoc.v:197106$13893
assign { } { }
assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:197250.7-197250.22"
- process $proc$libresoc.v:197250$14102
+ attribute \src "libresoc.v:197146.7-197146.22"
+ process $proc$libresoc.v:197146$13894
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:197290.14-197290.40"
- process $proc$libresoc.v:197290$14103
+ attribute \src "libresoc.v:197186.14-197186.40"
+ process $proc$libresoc.v:197186$13895
assign { } { }
assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \nia $1\nia[63:0]
end
- attribute \src "libresoc.v:197296.7-197296.24"
- process $proc$libresoc.v:197296$14104
+ attribute \src "libresoc.v:197192.7-197192.24"
+ process $proc$libresoc.v:197192$13896
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:197306.7-197306.25"
- process $proc$libresoc.v:197306$14105
+ attribute \src "libresoc.v:197202.7-197202.25"
+ process $proc$libresoc.v:197202$13897
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:197606.7-197606.24"
- process $proc$libresoc.v:197606$14106
+ attribute \src "libresoc.v:197502.7-197502.24"
+ process $proc$libresoc.v:197502$13898
assign { } { }
assign $1\sv_changed[0:0] 1'0
sync always
sync init
update \sv_changed $1\sv_changed[0:0]
end
- attribute \src "libresoc.v:197616.7-197616.30"
- process $proc$libresoc.v:197616$14107
+ attribute \src "libresoc.v:197512.7-197512.30"
+ process $proc$libresoc.v:197512$13899
assign { } { }
assign $1\svstate_ok_delay[0:0] 1'0
sync always
sync init
update \svstate_ok_delay $1\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:197753.3-197754.41"
- process $proc$libresoc.v:197753$13409
+ attribute \src "libresoc.v:197649.3-197650.41"
+ process $proc$libresoc.v:197649$13201
assign { } { }
assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
sync posedge \clk
update \dec2_cur_dec $0\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:197755.3-197756.41"
- process $proc$libresoc.v:197755$13410
+ attribute \src "libresoc.v:197651.3-197652.41"
+ process $proc$libresoc.v:197651$13202
assign { } { }
assign $0\core_core_pc[63:0] \core_core_pc$next
sync posedge \clk
update \core_core_pc $0\core_core_pc[63:0]
end
- attribute \src "libresoc.v:197757.3-197758.49"
- process $proc$libresoc.v:197757$13411
+ attribute \src "libresoc.v:197653.3-197654.49"
+ process $proc$libresoc.v:197653$13203
assign { } { }
assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
sync posedge \clk
update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:197759.3-197760.39"
- process $proc$libresoc.v:197759$13412
+ attribute \src "libresoc.v:197655.3-197656.39"
+ process $proc$libresoc.v:197655$13204
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
sync posedge \clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:197761.3-197762.41"
- process $proc$libresoc.v:197761$13413
+ attribute \src "libresoc.v:197657.3-197658.41"
+ process $proc$libresoc.v:197657$13205
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
sync posedge \clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:197763.3-197764.43"
- process $proc$libresoc.v:197763$13414
+ attribute \src "libresoc.v:197659.3-197660.43"
+ process $proc$libresoc.v:197659$13206
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
sync posedge \clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:197765.3-197766.45"
- process $proc$libresoc.v:197765$13415
+ attribute \src "libresoc.v:197661.3-197662.45"
+ process $proc$libresoc.v:197661$13207
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
sync posedge \clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:197767.3-197768.33"
- process $proc$libresoc.v:197767$13416
+ attribute \src "libresoc.v:197663.3-197664.33"
+ process $proc$libresoc.v:197663$13208
assign { } { }
assign $0\core_msr[63:0] \core_msr$next
sync posedge \clk
update \core_msr $0\core_msr[63:0]
end
- attribute \src "libresoc.v:197769.3-197770.35"
- process $proc$libresoc.v:197769$13417
+ attribute \src "libresoc.v:197665.3-197666.35"
+ process $proc$libresoc.v:197665$13209
assign { } { }
assign $0\core_eint[0:0] \core_eint$next
sync posedge \clk
update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:197771.3-197772.33"
- process $proc$libresoc.v:197771$13418
+ attribute \src "libresoc.v:197667.3-197668.33"
+ process $proc$libresoc.v:197667$13210
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
sync posedge \clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:197773.3-197774.49"
- process $proc$libresoc.v:197773$13419
+ attribute \src "libresoc.v:197669.3-197670.49"
+ process $proc$libresoc.v:197669$13211
assign { } { }
assign $0\core_core_svstep[1:0] \core_core_svstep$next
sync posedge \clk
update \core_core_svstep $0\core_core_svstep[1:0]
end
- attribute \src "libresoc.v:197775.3-197776.47"
- process $proc$libresoc.v:197775$13420
+ attribute \src "libresoc.v:197671.3-197672.47"
+ process $proc$libresoc.v:197671$13212
assign { } { }
assign $0\core_core_subvl[1:0] \core_core_subvl$next
sync posedge \clk
update \core_core_subvl $0\core_core_subvl[1:0]
end
- attribute \src "libresoc.v:197777.3-197778.51"
- process $proc$libresoc.v:197777$13421
+ attribute \src "libresoc.v:197673.3-197674.51"
+ process $proc$libresoc.v:197673$13213
assign { } { }
assign $0\core_core_dststep[6:0] \core_core_dststep$next
sync posedge \clk
update \core_core_dststep $0\core_core_dststep[6:0]
end
- attribute \src "libresoc.v:197779.3-197780.51"
- process $proc$libresoc.v:197779$13422
+ attribute \src "libresoc.v:197675.3-197676.51"
+ process $proc$libresoc.v:197675$13214
assign { } { }
assign $0\core_core_srcstep[6:0] \core_core_srcstep$next
sync posedge \clk
update \core_core_srcstep $0\core_core_srcstep[6:0]
end
- attribute \src "libresoc.v:197781.3-197782.41"
- process $proc$libresoc.v:197781$13423
+ attribute \src "libresoc.v:197677.3-197678.41"
+ process $proc$libresoc.v:197677$13215
assign { } { }
assign $0\core_core_vl[6:0] \core_core_vl$next
sync posedge \clk
update \core_core_vl $0\core_core_vl[6:0]
end
- attribute \src "libresoc.v:197783.3-197784.47"
- process $proc$libresoc.v:197783$13424
+ attribute \src "libresoc.v:197679.3-197680.47"
+ process $proc$libresoc.v:197679$13216
assign { } { }
assign $0\core_core_maxvl[6:0] \core_core_maxvl$next
sync posedge \clk
update \core_core_maxvl $0\core_core_maxvl[6:0]
end
- attribute \src "libresoc.v:197785.3-197786.35"
- process $proc$libresoc.v:197785$13425
+ attribute \src "libresoc.v:197681.3-197682.35"
+ process $proc$libresoc.v:197681$13217
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:197787.3-197788.41"
- process $proc$libresoc.v:197787$13426
+ attribute \src "libresoc.v:197683.3-197684.41"
+ process $proc$libresoc.v:197683$13218
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
sync posedge \clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:197789.3-197790.45"
- process $proc$libresoc.v:197789$13427
+ attribute \src "libresoc.v:197685.3-197686.45"
+ process $proc$libresoc.v:197685$13219
assign { } { }
assign $0\core_core_rego[6:0] \core_core_rego$next
sync posedge \clk
update \core_core_rego $0\core_core_rego[6:0]
end
- attribute \src "libresoc.v:197791.3-197792.41"
- process $proc$libresoc.v:197791$13428
+ attribute \src "libresoc.v:197687.3-197688.41"
+ process $proc$libresoc.v:197687$13220
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
sync posedge \clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:197793.3-197794.41"
- process $proc$libresoc.v:197793$13429
+ attribute \src "libresoc.v:197689.3-197690.41"
+ process $proc$libresoc.v:197689$13221
assign { } { }
assign $0\core_core_ea[6:0] \core_core_ea$next
sync posedge \clk
update \core_core_ea $0\core_core_ea[6:0]
end
- attribute \src "libresoc.v:197795.3-197796.37"
- process $proc$libresoc.v:197795$13430
+ attribute \src "libresoc.v:197691.3-197692.37"
+ process $proc$libresoc.v:197691$13222
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
sync posedge \clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:197797.3-197798.45"
- process $proc$libresoc.v:197797$13431
+ attribute \src "libresoc.v:197693.3-197694.45"
+ process $proc$libresoc.v:197693$13223
assign { } { }
assign $0\core_core_reg1[6:0] \core_core_reg1$next
sync posedge \clk
update \core_core_reg1 $0\core_core_reg1[6:0]
end
- attribute \src "libresoc.v:197799.3-197800.51"
- process $proc$libresoc.v:197799$13432
+ attribute \src "libresoc.v:197695.3-197696.51"
+ process $proc$libresoc.v:197695$13224
assign { } { }
assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next
sync posedge \clk
update \core_core_reg1_ok $0\core_core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:197801.3-197802.45"
- process $proc$libresoc.v:197801$13433
+ attribute \src "libresoc.v:197697.3-197698.45"
+ process $proc$libresoc.v:197697$13225
assign { } { }
assign $0\core_core_reg2[6:0] \core_core_reg2$next
sync posedge \clk
update \core_core_reg2 $0\core_core_reg2[6:0]
end
- attribute \src "libresoc.v:197803.3-197804.51"
- process $proc$libresoc.v:197803$13434
+ attribute \src "libresoc.v:197699.3-197700.51"
+ process $proc$libresoc.v:197699$13226
assign { } { }
assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next
sync posedge \clk
update \core_core_reg2_ok $0\core_core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:197805.3-197806.45"
- process $proc$libresoc.v:197805$13435
+ attribute \src "libresoc.v:197701.3-197702.45"
+ process $proc$libresoc.v:197701$13227
assign { } { }
assign $0\core_core_reg3[6:0] \core_core_reg3$next
sync posedge \clk
update \core_core_reg3 $0\core_core_reg3[6:0]
end
- attribute \src "libresoc.v:197807.3-197808.39"
- process $proc$libresoc.v:197807$13436
+ attribute \src "libresoc.v:197703.3-197704.39"
+ process $proc$libresoc.v:197703$13228
assign { } { }
assign $0\d_xer_delay[0:0] \d_xer_delay$next
sync posedge \clk
update \d_xer_delay $0\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:197809.3-197810.51"
- process $proc$libresoc.v:197809$13437
+ attribute \src "libresoc.v:197705.3-197706.51"
+ process $proc$libresoc.v:197705$13229
assign { } { }
assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next
sync posedge \clk
update \core_core_reg3_ok $0\core_core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:197811.3-197812.45"
- process $proc$libresoc.v:197811$13438
+ attribute \src "libresoc.v:197707.3-197708.45"
+ process $proc$libresoc.v:197707$13230
assign { } { }
assign $0\core_core_spro[9:0] \core_core_spro$next
sync posedge \clk
update \core_core_spro $0\core_core_spro[9:0]
end
- attribute \src "libresoc.v:197813.3-197814.41"
- process $proc$libresoc.v:197813$13439
+ attribute \src "libresoc.v:197709.3-197710.41"
+ process $proc$libresoc.v:197709$13231
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
sync posedge \clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:197815.3-197816.45"
- process $proc$libresoc.v:197815$13440
+ attribute \src "libresoc.v:197711.3-197712.45"
+ process $proc$libresoc.v:197711$13232
assign { } { }
assign $0\core_core_spr1[9:0] \core_core_spr1$next
sync posedge \clk
update \core_core_spr1 $0\core_core_spr1[9:0]
end
- attribute \src "libresoc.v:197817.3-197818.51"
- process $proc$libresoc.v:197817$13441
+ attribute \src "libresoc.v:197713.3-197714.51"
+ process $proc$libresoc.v:197713$13233
assign { } { }
assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next
sync posedge \clk
update \core_core_spr1_ok $0\core_core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:197819.3-197820.49"
- process $proc$libresoc.v:197819$13442
+ attribute \src "libresoc.v:197715.3-197716.49"
+ process $proc$libresoc.v:197715$13234
assign { } { }
assign $0\core_core_xer_in[2:0] \core_core_xer_in$next
sync posedge \clk
update \core_core_xer_in $0\core_core_xer_in[2:0]
end
- attribute \src "libresoc.v:197821.3-197822.41"
- process $proc$libresoc.v:197821$13443
+ attribute \src "libresoc.v:197717.3-197718.41"
+ process $proc$libresoc.v:197717$13235
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
sync posedge \clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:197823.3-197824.47"
- process $proc$libresoc.v:197823$13444
+ attribute \src "libresoc.v:197719.3-197720.47"
+ process $proc$libresoc.v:197719$13236
assign { } { }
assign $0\core_core_fast1[2:0] \core_core_fast1$next
sync posedge \clk
update \core_core_fast1 $0\core_core_fast1[2:0]
end
- attribute \src "libresoc.v:197825.3-197826.53"
- process $proc$libresoc.v:197825$13445
+ attribute \src "libresoc.v:197721.3-197722.53"
+ process $proc$libresoc.v:197721$13237
assign { } { }
assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next
sync posedge \clk
update \core_core_fast1_ok $0\core_core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:197827.3-197828.47"
- process $proc$libresoc.v:197827$13446
+ attribute \src "libresoc.v:197723.3-197724.47"
+ process $proc$libresoc.v:197723$13238
assign { } { }
assign $0\core_core_fast2[2:0] \core_core_fast2$next
sync posedge \clk
update \core_core_fast2 $0\core_core_fast2[2:0]
end
- attribute \src "libresoc.v:197829.3-197830.37"
- process $proc$libresoc.v:197829$13447
+ attribute \src "libresoc.v:197725.3-197726.37"
+ process $proc$libresoc.v:197725$13239
assign { } { }
assign $0\d_cr_delay[0:0] \d_cr_delay$next
sync posedge \clk
update \d_cr_delay $0\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:197831.3-197832.53"
- process $proc$libresoc.v:197831$13448
+ attribute \src "libresoc.v:197727.3-197728.53"
+ process $proc$libresoc.v:197727$13240
assign { } { }
assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next
sync posedge \clk
update \core_core_fast2_ok $0\core_core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:197833.3-197834.49"
- process $proc$libresoc.v:197833$13449
+ attribute \src "libresoc.v:197729.3-197730.49"
+ process $proc$libresoc.v:197729$13241
assign { } { }
assign $0\core_core_fasto1[2:0] \core_core_fasto1$next
sync posedge \clk
update \core_core_fasto1 $0\core_core_fasto1[2:0]
end
- attribute \src "libresoc.v:197835.3-197836.45"
- process $proc$libresoc.v:197835$13450
+ attribute \src "libresoc.v:197731.3-197732.45"
+ process $proc$libresoc.v:197731$13242
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
sync posedge \clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:197837.3-197838.49"
- process $proc$libresoc.v:197837$13451
+ attribute \src "libresoc.v:197733.3-197734.49"
+ process $proc$libresoc.v:197733$13243
assign { } { }
assign $0\core_core_fasto2[2:0] \core_core_fasto2$next
sync posedge \clk
update \core_core_fasto2 $0\core_core_fasto2[2:0]
end
- attribute \src "libresoc.v:197839.3-197840.45"
- process $proc$libresoc.v:197839$13452
+ attribute \src "libresoc.v:197735.3-197736.45"
+ process $proc$libresoc.v:197735$13244
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
sync posedge \clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:197841.3-197842.49"
- process $proc$libresoc.v:197841$13453
+ attribute \src "libresoc.v:197737.3-197738.49"
+ process $proc$libresoc.v:197737$13245
assign { } { }
assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next
sync posedge \clk
update \core_core_cr_in1 $0\core_core_cr_in1[6:0]
end
- attribute \src "libresoc.v:197843.3-197844.55"
- process $proc$libresoc.v:197843$13454
+ attribute \src "libresoc.v:197739.3-197740.55"
+ process $proc$libresoc.v:197739$13246
assign { } { }
assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next
sync posedge \clk
update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:197845.3-197846.49"
- process $proc$libresoc.v:197845$13455
+ attribute \src "libresoc.v:197741.3-197742.49"
+ process $proc$libresoc.v:197741$13247
assign { } { }
assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next
sync posedge \clk
update \core_core_cr_in2 $0\core_core_cr_in2[6:0]
end
- attribute \src "libresoc.v:197847.3-197848.55"
- process $proc$libresoc.v:197847$13456
+ attribute \src "libresoc.v:197743.3-197744.55"
+ process $proc$libresoc.v:197743$13248
assign { } { }
assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next
sync posedge \clk
update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:197849.3-197850.55"
- process $proc$libresoc.v:197849$13457
+ attribute \src "libresoc.v:197745.3-197746.55"
+ process $proc$libresoc.v:197745$13249
assign { } { }
- assign $0\core_core_cr_in2$1[6:0]$13458 \core_core_cr_in2$1$next
+ assign $0\core_core_cr_in2$1[6:0]$13250 \core_core_cr_in2$1$next
sync posedge \clk
- update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13458
+ update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13250
end
- attribute \src "libresoc.v:197851.3-197852.39"
- process $proc$libresoc.v:197851$13459
+ attribute \src "libresoc.v:197747.3-197748.39"
+ process $proc$libresoc.v:197747$13251
assign { } { }
assign $0\d_reg_delay[0:0] \d_reg_delay$next
sync posedge \clk
update \d_reg_delay $0\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:197853.3-197854.61"
- process $proc$libresoc.v:197853$13460
+ attribute \src "libresoc.v:197749.3-197750.61"
+ process $proc$libresoc.v:197749$13252
assign { } { }
- assign $0\core_core_cr_in2_ok$2[0:0]$13461 \core_core_cr_in2_ok$2$next
+ assign $0\core_core_cr_in2_ok$2[0:0]$13253 \core_core_cr_in2_ok$2$next
sync posedge \clk
- update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13461
+ update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13253
end
- attribute \src "libresoc.v:197855.3-197856.49"
- process $proc$libresoc.v:197855$13462
+ attribute \src "libresoc.v:197751.3-197752.49"
+ process $proc$libresoc.v:197751$13254
assign { } { }
assign $0\core_core_cr_out[6:0] \core_core_cr_out$next
sync posedge \clk
update \core_core_cr_out $0\core_core_cr_out[6:0]
end
- attribute \src "libresoc.v:197857.3-197858.45"
- process $proc$libresoc.v:197857$13463
+ attribute \src "libresoc.v:197753.3-197754.45"
+ process $proc$libresoc.v:197753$13255
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
sync posedge \clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:197859.3-197860.53"
- process $proc$libresoc.v:197859$13464
+ attribute \src "libresoc.v:197755.3-197756.53"
+ process $proc$libresoc.v:197755$13256
assign { } { }
assign $0\core_core_core_msr[63:0] \core_core_core_msr$next
sync posedge \clk
update \core_core_core_msr $0\core_core_core_msr[63:0]
end
- attribute \src "libresoc.v:197861.3-197862.53"
- process $proc$libresoc.v:197861$13465
+ attribute \src "libresoc.v:197757.3-197758.53"
+ process $proc$libresoc.v:197757$13257
assign { } { }
assign $0\core_core_core_cia[63:0] \core_core_core_cia$next
sync posedge \clk
update \core_core_core_cia $0\core_core_core_cia[63:0]
end
- attribute \src "libresoc.v:197863.3-197864.55"
- process $proc$libresoc.v:197863$13466
+ attribute \src "libresoc.v:197759.3-197760.55"
+ process $proc$libresoc.v:197759$13258
assign { } { }
assign $0\core_core_core_insn[31:0] \core_core_core_insn$next
sync posedge \clk
update \core_core_core_insn $0\core_core_core_insn[31:0]
end
- attribute \src "libresoc.v:197865.3-197866.65"
- process $proc$libresoc.v:197865$13467
+ attribute \src "libresoc.v:197761.3-197762.65"
+ process $proc$libresoc.v:197761$13259
assign { } { }
assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next
sync posedge \clk
update \core_core_core_insn_type $0\core_core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:197867.3-197868.61"
- process $proc$libresoc.v:197867$13468
+ attribute \src "libresoc.v:197763.3-197764.61"
+ process $proc$libresoc.v:197763$13260
assign { } { }
assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next
sync posedge \clk
update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0]
end
- attribute \src "libresoc.v:197869.3-197870.41"
- process $proc$libresoc.v:197869$13469
+ attribute \src "libresoc.v:197765.3-197766.41"
+ process $proc$libresoc.v:197765$13261
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
sync posedge \clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:197871.3-197872.51"
- process $proc$libresoc.v:197871$13470
+ attribute \src "libresoc.v:197767.3-197768.51"
+ process $proc$libresoc.v:197767$13262
assign { } { }
assign $0\core_core_core_rc[0:0] \core_core_core_rc$next
sync posedge \clk
update \core_core_core_rc $0\core_core_core_rc[0:0]
end
- attribute \src "libresoc.v:197873.3-197874.45"
- process $proc$libresoc.v:197873$13471
+ attribute \src "libresoc.v:197769.3-197770.45"
+ process $proc$libresoc.v:197769$13263
assign { } { }
assign $0\exec_fsm_state[0:0] \exec_fsm_state$next
sync posedge \clk
update \exec_fsm_state $0\exec_fsm_state[0:0]
end
- attribute \src "libresoc.v:197875.3-197876.57"
- process $proc$libresoc.v:197875$13472
+ attribute \src "libresoc.v:197771.3-197772.57"
+ process $proc$libresoc.v:197771$13264
assign { } { }
assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next
sync posedge \clk
update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:197877.3-197878.51"
- process $proc$libresoc.v:197877$13473
+ attribute \src "libresoc.v:197773.3-197774.51"
+ process $proc$libresoc.v:197773$13265
assign { } { }
assign $0\core_core_core_oe[0:0] \core_core_core_oe$next
sync posedge \clk
update \core_core_core_oe $0\core_core_core_oe[0:0]
end
- attribute \src "libresoc.v:197879.3-197880.57"
- process $proc$libresoc.v:197879$13474
+ attribute \src "libresoc.v:197775.3-197776.57"
+ process $proc$libresoc.v:197775$13266
assign { } { }
assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next
sync posedge \clk
update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:197881.3-197882.69"
- process $proc$libresoc.v:197881$13475
+ attribute \src "libresoc.v:197777.3-197778.69"
+ process $proc$libresoc.v:197777$13267
assign { } { }
assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next
sync posedge \clk
update \core_core_core_input_carry $0\core_core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:197883.3-197884.63"
- process $proc$libresoc.v:197883$13476
+ attribute \src "libresoc.v:197779.3-197780.63"
+ process $proc$libresoc.v:197779$13268
assign { } { }
assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next
sync posedge \clk
update \core_core_core_traptype $0\core_core_core_traptype[7:0]
end
- attribute \src "libresoc.v:197885.3-197886.71"
- process $proc$libresoc.v:197885$13477
+ attribute \src "libresoc.v:197781.3-197782.71"
+ process $proc$libresoc.v:197781$13269
assign { } { }
- assign $0\core_core_core_exc_$signal[0:0]$13478 \core_core_core_exc_$signal$next
+ assign $0\core_core_core_exc_$signal[0:0]$13270 \core_core_core_exc_$signal$next
sync posedge \clk
- update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13478
+ update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13270
end
- attribute \src "libresoc.v:197887.3-197888.75"
- process $proc$libresoc.v:197887$13479
+ attribute \src "libresoc.v:197783.3-197784.75"
+ process $proc$libresoc.v:197783$13271
assign { } { }
- assign $0\core_core_core_exc_$signal$3[0:0]$13480 \core_core_core_exc_$signal$3$next
+ assign $0\core_core_core_exc_$signal$3[0:0]$13272 \core_core_core_exc_$signal$3$next
sync posedge \clk
- update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13480
+ update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13272
end
- attribute \src "libresoc.v:197889.3-197890.75"
- process $proc$libresoc.v:197889$13481
+ attribute \src "libresoc.v:197785.3-197786.75"
+ process $proc$libresoc.v:197785$13273
assign { } { }
- assign $0\core_core_core_exc_$signal$4[0:0]$13482 \core_core_core_exc_$signal$4$next
+ assign $0\core_core_core_exc_$signal$4[0:0]$13274 \core_core_core_exc_$signal$4$next
sync posedge \clk
- update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13482
+ update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13274
end
- attribute \src "libresoc.v:197891.3-197892.75"
- process $proc$libresoc.v:197891$13483
+ attribute \src "libresoc.v:197787.3-197788.75"
+ process $proc$libresoc.v:197787$13275
assign { } { }
- assign $0\core_core_core_exc_$signal$5[0:0]$13484 \core_core_core_exc_$signal$5$next
+ assign $0\core_core_core_exc_$signal$5[0:0]$13276 \core_core_core_exc_$signal$5$next
sync posedge \clk
- update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13484
+ update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13276
end
- attribute \src "libresoc.v:197893.3-197894.75"
- process $proc$libresoc.v:197893$13485
+ attribute \src "libresoc.v:197789.3-197790.75"
+ process $proc$libresoc.v:197789$13277
assign { } { }
- assign $0\core_core_core_exc_$signal$6[0:0]$13486 \core_core_core_exc_$signal$6$next
+ assign $0\core_core_core_exc_$signal$6[0:0]$13278 \core_core_core_exc_$signal$6$next
sync posedge \clk
- update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13486
+ update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13278
end
- attribute \src "libresoc.v:197895.3-197896.41"
- process $proc$libresoc.v:197895$13487
+ attribute \src "libresoc.v:197791.3-197792.41"
+ process $proc$libresoc.v:197791$13279
assign { } { }
assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next
sync posedge \clk
update \core_sv_a_nz $0\core_sv_a_nz[0:0]
end
- attribute \src "libresoc.v:197897.3-197898.75"
- process $proc$libresoc.v:197897$13488
+ attribute \src "libresoc.v:197793.3-197794.75"
+ process $proc$libresoc.v:197793$13280
assign { } { }
- assign $0\core_core_core_exc_$signal$7[0:0]$13489 \core_core_core_exc_$signal$7$next
+ assign $0\core_core_core_exc_$signal$7[0:0]$13281 \core_core_core_exc_$signal$7$next
sync posedge \clk
- update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13489
+ update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13281
end
- attribute \src "libresoc.v:197899.3-197900.75"
- process $proc$libresoc.v:197899$13490
+ attribute \src "libresoc.v:197795.3-197796.75"
+ process $proc$libresoc.v:197795$13282
assign { } { }
- assign $0\core_core_core_exc_$signal$8[0:0]$13491 \core_core_core_exc_$signal$8$next
+ assign $0\core_core_core_exc_$signal$8[0:0]$13283 \core_core_core_exc_$signal$8$next
sync posedge \clk
- update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13491
+ update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13283
end
- attribute \src "libresoc.v:197901.3-197902.75"
- process $proc$libresoc.v:197901$13492
+ attribute \src "libresoc.v:197797.3-197798.75"
+ process $proc$libresoc.v:197797$13284
assign { } { }
- assign $0\core_core_core_exc_$signal$9[0:0]$13493 \core_core_core_exc_$signal$9$next
+ assign $0\core_core_core_exc_$signal$9[0:0]$13285 \core_core_core_exc_$signal$9$next
sync posedge \clk
- update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13493
+ update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13285
end
- attribute \src "libresoc.v:197903.3-197904.63"
- process $proc$libresoc.v:197903$13494
+ attribute \src "libresoc.v:197799.3-197800.63"
+ process $proc$libresoc.v:197799$13286
assign { } { }
assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next
sync posedge \clk
update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:197905.3-197906.57"
- process $proc$libresoc.v:197905$13495
+ attribute \src "libresoc.v:197801.3-197802.57"
+ process $proc$libresoc.v:197801$13287
assign { } { }
assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next
sync posedge \clk
update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:197907.3-197908.63"
- process $proc$libresoc.v:197907$13496
+ attribute \src "libresoc.v:197803.3-197804.63"
+ process $proc$libresoc.v:197803$13288
assign { } { }
assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next
sync posedge \clk
update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:197909.3-197910.57"
- process $proc$libresoc.v:197909$13497
+ attribute \src "libresoc.v:197805.3-197806.57"
+ process $proc$libresoc.v:197805$13289
assign { } { }
assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next
sync posedge \clk
update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:197911.3-197912.53"
- process $proc$libresoc.v:197911$13498
+ attribute \src "libresoc.v:197807.3-197808.53"
+ process $proc$libresoc.v:197807$13290
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
sync posedge \clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:197913.3-197914.63"
- process $proc$libresoc.v:197913$13499
+ attribute \src "libresoc.v:197809.3-197810.63"
+ process $proc$libresoc.v:197809$13291
assign { } { }
assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next
sync posedge \clk
update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:197915.3-197916.37"
- process $proc$libresoc.v:197915$13500
+ attribute \src "libresoc.v:197811.3-197812.37"
+ process $proc$libresoc.v:197811$13292
assign { } { }
assign $0\sv_changed[0:0] \sv_changed$next
sync posedge \clk
update \sv_changed $0\sv_changed[0:0]
end
- attribute \src "libresoc.v:197917.3-197918.57"
- process $proc$libresoc.v:197917$13501
+ attribute \src "libresoc.v:197813.3-197814.57"
+ process $proc$libresoc.v:197813$13293
assign { } { }
- assign $0\core_bigendian_i$10[0:0]$13502 \core_bigendian_i$10$next
+ assign $0\core_bigendian_i$10[0:0]$13294 \core_bigendian_i$10$next
sync posedge \clk
- update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13502
+ update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13294
end
- attribute \src "libresoc.v:197919.3-197920.37"
- process $proc$libresoc.v:197919$13503
+ attribute \src "libresoc.v:197815.3-197816.37"
+ process $proc$libresoc.v:197815$13295
assign { } { }
assign $0\pc_changed[0:0] \pc_changed$next
sync posedge \clk
update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:197921.3-197922.47"
- process $proc$libresoc.v:197921$13504
+ attribute \src "libresoc.v:197817.3-197818.47"
+ process $proc$libresoc.v:197817$13296
assign { } { }
assign $0\issue_fsm_state[2:0] \issue_fsm_state$next
sync posedge \clk
update \issue_fsm_state $0\issue_fsm_state[2:0]
end
- attribute \src "libresoc.v:197923.3-197924.53"
- process $proc$libresoc.v:197923$13505
+ attribute \src "libresoc.v:197819.3-197820.53"
+ process $proc$libresoc.v:197819$13297
assign { } { }
assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next
sync posedge \clk
update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:197925.3-197926.23"
- process $proc$libresoc.v:197925$13506
+ attribute \src "libresoc.v:197821.3-197822.23"
+ process $proc$libresoc.v:197821$13298
assign { } { }
assign $0\nia[63:0] \nia$next
sync posedge \clk
update \nia $0\nia[63:0]
end
- attribute \src "libresoc.v:197927.3-197928.41"
- process $proc$libresoc.v:197927$13507
+ attribute \src "libresoc.v:197823.3-197824.41"
+ process $proc$libresoc.v:197823$13299
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
sync posedge \clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:197929.3-197930.47"
- process $proc$libresoc.v:197929$13508
+ attribute \src "libresoc.v:197825.3-197826.47"
+ process $proc$libresoc.v:197825$13300
assign { } { }
assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next
sync posedge \clk
update \fetch_fsm_state $0\fetch_fsm_state[1:0]
end
- attribute \src "libresoc.v:197931.3-197932.33"
- process $proc$libresoc.v:197931$13509
+ attribute \src "libresoc.v:197827.3-197828.33"
+ process $proc$libresoc.v:197827$13301
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
sync posedge \clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:197933.3-197934.45"
- process $proc$libresoc.v:197933$13510
+ attribute \src "libresoc.v:197829.3-197830.45"
+ process $proc$libresoc.v:197829$13302
assign { } { }
assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next
sync posedge \clk
update \cur_cur_svstep $0\cur_cur_svstep[1:0]
end
- attribute \src "libresoc.v:197935.3-197936.43"
- process $proc$libresoc.v:197935$13511
+ attribute \src "libresoc.v:197831.3-197832.43"
+ process $proc$libresoc.v:197831$13303
assign { } { }
assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next
sync posedge \clk
update \cur_cur_subvl $0\cur_cur_subvl[1:0]
end
- attribute \src "libresoc.v:197937.3-197938.47"
- process $proc$libresoc.v:197937$13512
+ attribute \src "libresoc.v:197833.3-197834.47"
+ process $proc$libresoc.v:197833$13304
assign { } { }
assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next
sync posedge \clk
update \cur_cur_dststep $0\cur_cur_dststep[6:0]
end
- attribute \src "libresoc.v:197939.3-197940.47"
- process $proc$libresoc.v:197939$13513
+ attribute \src "libresoc.v:197835.3-197836.47"
+ process $proc$libresoc.v:197835$13305
assign { } { }
assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next
sync posedge \clk
update \core_raw_insn_i $0\core_raw_insn_i[31:0]
end
- attribute \src "libresoc.v:197941.3-197942.47"
- process $proc$libresoc.v:197941$13514
+ attribute \src "libresoc.v:197837.3-197838.47"
+ process $proc$libresoc.v:197837$13306
assign { } { }
assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next
sync posedge \clk
update \cur_cur_srcstep $0\cur_cur_srcstep[6:0]
end
- attribute \src "libresoc.v:197943.3-197944.37"
- process $proc$libresoc.v:197943$13515
+ attribute \src "libresoc.v:197839.3-197840.37"
+ process $proc$libresoc.v:197839$13307
assign { } { }
assign $0\cur_cur_vl[6:0] \cur_cur_vl$next
sync posedge \clk
update \cur_cur_vl $0\cur_cur_vl[6:0]
end
- attribute \src "libresoc.v:197945.3-197946.43"
- process $proc$libresoc.v:197945$13516
+ attribute \src "libresoc.v:197841.3-197842.43"
+ process $proc$libresoc.v:197841$13308
assign { } { }
assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next
sync posedge \clk
update \cur_cur_maxvl $0\cur_cur_maxvl[6:0]
end
- attribute \src "libresoc.v:197947.3-197948.39"
- process $proc$libresoc.v:197947$13517
+ attribute \src "libresoc.v:197843.3-197844.39"
+ process $proc$libresoc.v:197843$13309
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
sync posedge \clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:197949.3-197950.49"
- process $proc$libresoc.v:197949$13518
+ attribute \src "libresoc.v:197845.3-197846.49"
+ process $proc$libresoc.v:197845$13310
assign { } { }
assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next
sync posedge \clk
update \svstate_ok_delay $0\svstate_ok_delay[0:0]
end
- attribute \src "libresoc.v:197951.3-197952.39"
- process $proc$libresoc.v:197951$13519
+ attribute \src "libresoc.v:197847.3-197848.39"
+ process $proc$libresoc.v:197847$13311
assign { } { }
assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
sync posedge \clk
update \pc_ok_delay $0\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:197953.3-197954.43"
- process $proc$libresoc.v:197953$13520
+ attribute \src "libresoc.v:197849.3-197850.43"
+ process $proc$libresoc.v:197849$13312
assign { } { }
assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o
sync posedge \clk
update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:197955.3-197956.27"
- process $proc$libresoc.v:197955$13521
+ attribute \src "libresoc.v:197851.3-197852.27"
+ process $proc$libresoc.v:197851$13313
assign { } { }
assign $0\delay[1:0] \delay$next
sync posedge \por_clk
update \delay $0\delay[1:0]
end
- attribute \src "libresoc.v:197957.3-197958.43"
- process $proc$libresoc.v:197957$13522
+ attribute \src "libresoc.v:197853.3-197854.43"
+ process $proc$libresoc.v:197853$13314
assign { } { }
assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
sync posedge \clk
update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:197959.3-197960.47"
- process $proc$libresoc.v:197959$13523
+ attribute \src "libresoc.v:197855.3-197856.47"
+ process $proc$libresoc.v:197855$13315
assign { } { }
assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
sync posedge \clk
update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:198490.3-198498.6"
- process $proc$libresoc.v:198490$13524
+ attribute \src "libresoc.v:198386.3-198394.6"
+ process $proc$libresoc.v:198386$13316
assign { } { }
assign { } { }
- assign $0\dbg_dmi_addr_i$next[3:0]$13525 $1\dbg_dmi_addr_i$next[3:0]$13526
- attribute \src "libresoc.v:198491.5-198491.29"
+ assign $0\dbg_dmi_addr_i$next[3:0]$13317 $1\dbg_dmi_addr_i$next[3:0]$13318
+ attribute \src "libresoc.v:198387.5-198387.29"
switch \initial
- attribute \src "libresoc.v:198491.9-198491.17"
+ attribute \src "libresoc.v:198387.9-198387.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_addr_i$next[3:0]$13526 4'0000
+ assign $1\dbg_dmi_addr_i$next[3:0]$13318 4'0000
case
- assign $1\dbg_dmi_addr_i$next[3:0]$13526 \jtag_dmi0__addr_i
+ assign $1\dbg_dmi_addr_i$next[3:0]$13318 \jtag_dmi0__addr_i
end
sync always
- update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13525
+ update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13317
end
- attribute \src "libresoc.v:198499.3-198507.6"
- process $proc$libresoc.v:198499$13527
+ attribute \src "libresoc.v:198395.3-198403.6"
+ process $proc$libresoc.v:198395$13319
assign { } { }
assign { } { }
- assign $0\dbg_dmi_req_i$next[0:0]$13528 $1\dbg_dmi_req_i$next[0:0]$13529
- attribute \src "libresoc.v:198500.5-198500.29"
+ assign $0\dbg_dmi_req_i$next[0:0]$13320 $1\dbg_dmi_req_i$next[0:0]$13321
+ attribute \src "libresoc.v:198396.5-198396.29"
switch \initial
- attribute \src "libresoc.v:198500.9-198500.17"
+ attribute \src "libresoc.v:198396.9-198396.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_req_i$next[0:0]$13529 1'0
+ assign $1\dbg_dmi_req_i$next[0:0]$13321 1'0
case
- assign $1\dbg_dmi_req_i$next[0:0]$13529 \jtag_dmi0__req_i
+ assign $1\dbg_dmi_req_i$next[0:0]$13321 \jtag_dmi0__req_i
end
sync always
- update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13528
+ update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13320
end
- attribute \src "libresoc.v:198508.3-198572.6"
- process $proc$libresoc.v:198508$13530
+ attribute \src "libresoc.v:198404.3-198468.6"
+ process $proc$libresoc.v:198404$13322
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_dststep$next[6:0]$13531 $3\core_core_dststep$next[6:0]$13561
- assign $0\core_core_maxvl$next[6:0]$13532 $3\core_core_maxvl$next[6:0]$13562
- assign $0\core_core_pc$next[63:0]$13533 $3\core_core_pc$next[63:0]$13563
- assign $0\core_core_srcstep$next[6:0]$13534 $3\core_core_srcstep$next[6:0]$13564
- assign $0\core_core_subvl$next[1:0]$13535 $3\core_core_subvl$next[1:0]$13565
- assign $0\core_core_svstep$next[1:0]$13536 $3\core_core_svstep$next[1:0]$13566
- assign $0\core_core_vl$next[6:0]$13537 $3\core_core_vl$next[6:0]$13567
- assign $0\core_dec$next[63:0]$13538 $3\core_dec$next[63:0]$13568
- assign $0\core_eint$next[0:0]$13539 $3\core_eint$next[0:0]$13569
- assign $0\core_msr$next[63:0]$13540 $3\core_msr$next[63:0]$13570
- attribute \src "libresoc.v:198509.5-198509.29"
+ assign $0\core_core_dststep$next[6:0]$13323 $3\core_core_dststep$next[6:0]$13353
+ assign $0\core_core_maxvl$next[6:0]$13324 $3\core_core_maxvl$next[6:0]$13354
+ assign $0\core_core_pc$next[63:0]$13325 $3\core_core_pc$next[63:0]$13355
+ assign $0\core_core_srcstep$next[6:0]$13326 $3\core_core_srcstep$next[6:0]$13356
+ assign $0\core_core_subvl$next[1:0]$13327 $3\core_core_subvl$next[1:0]$13357
+ assign $0\core_core_svstep$next[1:0]$13328 $3\core_core_svstep$next[1:0]$13358
+ assign $0\core_core_vl$next[6:0]$13329 $3\core_core_vl$next[6:0]$13359
+ assign $0\core_dec$next[63:0]$13330 $3\core_dec$next[63:0]$13360
+ assign $0\core_eint$next[0:0]$13331 $3\core_eint$next[0:0]$13361
+ assign $0\core_msr$next[63:0]$13332 $3\core_msr$next[63:0]$13362
+ attribute \src "libresoc.v:198405.5-198405.29"
switch \initial
- attribute \src "libresoc.v:198509.9-198509.17"
+ attribute \src "libresoc.v:198405.9-198405.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_core_dststep$next[6:0]$13541 $2\core_core_dststep$next[6:0]$13551
- assign $1\core_core_maxvl$next[6:0]$13542 $2\core_core_maxvl$next[6:0]$13552
- assign $1\core_core_pc$next[63:0]$13543 $2\core_core_pc$next[63:0]$13553
- assign $1\core_core_srcstep$next[6:0]$13544 $2\core_core_srcstep$next[6:0]$13554
- assign $1\core_core_subvl$next[1:0]$13545 $2\core_core_subvl$next[1:0]$13555
- assign $1\core_core_svstep$next[1:0]$13546 $2\core_core_svstep$next[1:0]$13556
- assign $1\core_core_vl$next[6:0]$13547 $2\core_core_vl$next[6:0]$13557
- assign $1\core_dec$next[63:0]$13548 $2\core_dec$next[63:0]$13558
- assign $1\core_eint$next[0:0]$13549 $2\core_eint$next[0:0]$13559
- assign $1\core_msr$next[63:0]$13550 $2\core_msr$next[63:0]$13560
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\core_core_dststep$next[6:0]$13333 $2\core_core_dststep$next[6:0]$13343
+ assign $1\core_core_maxvl$next[6:0]$13334 $2\core_core_maxvl$next[6:0]$13344
+ assign $1\core_core_pc$next[63:0]$13335 $2\core_core_pc$next[63:0]$13345
+ assign $1\core_core_srcstep$next[6:0]$13336 $2\core_core_srcstep$next[6:0]$13346
+ assign $1\core_core_subvl$next[1:0]$13337 $2\core_core_subvl$next[1:0]$13347
+ assign $1\core_core_svstep$next[1:0]$13338 $2\core_core_svstep$next[1:0]$13348
+ assign $1\core_core_vl$next[6:0]$13339 $2\core_core_vl$next[6:0]$13349
+ assign $1\core_dec$next[63:0]$13340 $2\core_dec$next[63:0]$13350
+ assign $1\core_eint$next[0:0]$13341 $2\core_eint$next[0:0]$13351
+ assign $1\core_msr$next[63:0]$13342 $2\core_msr$next[63:0]$13352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_maxvl$next[6:0]$13552 $2\core_core_vl$next[6:0]$13557 $2\core_core_srcstep$next[6:0]$13554 $2\core_core_dststep$next[6:0]$13551 $2\core_core_subvl$next[1:0]$13555 $2\core_core_svstep$next[1:0]$13556 $2\core_dec$next[63:0]$13558 $2\core_eint$next[0:0]$13559 $2\core_msr$next[63:0]$13560 $2\core_core_pc$next[63:0]$13553 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $2\core_core_maxvl$next[6:0]$13344 $2\core_core_vl$next[6:0]$13349 $2\core_core_srcstep$next[6:0]$13346 $2\core_core_dststep$next[6:0]$13343 $2\core_core_subvl$next[1:0]$13347 $2\core_core_svstep$next[1:0]$13348 $2\core_dec$next[63:0]$13350 $2\core_eint$next[0:0]$13351 $2\core_msr$next[63:0]$13352 $2\core_core_pc$next[63:0]$13345 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $2\core_core_dststep$next[6:0]$13551 \core_core_dststep
- assign $2\core_core_maxvl$next[6:0]$13552 \core_core_maxvl
- assign $2\core_core_pc$next[63:0]$13553 \core_core_pc
- assign $2\core_core_srcstep$next[6:0]$13554 \core_core_srcstep
- assign $2\core_core_subvl$next[1:0]$13555 \core_core_subvl
- assign $2\core_core_svstep$next[1:0]$13556 \core_core_svstep
- assign $2\core_core_vl$next[6:0]$13557 \core_core_vl
- assign $2\core_dec$next[63:0]$13558 \core_dec
- assign $2\core_eint$next[0:0]$13559 \core_eint
- assign $2\core_msr$next[63:0]$13560 \core_msr
+ assign $2\core_core_dststep$next[6:0]$13343 \core_core_dststep
+ assign $2\core_core_maxvl$next[6:0]$13344 \core_core_maxvl
+ assign $2\core_core_pc$next[63:0]$13345 \core_core_pc
+ assign $2\core_core_srcstep$next[6:0]$13346 \core_core_srcstep
+ assign $2\core_core_subvl$next[1:0]$13347 \core_core_subvl
+ assign $2\core_core_svstep$next[1:0]$13348 \core_core_svstep
+ assign $2\core_core_vl$next[6:0]$13349 \core_core_vl
+ assign $2\core_dec$next[63:0]$13350 \core_dec
+ assign $2\core_eint$next[0:0]$13351 \core_eint
+ assign $2\core_msr$next[63:0]$13352 \core_msr
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_maxvl$next[6:0]$13542 $1\core_core_vl$next[6:0]$13547 $1\core_core_srcstep$next[6:0]$13544 $1\core_core_dststep$next[6:0]$13541 $1\core_core_subvl$next[1:0]$13545 $1\core_core_svstep$next[1:0]$13546 $1\core_dec$next[63:0]$13548 $1\core_eint$next[0:0]$13549 $1\core_msr$next[63:0]$13550 $1\core_core_pc$next[63:0]$13543 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $1\core_core_maxvl$next[6:0]$13334 $1\core_core_vl$next[6:0]$13339 $1\core_core_srcstep$next[6:0]$13336 $1\core_core_dststep$next[6:0]$13333 $1\core_core_subvl$next[1:0]$13337 $1\core_core_svstep$next[1:0]$13338 $1\core_dec$next[63:0]$13340 $1\core_eint$next[0:0]$13341 $1\core_msr$next[63:0]$13342 $1\core_core_pc$next[63:0]$13335 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
case
- assign $1\core_core_dststep$next[6:0]$13541 \core_core_dststep
- assign $1\core_core_maxvl$next[6:0]$13542 \core_core_maxvl
- assign $1\core_core_pc$next[63:0]$13543 \core_core_pc
- assign $1\core_core_srcstep$next[6:0]$13544 \core_core_srcstep
- assign $1\core_core_subvl$next[1:0]$13545 \core_core_subvl
- assign $1\core_core_svstep$next[1:0]$13546 \core_core_svstep
- assign $1\core_core_vl$next[6:0]$13547 \core_core_vl
- assign $1\core_dec$next[63:0]$13548 \core_dec
- assign $1\core_eint$next[0:0]$13549 \core_eint
- assign $1\core_msr$next[63:0]$13550 \core_msr
+ assign $1\core_core_dststep$next[6:0]$13333 \core_core_dststep
+ assign $1\core_core_maxvl$next[6:0]$13334 \core_core_maxvl
+ assign $1\core_core_pc$next[63:0]$13335 \core_core_pc
+ assign $1\core_core_srcstep$next[6:0]$13336 \core_core_srcstep
+ assign $1\core_core_subvl$next[1:0]$13337 \core_core_subvl
+ assign $1\core_core_svstep$next[1:0]$13338 \core_core_svstep
+ assign $1\core_core_vl$next[6:0]$13339 \core_core_vl
+ assign $1\core_dec$next[63:0]$13340 \core_dec
+ assign $1\core_eint$next[0:0]$13341 \core_eint
+ assign $1\core_msr$next[63:0]$13342 \core_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_core_pc$next[63:0]$13563 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_msr$next[63:0]$13570 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_eint$next[0:0]$13569 1'0
- assign $3\core_dec$next[63:0]$13568 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_core_svstep$next[1:0]$13566 2'00
- assign $3\core_core_subvl$next[1:0]$13565 2'00
- assign $3\core_core_dststep$next[6:0]$13561 7'0000000
- assign $3\core_core_srcstep$next[6:0]$13564 7'0000000
- assign $3\core_core_vl$next[6:0]$13567 7'0000000
- assign $3\core_core_maxvl$next[6:0]$13562 7'0000000
+ assign $3\core_core_pc$next[63:0]$13355 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_msr$next[63:0]$13362 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_eint$next[0:0]$13361 1'0
+ assign $3\core_dec$next[63:0]$13360 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_core_svstep$next[1:0]$13358 2'00
+ assign $3\core_core_subvl$next[1:0]$13357 2'00
+ assign $3\core_core_dststep$next[6:0]$13353 7'0000000
+ assign $3\core_core_srcstep$next[6:0]$13356 7'0000000
+ assign $3\core_core_vl$next[6:0]$13359 7'0000000
+ assign $3\core_core_maxvl$next[6:0]$13354 7'0000000
case
- assign $3\core_core_dststep$next[6:0]$13561 $1\core_core_dststep$next[6:0]$13541
- assign $3\core_core_maxvl$next[6:0]$13562 $1\core_core_maxvl$next[6:0]$13542
- assign $3\core_core_pc$next[63:0]$13563 $1\core_core_pc$next[63:0]$13543
- assign $3\core_core_srcstep$next[6:0]$13564 $1\core_core_srcstep$next[6:0]$13544
- assign $3\core_core_subvl$next[1:0]$13565 $1\core_core_subvl$next[1:0]$13545
- assign $3\core_core_svstep$next[1:0]$13566 $1\core_core_svstep$next[1:0]$13546
- assign $3\core_core_vl$next[6:0]$13567 $1\core_core_vl$next[6:0]$13547
- assign $3\core_dec$next[63:0]$13568 $1\core_dec$next[63:0]$13548
- assign $3\core_eint$next[0:0]$13569 $1\core_eint$next[0:0]$13549
- assign $3\core_msr$next[63:0]$13570 $1\core_msr$next[63:0]$13550
+ assign $3\core_core_dststep$next[6:0]$13353 $1\core_core_dststep$next[6:0]$13333
+ assign $3\core_core_maxvl$next[6:0]$13354 $1\core_core_maxvl$next[6:0]$13334
+ assign $3\core_core_pc$next[63:0]$13355 $1\core_core_pc$next[63:0]$13335
+ assign $3\core_core_srcstep$next[6:0]$13356 $1\core_core_srcstep$next[6:0]$13336
+ assign $3\core_core_subvl$next[1:0]$13357 $1\core_core_subvl$next[1:0]$13337
+ assign $3\core_core_svstep$next[1:0]$13358 $1\core_core_svstep$next[1:0]$13338
+ assign $3\core_core_vl$next[6:0]$13359 $1\core_core_vl$next[6:0]$13339
+ assign $3\core_dec$next[63:0]$13360 $1\core_dec$next[63:0]$13340
+ assign $3\core_eint$next[0:0]$13361 $1\core_eint$next[0:0]$13341
+ assign $3\core_msr$next[63:0]$13362 $1\core_msr$next[63:0]$13342
end
sync always
- update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13531
- update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13532
- update \core_core_pc$next $0\core_core_pc$next[63:0]$13533
- update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13534
- update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13535
- update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13536
- update \core_core_vl$next $0\core_core_vl$next[6:0]$13537
- update \core_dec$next $0\core_dec$next[63:0]$13538
- update \core_eint$next $0\core_eint$next[0:0]$13539
- update \core_msr$next $0\core_msr$next[63:0]$13540
+ update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13323
+ update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13324
+ update \core_core_pc$next $0\core_core_pc$next[63:0]$13325
+ update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13326
+ update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13327
+ update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13328
+ update \core_core_vl$next $0\core_core_vl$next[6:0]$13329
+ update \core_dec$next $0\core_dec$next[63:0]$13330
+ update \core_eint$next $0\core_eint$next[0:0]$13331
+ update \core_msr$next $0\core_msr$next[63:0]$13332
end
- attribute \src "libresoc.v:198573.3-198597.6"
- process $proc$libresoc.v:198573$13571
+ attribute \src "libresoc.v:198469.3-198493.6"
+ process $proc$libresoc.v:198469$13363
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_raw_insn_i$next[31:0]$13572 $3\core_raw_insn_i$next[31:0]$13575
- attribute \src "libresoc.v:198574.5-198574.29"
+ assign $0\core_raw_insn_i$next[31:0]$13364 $3\core_raw_insn_i$next[31:0]$13367
+ attribute \src "libresoc.v:198470.5-198470.29"
switch \initial
- attribute \src "libresoc.v:198574.9-198574.17"
+ attribute \src "libresoc.v:198470.9-198470.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_raw_insn_i$next[31:0]$13573 \core_raw_insn_i
+ assign $1\core_raw_insn_i$next[31:0]$13365 \core_raw_insn_i
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_raw_insn_i$next[31:0]$13573 $2\core_raw_insn_i$next[31:0]$13574
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\core_raw_insn_i$next[31:0]$13365 $2\core_raw_insn_i$next[31:0]$13366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_raw_insn_i$next[31:0]$13574 \dec2_raw_opcode_in
+ assign $2\core_raw_insn_i$next[31:0]$13366 \dec2_raw_opcode_in
case
- assign $2\core_raw_insn_i$next[31:0]$13574 \core_raw_insn_i
+ assign $2\core_raw_insn_i$next[31:0]$13366 \core_raw_insn_i
end
case
- assign $1\core_raw_insn_i$next[31:0]$13573 \core_raw_insn_i
+ assign $1\core_raw_insn_i$next[31:0]$13365 \core_raw_insn_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_raw_insn_i$next[31:0]$13575 0
+ assign $3\core_raw_insn_i$next[31:0]$13367 0
case
- assign $3\core_raw_insn_i$next[31:0]$13575 $1\core_raw_insn_i$next[31:0]$13573
+ assign $3\core_raw_insn_i$next[31:0]$13367 $1\core_raw_insn_i$next[31:0]$13365
end
sync always
- update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13572
+ update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13364
end
- attribute \src "libresoc.v:198598.3-198642.6"
- process $proc$libresoc.v:198598$13576
+ attribute \src "libresoc.v:198494.3-198538.6"
+ process $proc$libresoc.v:198494$13368
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_bigendian_i$10$next[0:0]$13577 $3\core_bigendian_i$10$next[0:0]$13580
- attribute \src "libresoc.v:198599.5-198599.29"
+ assign $0\core_bigendian_i$10$next[0:0]$13369 $3\core_bigendian_i$10$next[0:0]$13372
+ attribute \src "libresoc.v:198495.5-198495.29"
switch \initial
- attribute \src "libresoc.v:198599.9-198599.17"
+ attribute \src "libresoc.v:198495.9-198495.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_bigendian_i$10$next[0:0]$13578 $2\core_bigendian_i$10$next[0:0]$13579
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\core_bigendian_i$10$next[0:0]$13370 $2\core_bigendian_i$10$next[0:0]$13371
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_bigendian_i$10$next[0:0]$13579 \core_bigendian_i
+ assign $2\core_bigendian_i$10$next[0:0]$13371 \core_bigendian_i
case
- assign $2\core_bigendian_i$10$next[0:0]$13579 \core_bigendian_i$10
+ assign $2\core_bigendian_i$10$next[0:0]$13371 \core_bigendian_i$10
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i
case
- assign $1\core_bigendian_i$10$next[0:0]$13578 \core_bigendian_i$10
+ assign $1\core_bigendian_i$10$next[0:0]$13370 \core_bigendian_i$10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_bigendian_i$10$next[0:0]$13580 1'0
+ assign $3\core_bigendian_i$10$next[0:0]$13372 1'0
case
- assign $3\core_bigendian_i$10$next[0:0]$13580 $1\core_bigendian_i$10$next[0:0]$13578
+ assign $3\core_bigendian_i$10$next[0:0]$13372 $1\core_bigendian_i$10$next[0:0]$13370
end
sync always
- update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13577
+ update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13369
end
- attribute \src "libresoc.v:198643.3-198687.6"
- process $proc$libresoc.v:198643$13581
+ attribute \src "libresoc.v:198539.3-198583.6"
+ process $proc$libresoc.v:198539$13373
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_sv_a_nz$next[0:0]$13582 $3\core_sv_a_nz$next[0:0]$13585
- attribute \src "libresoc.v:198644.5-198644.29"
+ assign $0\core_sv_a_nz$next[0:0]$13374 $3\core_sv_a_nz$next[0:0]$13377
+ attribute \src "libresoc.v:198540.5-198540.29"
switch \initial
- attribute \src "libresoc.v:198644.9-198644.17"
+ attribute \src "libresoc.v:198540.9-198540.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\core_sv_a_nz$next[0:0]$13583 $2\core_sv_a_nz$next[0:0]$13584
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\core_sv_a_nz$next[0:0]$13375 $2\core_sv_a_nz$next[0:0]$13376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\core_sv_a_nz$next[0:0]$13584 \dec2_sv_a_nz
+ assign $2\core_sv_a_nz$next[0:0]$13376 \dec2_sv_a_nz
case
- assign $2\core_sv_a_nz$next[0:0]$13584 \core_sv_a_nz
+ assign $2\core_sv_a_nz$next[0:0]$13376 \core_sv_a_nz
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\core_sv_a_nz$next[0:0]$13583 \dec2_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \dec2_sv_a_nz
case
- assign $1\core_sv_a_nz$next[0:0]$13583 \core_sv_a_nz
+ assign $1\core_sv_a_nz$next[0:0]$13375 \core_sv_a_nz
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\core_sv_a_nz$next[0:0]$13585 1'0
+ assign $3\core_sv_a_nz$next[0:0]$13377 1'0
case
- assign $3\core_sv_a_nz$next[0:0]$13585 $1\core_sv_a_nz$next[0:0]$13583
+ assign $3\core_sv_a_nz$next[0:0]$13377 $1\core_sv_a_nz$next[0:0]$13375
end
sync always
- update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13582
+ update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13374
end
- attribute \src "libresoc.v:198688.3-198733.6"
- process $proc$libresoc.v:198688$13586
+ attribute \src "libresoc.v:198584.3-198629.6"
+ process $proc$libresoc.v:198584$13378
assign { } { }
assign { } { }
assign { } { }
assign $0\insn_done[0:0] $4\insn_done[0:0]
- attribute \src "libresoc.v:198689.5-198689.29"
+ attribute \src "libresoc.v:198585.5-198585.29"
switch \initial
- attribute \src "libresoc.v:198689.9-198689.17"
+ attribute \src "libresoc.v:198585.9-198585.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'001
assign { } { }
assign $1\insn_done[0:0] $2\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\insn_done[0:0] $3\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
switch \$234
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign $1\insn_done[0:0] 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
case 1'1
assign { } { }
assign $4\insn_done[0:0] $5\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
switch \$236
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\insn_done[0:0] $6\insn_done[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:736"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741"
switch \exec_pc_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \insn_done $0\insn_done[0:0]
end
- attribute \src "libresoc.v:198734.3-198752.6"
- process $proc$libresoc.v:198734$13587
+ attribute \src "libresoc.v:198630.3-198648.6"
+ process $proc$libresoc.v:198630$13379
assign { } { }
assign { } { }
assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0]
- attribute \src "libresoc.v:198735.5-198735.29"
+ attribute \src "libresoc.v:198631.5-198631.29"
switch \initial
- attribute \src "libresoc.v:198735.9-198735.17"
+ attribute \src "libresoc.v:198631.9-198631.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \pred_insn_valid_i $0\pred_insn_valid_i[0:0]
end
- attribute \src "libresoc.v:198753.3-198775.6"
- process $proc$libresoc.v:198753$13588
+ attribute \src "libresoc.v:198649.3-198671.6"
+ process $proc$libresoc.v:198649$13380
assign { } { }
assign { } { }
assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0]
- attribute \src "libresoc.v:198754.5-198754.29"
+ attribute \src "libresoc.v:198650.5-198650.29"
switch \initial
- attribute \src "libresoc.v:198754.9-198754.17"
+ attribute \src "libresoc.v:198650.9-198650.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \pred_mask_ready_i $0\pred_mask_ready_i[0:0]
end
- attribute \src "libresoc.v:198776.3-198802.6"
- process $proc$libresoc.v:198776$13589
+ attribute \src "libresoc.v:198672.3-198698.6"
+ process $proc$libresoc.v:198672$13381
assign { } { }
assign { } { }
assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0]
- attribute \src "libresoc.v:198777.5-198777.29"
+ attribute \src "libresoc.v:198673.5-198673.29"
switch \initial
- attribute \src "libresoc.v:198777.9-198777.17"
+ attribute \src "libresoc.v:198673.9-198673.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \exec_insn_valid_i $0\exec_insn_valid_i[0:0]
end
- attribute \src "libresoc.v:198803.3-198838.6"
- process $proc$libresoc.v:198803$13590
+ attribute \src "libresoc.v:198699.3-198734.6"
+ process $proc$libresoc.v:198699$13382
assign { } { }
assign { } { }
assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0]
- attribute \src "libresoc.v:198804.5-198804.29"
+ attribute \src "libresoc.v:198700.5-198700.29"
switch \initial
- attribute \src "libresoc.v:198804.9-198804.17"
+ attribute \src "libresoc.v:198700.9-198700.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'101
assign { } { }
assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$242
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \exec_pc_ready_i $0\exec_pc_ready_i[0:0]
end
- attribute \src "libresoc.v:198839.3-198879.6"
- process $proc$libresoc.v:198839$13591
+ attribute \src "libresoc.v:198735.3-198775.6"
+ process $proc$libresoc.v:198735$13383
assign { } { }
assign { } { }
assign $0\is_last[0:0] $1\is_last[0:0]
- attribute \src "libresoc.v:198840.5-198840.29"
+ attribute \src "libresoc.v:198736.5-198736.29"
switch \initial
- attribute \src "libresoc.v:198840.9-198840.17"
+ attribute \src "libresoc.v:198736.9-198736.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
case 3'101
assign { } { }
assign $1\is_last[0:0] $2\is_last[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$248
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $2\is_last[0:0] $3\is_last[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \is_last $0\is_last[0:0]
end
- attribute \src "libresoc.v:198880.3-198889.6"
- process $proc$libresoc.v:198880$13592
+ attribute \src "libresoc.v:198776.3-198785.6"
+ process $proc$libresoc.v:198776$13384
assign { } { }
assign { } { }
- assign $0\core_wen$11[2:0]$13593 $1\core_wen$11[2:0]$13594
- attribute \src "libresoc.v:198881.5-198881.29"
+ assign $0\core_wen$11[2:0]$13385 $1\core_wen$11[2:0]$13386
+ attribute \src "libresoc.v:198777.5-198777.29"
switch \initial
- attribute \src "libresoc.v:198881.9-198881.17"
+ attribute \src "libresoc.v:198777.9-198777.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_wen$11[2:0]$13594 3'100
+ assign $1\core_wen$11[2:0]$13386 3'100
case
- assign $1\core_wen$11[2:0]$13594 3'000
+ assign $1\core_wen$11[2:0]$13386 3'000
end
sync always
- update \core_wen$11 $0\core_wen$11[2:0]$13593
+ update \core_wen$11 $0\core_wen$11[2:0]$13385
end
- attribute \src "libresoc.v:198890.3-198899.6"
- process $proc$libresoc.v:198890$13595
+ attribute \src "libresoc.v:198786.3-198795.6"
+ process $proc$libresoc.v:198786$13387
assign { } { }
assign { } { }
- assign $0\core_data_i$12[63:0]$13596 $1\core_data_i$12[63:0]$13597
- attribute \src "libresoc.v:198891.5-198891.29"
+ assign $0\core_data_i$12[63:0]$13388 $1\core_data_i$12[63:0]$13389
+ attribute \src "libresoc.v:198787.5-198787.29"
switch \initial
- attribute \src "libresoc.v:198891.9-198891.17"
+ attribute \src "libresoc.v:198787.9-198787.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_data_i$12[63:0]$13597 \$252
+ assign $1\core_data_i$12[63:0]$13389 \$252
case
- assign $1\core_data_i$12[63:0]$13597 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\core_data_i$12[63:0]$13389 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync always
- update \core_data_i$12 $0\core_data_i$12[63:0]$13596
+ update \core_data_i$12 $0\core_data_i$12[63:0]$13388
end
- attribute \src "libresoc.v:198900.3-198910.6"
- process $proc$libresoc.v:198900$13598
+ attribute \src "libresoc.v:198796.3-198806.6"
+ process $proc$libresoc.v:198796$13390
assign { } { }
assign { } { }
assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0]
- attribute \src "libresoc.v:198901.5-198901.29"
+ attribute \src "libresoc.v:198797.5-198797.29"
switch \initial
- attribute \src "libresoc.v:198901.9-198901.17"
+ attribute \src "libresoc.v:198797.9-198797.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
sync always
update \exec_insn_ready_o $0\exec_insn_ready_o[0:0]
end
- attribute \src "libresoc.v:198911.3-198935.6"
- process $proc$libresoc.v:198911$13599
+ attribute \src "libresoc.v:198807.3-198831.6"
+ process $proc$libresoc.v:198807$13391
assign { } { }
assign { } { }
assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0]
- attribute \src "libresoc.v:198912.5-198912.29"
+ attribute \src "libresoc.v:198808.5-198808.29"
switch \initial
- attribute \src "libresoc.v:198912.9-198912.17"
+ attribute \src "libresoc.v:198808.9-198808.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 1'1
assign { } { }
assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
switch \$254
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_ivalid_i $0\core_ivalid_i[0:0]
end
- attribute \src "libresoc.v:198936.3-198951.6"
- process $proc$libresoc.v:198936$13600
+ attribute \src "libresoc.v:198832.3-198847.6"
+ process $proc$libresoc.v:198832$13392
assign { } { }
assign { } { }
assign $0\core_issue_i[0:0] $1\core_issue_i[0:0]
- attribute \src "libresoc.v:198937.5-198937.29"
+ attribute \src "libresoc.v:198833.5-198833.29"
switch \initial
- attribute \src "libresoc.v:198937.9-198937.17"
+ attribute \src "libresoc.v:198833.9-198833.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
assign $1\core_issue_i[0:0] $2\core_issue_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_issue_i $0\core_issue_i[0:0]
end
- attribute \src "libresoc.v:198952.3-198986.6"
- process $proc$libresoc.v:198952$13601
+ attribute \src "libresoc.v:198848.3-198882.6"
+ process $proc$libresoc.v:198848$13393
assign { } { }
assign { } { }
assign { } { }
- assign $0\exec_fsm_state$next[0:0]$13602 $5\exec_fsm_state$next[0:0]$13607
- attribute \src "libresoc.v:198953.5-198953.29"
+ assign $0\exec_fsm_state$next[0:0]$13394 $5\exec_fsm_state$next[0:0]$13399
+ attribute \src "libresoc.v:198849.5-198849.29"
switch \initial
- attribute \src "libresoc.v:198953.9-198953.17"
+ attribute \src "libresoc.v:198849.9-198849.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13603 $2\exec_fsm_state$next[0:0]$13604
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ assign $1\exec_fsm_state$next[0:0]$13395 $2\exec_fsm_state$next[0:0]$13396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\exec_fsm_state$next[0:0]$13604 1'1
+ assign $2\exec_fsm_state$next[0:0]$13396 1'1
case
- assign $2\exec_fsm_state$next[0:0]$13604 \exec_fsm_state
+ assign $2\exec_fsm_state$next[0:0]$13396 \exec_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\exec_fsm_state$next[0:0]$13603 $3\exec_fsm_state$next[0:0]$13605
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ assign $1\exec_fsm_state$next[0:0]$13395 $3\exec_fsm_state$next[0:0]$13397
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
switch \$256
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\exec_fsm_state$next[0:0]$13605 $4\exec_fsm_state$next[0:0]$13606
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:736"
+ assign $3\exec_fsm_state$next[0:0]$13397 $4\exec_fsm_state$next[0:0]$13398
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741"
switch \exec_pc_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\exec_fsm_state$next[0:0]$13606 1'0
+ assign $4\exec_fsm_state$next[0:0]$13398 1'0
case
- assign $4\exec_fsm_state$next[0:0]$13606 \exec_fsm_state
+ assign $4\exec_fsm_state$next[0:0]$13398 \exec_fsm_state
end
case
- assign $3\exec_fsm_state$next[0:0]$13605 \exec_fsm_state
+ assign $3\exec_fsm_state$next[0:0]$13397 \exec_fsm_state
end
case
- assign $1\exec_fsm_state$next[0:0]$13603 \exec_fsm_state
+ assign $1\exec_fsm_state$next[0:0]$13395 \exec_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\exec_fsm_state$next[0:0]$13607 1'0
+ assign $5\exec_fsm_state$next[0:0]$13399 1'0
case
- assign $5\exec_fsm_state$next[0:0]$13607 $1\exec_fsm_state$next[0:0]$13603
+ assign $5\exec_fsm_state$next[0:0]$13399 $1\exec_fsm_state$next[0:0]$13395
end
sync always
- update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13602
+ update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13394
end
- attribute \src "libresoc.v:198987.3-199006.6"
- process $proc$libresoc.v:198987$13608
+ attribute \src "libresoc.v:198883.3-198902.6"
+ process $proc$libresoc.v:198883$13400
assign { } { }
assign { } { }
assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0]
- attribute \src "libresoc.v:198988.5-198988.29"
+ attribute \src "libresoc.v:198884.5-198884.29"
switch \initial
- attribute \src "libresoc.v:198988.9-198988.17"
+ attribute \src "libresoc.v:198884.9-198884.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
case 1'1
assign { } { }
assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739"
switch \$258
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \exec_pc_valid_o $0\exec_pc_valid_o[0:0]
end
- attribute \src "libresoc.v:199007.3-199016.6"
- process $proc$libresoc.v:199007$13609
+ attribute \src "libresoc.v:198903.3-198912.6"
+ process $proc$libresoc.v:198903$13401
assign { } { }
assign { } { }
assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0]
- attribute \src "libresoc.v:199008.5-199008.29"
+ attribute \src "libresoc.v:198904.5-198904.29"
switch \initial
- attribute \src "libresoc.v:199008.9-199008.17"
+ attribute \src "libresoc.v:198904.9-198904.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__addr $0\core_dmi__addr[4:0]
end
- attribute \src "libresoc.v:199017.3-199026.6"
- process $proc$libresoc.v:199017$13610
+ attribute \src "libresoc.v:198913.3-198922.6"
+ process $proc$libresoc.v:198913$13402
assign { } { }
assign { } { }
assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0]
- attribute \src "libresoc.v:199018.5-199018.29"
+ attribute \src "libresoc.v:198914.5-198914.29"
switch \initial
- attribute \src "libresoc.v:199018.9-199018.17"
+ attribute \src "libresoc.v:198914.9-198914.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947"
switch \dbg_d_gpr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_dmi__ren $0\core_dmi__ren[0:0]
end
- attribute \src "libresoc.v:199027.3-199035.6"
- process $proc$libresoc.v:199027$13611
+ attribute \src "libresoc.v:198923.3-198931.6"
+ process $proc$libresoc.v:198923$13403
assign { } { }
assign { } { }
- assign $0\d_reg_delay$next[0:0]$13612 $1\d_reg_delay$next[0:0]$13613
- attribute \src "libresoc.v:199028.5-199028.29"
+ assign $0\d_reg_delay$next[0:0]$13404 $1\d_reg_delay$next[0:0]$13405
+ attribute \src "libresoc.v:198924.5-198924.29"
switch \initial
- attribute \src "libresoc.v:199028.9-199028.17"
+ attribute \src "libresoc.v:198924.9-198924.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_reg_delay$next[0:0]$13613 1'0
+ assign $1\d_reg_delay$next[0:0]$13405 1'0
case
- assign $1\d_reg_delay$next[0:0]$13613 \dbg_d_gpr_req
+ assign $1\d_reg_delay$next[0:0]$13405 \dbg_d_gpr_req
end
sync always
- update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13612
+ update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13404
end
- attribute \src "libresoc.v:199036.3-199045.6"
- process $proc$libresoc.v:199036$13614
+ attribute \src "libresoc.v:198932.3-198941.6"
+ process $proc$libresoc.v:198932$13406
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:199037.5-199037.29"
+ attribute \src "libresoc.v:198933.5-198933.29"
switch \initial
- attribute \src "libresoc.v:199037.9-199037.17"
+ attribute \src "libresoc.v:198933.9-198933.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:199046.3-199055.6"
- process $proc$libresoc.v:199046$13615
+ attribute \src "libresoc.v:198942.3-198951.6"
+ process $proc$libresoc.v:198942$13407
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:199047.5-199047.29"
+ attribute \src "libresoc.v:198943.5-198943.29"
switch \initial
- attribute \src "libresoc.v:199047.9-199047.17"
+ attribute \src "libresoc.v:198943.9-198943.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957"
switch \d_reg_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:199056.3-199065.6"
- process $proc$libresoc.v:199056$13616
+ attribute \src "libresoc.v:198952.3-198961.6"
+ process $proc$libresoc.v:198952$13408
assign { } { }
assign { } { }
assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0]
- attribute \src "libresoc.v:199057.5-199057.29"
+ attribute \src "libresoc.v:198953.5-198953.29"
switch \initial
- attribute \src "libresoc.v:199057.9-199057.17"
+ attribute \src "libresoc.v:198953.9-198953.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:963"
switch \dbg_d_cr_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd2__ren $0\core_full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:199066.3-199074.6"
- process $proc$libresoc.v:199066$13617
+ attribute \src "libresoc.v:198962.3-198970.6"
+ process $proc$libresoc.v:198962$13409
assign { } { }
assign { } { }
- assign $0\d_cr_delay$next[0:0]$13618 $1\d_cr_delay$next[0:0]$13619
- attribute \src "libresoc.v:199067.5-199067.29"
+ assign $0\d_cr_delay$next[0:0]$13410 $1\d_cr_delay$next[0:0]$13411
+ attribute \src "libresoc.v:198963.5-198963.29"
switch \initial
- attribute \src "libresoc.v:199067.9-199067.17"
+ attribute \src "libresoc.v:198963.9-198963.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_cr_delay$next[0:0]$13619 1'0
+ assign $1\d_cr_delay$next[0:0]$13411 1'0
case
- assign $1\d_cr_delay$next[0:0]$13619 \dbg_d_cr_req
+ assign $1\d_cr_delay$next[0:0]$13411 \dbg_d_cr_req
end
sync always
- update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13618
+ update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13410
end
- attribute \src "libresoc.v:199075.3-199084.6"
- process $proc$libresoc.v:199075$13620
+ attribute \src "libresoc.v:198971.3-198980.6"
+ process $proc$libresoc.v:198971$13412
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:199076.5-199076.29"
+ attribute \src "libresoc.v:198972.5-198972.29"
switch \initial
- attribute \src "libresoc.v:199076.9-199076.17"
+ attribute \src "libresoc.v:198972.9-198972.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:962"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:199085.3-199094.6"
- process $proc$libresoc.v:199085$13621
+ attribute \src "libresoc.v:198981.3-198990.6"
+ process $proc$libresoc.v:198981$13413
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:199086.5-199086.29"
+ attribute \src "libresoc.v:198982.5-198982.29"
switch \initial
- attribute \src "libresoc.v:199086.9-199086.17"
+ attribute \src "libresoc.v:198982.9-198982.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:962"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967"
switch \d_cr_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:199095.3-199104.6"
- process $proc$libresoc.v:199095$13622
+ attribute \src "libresoc.v:198991.3-199000.6"
+ process $proc$libresoc.v:198991$13414
assign { } { }
assign { } { }
assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0]
- attribute \src "libresoc.v:199096.5-199096.29"
+ attribute \src "libresoc.v:198992.5-198992.29"
switch \initial
- attribute \src "libresoc.v:199096.9-199096.17"
+ attribute \src "libresoc.v:198992.9-198992.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:973"
switch \dbg_d_xer_req
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_full_rd__ren $0\core_full_rd__ren[2:0]
end
- attribute \src "libresoc.v:199105.3-199113.6"
- process $proc$libresoc.v:199105$13623
+ attribute \src "libresoc.v:199001.3-199009.6"
+ process $proc$libresoc.v:199001$13415
assign { } { }
assign { } { }
- assign $0\d_xer_delay$next[0:0]$13624 $1\d_xer_delay$next[0:0]$13625
- attribute \src "libresoc.v:199106.5-199106.29"
+ assign $0\d_xer_delay$next[0:0]$13416 $1\d_xer_delay$next[0:0]$13417
+ attribute \src "libresoc.v:199002.5-199002.29"
switch \initial
- attribute \src "libresoc.v:199106.9-199106.17"
+ attribute \src "libresoc.v:199002.9-199002.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_xer_delay$next[0:0]$13625 1'0
+ assign $1\d_xer_delay$next[0:0]$13417 1'0
case
- assign $1\d_xer_delay$next[0:0]$13625 \dbg_d_xer_req
+ assign $1\d_xer_delay$next[0:0]$13417 \dbg_d_xer_req
end
sync always
- update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13624
+ update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13416
end
- attribute \src "libresoc.v:199114.3-199123.6"
- process $proc$libresoc.v:199114$13626
+ attribute \src "libresoc.v:199010.3-199019.6"
+ process $proc$libresoc.v:199010$13418
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:199115.5-199115.29"
+ attribute \src "libresoc.v:199011.5-199011.29"
switch \initial
- attribute \src "libresoc.v:199115.9-199115.17"
+ attribute \src "libresoc.v:199011.9-199011.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:199124.3-199133.6"
- process $proc$libresoc.v:199124$13627
+ attribute \src "libresoc.v:199020.3-199029.6"
+ process $proc$libresoc.v:199020$13419
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:199125.5-199125.29"
+ attribute \src "libresoc.v:199021.5-199021.29"
switch \initial
- attribute \src "libresoc.v:199125.9-199125.17"
+ attribute \src "libresoc.v:199021.9-199021.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977"
switch \d_xer_delay
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:199134.3-199152.6"
- process $proc$libresoc.v:199134$13628
+ attribute \src "libresoc.v:199030.3-199048.6"
+ process $proc$libresoc.v:199030$13420
assign { } { }
assign { } { }
assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0]
- attribute \src "libresoc.v:199135.5-199135.29"
+ attribute \src "libresoc.v:199031.5-199031.29"
switch \initial
- attribute \src "libresoc.v:199135.9-199135.17"
+ attribute \src "libresoc.v:199031.9-199031.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__addr $0\core_issue__addr[2:0]
end
- attribute \src "libresoc.v:199153.3-199171.6"
- process $proc$libresoc.v:199153$13629
+ attribute \src "libresoc.v:199049.3-199067.6"
+ process $proc$libresoc.v:199049$13421
assign { } { }
assign { } { }
assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0]
- attribute \src "libresoc.v:199154.5-199154.29"
+ attribute \src "libresoc.v:199050.5-199050.29"
switch \initial
- attribute \src "libresoc.v:199154.9-199154.17"
+ attribute \src "libresoc.v:199050.9-199050.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__ren $0\core_issue__ren[0:0]
end
- attribute \src "libresoc.v:199172.3-199199.6"
- process $proc$libresoc.v:199172$13630
+ attribute \src "libresoc.v:199068.3-199095.6"
+ process $proc$libresoc.v:199068$13422
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$13631 $2\fsm_state$next[1:0]$13633
- attribute \src "libresoc.v:199173.5-199173.29"
+ assign $0\fsm_state$next[1:0]$13423 $2\fsm_state$next[1:0]$13425
+ attribute \src "libresoc.v:199069.5-199069.29"
switch \initial
- attribute \src "libresoc.v:199173.9-199173.17"
+ attribute \src "libresoc.v:199069.9-199069.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$13632 2'01
+ assign $1\fsm_state$next[1:0]$13424 2'01
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$13632 2'10
+ assign $1\fsm_state$next[1:0]$13424 2'10
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$13632 2'11
+ assign $1\fsm_state$next[1:0]$13424 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$next[1:0]$13632 2'00
+ assign $1\fsm_state$next[1:0]$13424 2'00
case
- assign $1\fsm_state$next[1:0]$13632 \fsm_state
+ assign $1\fsm_state$next[1:0]$13424 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$13633 2'00
+ assign $2\fsm_state$next[1:0]$13425 2'00
case
- assign $2\fsm_state$next[1:0]$13633 $1\fsm_state$next[1:0]$13632
+ assign $2\fsm_state$next[1:0]$13425 $1\fsm_state$next[1:0]$13424
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$13631
+ update \fsm_state$next $0\fsm_state$next[1:0]$13423
end
- attribute \src "libresoc.v:199200.3-199214.6"
- process $proc$libresoc.v:199200$13634
+ attribute \src "libresoc.v:199096.3-199110.6"
+ process $proc$libresoc.v:199096$13426
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:199201.5-199201.29"
+ attribute \src "libresoc.v:199097.5-199097.29"
switch \initial
- attribute \src "libresoc.v:199201.9-199201.17"
+ attribute \src "libresoc.v:199097.9-199097.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:199215.3-199237.6"
- process $proc$libresoc.v:199215$13635
+ attribute \src "libresoc.v:199111.3-199133.6"
+ process $proc$libresoc.v:199111$13427
assign { } { }
assign { } { }
- assign $0\core_issue__addr$13[2:0]$13636 $1\core_issue__addr$13[2:0]$13637
- attribute \src "libresoc.v:199216.5-199216.29"
+ assign $0\core_issue__addr$13[2:0]$13428 $1\core_issue__addr$13[2:0]$13429
+ attribute \src "libresoc.v:199112.5-199112.29"
switch \initial
- attribute \src "libresoc.v:199216.9-199216.17"
+ attribute \src "libresoc.v:199112.9-199112.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\core_issue__addr$13[2:0]$13637 3'000
+ assign $1\core_issue__addr$13[2:0]$13429 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13637 3'110
+ assign $1\core_issue__addr$13[2:0]$13429 3'110
attribute \src "libresoc.v:0.0-0.0"
case 2'10
- assign $1\core_issue__addr$13[2:0]$13637 3'000
+ assign $1\core_issue__addr$13[2:0]$13429 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\core_issue__addr$13[2:0]$13637 3'111
+ assign $1\core_issue__addr$13[2:0]$13429 3'111
case
- assign $1\core_issue__addr$13[2:0]$13637 3'000
+ assign $1\core_issue__addr$13[2:0]$13429 3'000
end
sync always
- update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13636
+ update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13428
end
- attribute \src "libresoc.v:199238.3-199260.6"
- process $proc$libresoc.v:199238$13638
+ attribute \src "libresoc.v:199134.3-199156.6"
+ process $proc$libresoc.v:199134$13430
assign { } { }
assign { } { }
assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0]
- attribute \src "libresoc.v:199239.5-199239.29"
+ attribute \src "libresoc.v:199135.5-199135.29"
switch \initial
- attribute \src "libresoc.v:199239.9-199239.17"
+ attribute \src "libresoc.v:199135.9-199135.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__wen $0\core_issue__wen[0:0]
end
- attribute \src "libresoc.v:199261.3-199283.6"
- process $proc$libresoc.v:199261$13639
+ attribute \src "libresoc.v:199157.3-199179.6"
+ process $proc$libresoc.v:199157$13431
assign { } { }
assign { } { }
assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0]
- attribute \src "libresoc.v:199262.5-199262.29"
+ attribute \src "libresoc.v:199158.5-199158.29"
switch \initial
- attribute \src "libresoc.v:199262.9-199262.17"
+ attribute \src "libresoc.v:199158.9-199158.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \core_issue__data_i $0\core_issue__data_i[63:0]
end
- attribute \src "libresoc.v:199284.3-199303.6"
- process $proc$libresoc.v:199284$13640
+ attribute \src "libresoc.v:199180.3-199199.6"
+ process $proc$libresoc.v:199180$13432
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_dec$next[63:0]$13641 $2\dec2_cur_dec$next[63:0]$13643
- attribute \src "libresoc.v:199285.5-199285.29"
+ assign $0\dec2_cur_dec$next[63:0]$13433 $2\dec2_cur_dec$next[63:0]$13435
+ attribute \src "libresoc.v:199181.5-199181.29"
switch \initial
- attribute \src "libresoc.v:199285.9-199285.17"
+ attribute \src "libresoc.v:199181.9-199181.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_cur_dec$next[63:0]$13642 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$13434 \dec2_cur_dec
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_dec$next[63:0]$13642 \new_dec
+ assign $1\dec2_cur_dec$next[63:0]$13434 \new_dec
case
- assign $1\dec2_cur_dec$next[63:0]$13642 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$13434 \dec2_cur_dec
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_dec$next[63:0]$13643 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dec2_cur_dec$next[63:0]$13435 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\dec2_cur_dec$next[63:0]$13643 $1\dec2_cur_dec$next[63:0]$13642
+ assign $2\dec2_cur_dec$next[63:0]$13435 $1\dec2_cur_dec$next[63:0]$13434
end
sync always
- update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13641
+ update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13433
end
- attribute \src "libresoc.v:199304.3-199326.6"
- process $proc$libresoc.v:199304$13644
+ attribute \src "libresoc.v:199200.3-199222.6"
+ process $proc$libresoc.v:199200$13436
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:199305.5-199305.29"
+ attribute \src "libresoc.v:199201.5-199201.29"
switch \initial
- attribute \src "libresoc.v:199305.9-199305.17"
+ attribute \src "libresoc.v:199201.9-199201.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998"
switch \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:199327.3-199335.6"
- process $proc$libresoc.v:199327$13645
+ attribute \src "libresoc.v:199223.3-199231.6"
+ process $proc$libresoc.v:199223$13437
assign { } { }
assign { } { }
- assign $0\dbg_dmi_we_i$next[0:0]$13646 $1\dbg_dmi_we_i$next[0:0]$13647
- attribute \src "libresoc.v:199328.5-199328.29"
+ assign $0\dbg_dmi_we_i$next[0:0]$13438 $1\dbg_dmi_we_i$next[0:0]$13439
+ attribute \src "libresoc.v:199224.5-199224.29"
switch \initial
- attribute \src "libresoc.v:199328.9-199328.17"
+ attribute \src "libresoc.v:199224.9-199224.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_we_i$next[0:0]$13647 1'0
+ assign $1\dbg_dmi_we_i$next[0:0]$13439 1'0
case
- assign $1\dbg_dmi_we_i$next[0:0]$13647 \jtag_dmi0__we_i
+ assign $1\dbg_dmi_we_i$next[0:0]$13439 \jtag_dmi0__we_i
end
sync always
- update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13646
+ update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13438
end
- attribute \src "libresoc.v:199336.3-199344.6"
- process $proc$libresoc.v:199336$13648
+ attribute \src "libresoc.v:199232.3-199240.6"
+ process $proc$libresoc.v:199232$13440
assign { } { }
assign { } { }
- assign $0\pc_ok_delay$next[0:0]$13649 $1\pc_ok_delay$next[0:0]$13650
- attribute \src "libresoc.v:199337.5-199337.29"
+ assign $0\pc_ok_delay$next[0:0]$13441 $1\pc_ok_delay$next[0:0]$13442
+ attribute \src "libresoc.v:199233.5-199233.29"
switch \initial
- attribute \src "libresoc.v:199337.9-199337.17"
+ attribute \src "libresoc.v:199233.9-199233.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pc_ok_delay$next[0:0]$13650 1'0
+ assign $1\pc_ok_delay$next[0:0]$13442 1'0
case
- assign $1\pc_ok_delay$next[0:0]$13650 \$38
+ assign $1\pc_ok_delay$next[0:0]$13442 \$38
end
sync always
- update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13649
+ update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13441
end
- attribute \src "libresoc.v:199345.3-199360.6"
- process $proc$libresoc.v:199345$13651
+ attribute \src "libresoc.v:199241.3-199256.6"
+ process $proc$libresoc.v:199241$13443
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:199346.5-199346.29"
+ attribute \src "libresoc.v:199242.5-199242.29"
switch \initial
- attribute \src "libresoc.v:199346.9-199346.17"
+ attribute \src "libresoc.v:199242.9-199242.17"
case 1'1
case
end
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:199361.3-199373.6"
- process $proc$libresoc.v:199361$13652
+ attribute \src "libresoc.v:199257.3-199269.6"
+ process $proc$libresoc.v:199257$13444
assign { } { }
assign { } { }
assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0]
- attribute \src "libresoc.v:199362.5-199362.29"
+ attribute \src "libresoc.v:199258.5-199258.29"
switch \initial
- attribute \src "libresoc.v:199362.9-199362.17"
+ attribute \src "libresoc.v:199258.9-199258.17"
case 1'1
case
end
sync always
update \core_cia__ren $0\core_cia__ren[2:0]
end
- attribute \src "libresoc.v:199374.3-199382.6"
- process $proc$libresoc.v:199374$13653
+ attribute \src "libresoc.v:199270.3-199278.6"
+ process $proc$libresoc.v:199270$13445
assign { } { }
assign { } { }
- assign $0\svstate_ok_delay$next[0:0]$13654 $1\svstate_ok_delay$next[0:0]$13655
- attribute \src "libresoc.v:199375.5-199375.29"
+ assign $0\svstate_ok_delay$next[0:0]$13446 $1\svstate_ok_delay$next[0:0]$13447
+ attribute \src "libresoc.v:199271.5-199271.29"
switch \initial
- attribute \src "libresoc.v:199375.9-199375.17"
+ attribute \src "libresoc.v:199271.9-199271.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\svstate_ok_delay$next[0:0]$13655 1'0
+ assign $1\svstate_ok_delay$next[0:0]$13447 1'0
case
- assign $1\svstate_ok_delay$next[0:0]$13655 \$40
+ assign $1\svstate_ok_delay$next[0:0]$13447 \$40
end
sync always
- update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13654
+ update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13446
end
- attribute \src "libresoc.v:199383.3-199398.6"
- process $proc$libresoc.v:199383$13656
+ attribute \src "libresoc.v:199279.3-199294.6"
+ process $proc$libresoc.v:199279$13448
assign { } { }
assign { } { }
assign { } { }
assign $0\svstate[63:0] $2\svstate[63:0]
- attribute \src "libresoc.v:199384.5-199384.29"
+ attribute \src "libresoc.v:199280.5-199280.29"
switch \initial
- attribute \src "libresoc.v:199384.9-199384.17"
+ attribute \src "libresoc.v:199280.9-199280.17"
case 1'1
case
end
sync always
update \svstate $0\svstate[63:0]
end
- attribute \src "libresoc.v:199399.3-199411.6"
- process $proc$libresoc.v:199399$13657
+ attribute \src "libresoc.v:199295.3-199307.6"
+ process $proc$libresoc.v:199295$13449
assign { } { }
assign { } { }
assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0]
- attribute \src "libresoc.v:199400.5-199400.29"
+ attribute \src "libresoc.v:199296.5-199296.29"
switch \initial
- attribute \src "libresoc.v:199400.9-199400.17"
+ attribute \src "libresoc.v:199296.9-199296.17"
case 1'1
case
end
sync always
update \core_sv__ren $0\core_sv__ren[2:0]
end
- attribute \src "libresoc.v:199412.3-199491.6"
- process $proc$libresoc.v:199412$13658
+ attribute \src "libresoc.v:199308.3-199387.6"
+ process $proc$libresoc.v:199308$13450
assign { } { }
assign { } { }
assign $0\core_wen[2:0] $1\core_wen[2:0]
- attribute \src "libresoc.v:199413.5-199413.29"
+ attribute \src "libresoc.v:199309.5-199309.29"
switch \initial
- attribute \src "libresoc.v:199413.9-199413.17"
+ attribute \src "libresoc.v:199309.9-199309.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_wen[2:0] $2\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$48
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\core_wen[2:0] $3\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'001
assign { } { }
assign $1\core_wen[2:0] $4\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\core_wen[2:0] $5\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
switch \$52
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_wen[2:0] $6\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$58
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $6\core_wen[2:0] $7\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $7\core_wen[2:0] $8\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch { \$64 \$60 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $6\core_wen[2:0] $9\core_wen[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_wen $0\core_wen[2:0]
end
- attribute \src "libresoc.v:199492.3-199571.6"
- process $proc$libresoc.v:199492$13659
+ attribute \src "libresoc.v:199388.3-199467.6"
+ process $proc$libresoc.v:199388$13451
assign { } { }
assign { } { }
assign $0\core_data_i[63:0] $1\core_data_i[63:0]
- attribute \src "libresoc.v:199493.5-199493.29"
+ attribute \src "libresoc.v:199389.5-199389.29"
switch \initial
- attribute \src "libresoc.v:199493.9-199493.17"
+ attribute \src "libresoc.v:199389.9-199389.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_data_i[63:0] $2\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$70
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\core_data_i[63:0] $3\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'001
assign { } { }
assign $1\core_data_i[63:0] $4\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\core_data_i[63:0] $5\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
switch \$74
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_data_i[63:0] $6\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$80
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $6\core_data_i[63:0] $7\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $7\core_data_i[63:0] $8\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch { \$86 \$82 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $6\core_data_i[63:0] $9\core_data_i[63:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_data_i $0\core_data_i[63:0]
end
- attribute \src "libresoc.v:199572.3-199587.6"
- process $proc$libresoc.v:199572$13660
+ attribute \src "libresoc.v:199468.3-199483.6"
+ process $proc$libresoc.v:199468$13452
assign { } { }
assign { } { }
assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0]
- attribute \src "libresoc.v:199573.5-199573.29"
+ attribute \src "libresoc.v:199469.5-199469.29"
switch \initial
- attribute \src "libresoc.v:199573.9-199573.17"
+ attribute \src "libresoc.v:199469.9-199469.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_msr__ren $0\core_msr__ren[2:0]
end
- attribute \src "libresoc.v:199588.3-199596.6"
- process $proc$libresoc.v:199588$13661
+ attribute \src "libresoc.v:199484.3-199492.6"
+ process $proc$libresoc.v:199484$13453
assign { } { }
assign { } { }
- assign $0\dbg_dmi_din$next[63:0]$13662 $1\dbg_dmi_din$next[63:0]$13663
- attribute \src "libresoc.v:199589.5-199589.29"
+ assign $0\dbg_dmi_din$next[63:0]$13454 $1\dbg_dmi_din$next[63:0]$13455
+ attribute \src "libresoc.v:199485.5-199485.29"
switch \initial
- attribute \src "libresoc.v:199589.9-199589.17"
+ attribute \src "libresoc.v:199485.9-199485.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_din$next[63:0]$13663 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\dbg_dmi_din$next[63:0]$13455 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\dbg_dmi_din$next[63:0]$13663 \jtag_dmi0__din
+ assign $1\dbg_dmi_din$next[63:0]$13455 \jtag_dmi0__din
end
sync always
- update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13662
+ update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13454
end
- attribute \src "libresoc.v:199597.3-199607.6"
- process $proc$libresoc.v:199597$13664
+ attribute \src "libresoc.v:199493.3-199503.6"
+ process $proc$libresoc.v:199493$13456
assign { } { }
assign { } { }
assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0]
- attribute \src "libresoc.v:199598.5-199598.29"
+ attribute \src "libresoc.v:199494.5-199494.29"
switch \initial
- attribute \src "libresoc.v:199598.9-199598.17"
+ attribute \src "libresoc.v:199494.9-199494.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0]
end
- attribute \src "libresoc.v:199608.3-199623.6"
- process $proc$libresoc.v:199608$13665
+ attribute \src "libresoc.v:199504.3-199519.6"
+ process $proc$libresoc.v:199504$13457
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:199609.5-199609.29"
+ attribute \src "libresoc.v:199505.5-199505.29"
switch \initial
- attribute \src "libresoc.v:199609.9-199609.17"
+ attribute \src "libresoc.v:199505.9-199505.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:199624.3-199632.6"
- process $proc$libresoc.v:199624$13666
+ attribute \src "libresoc.v:199520.3-199528.6"
+ process $proc$libresoc.v:199520$13458
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__ack_o$next[0:0]$13667 $1\jtag_dmi0__ack_o$next[0:0]$13668
- attribute \src "libresoc.v:199625.5-199625.29"
+ assign $0\jtag_dmi0__ack_o$next[0:0]$13459 $1\jtag_dmi0__ack_o$next[0:0]$13460
+ attribute \src "libresoc.v:199521.5-199521.29"
switch \initial
- attribute \src "libresoc.v:199625.9-199625.17"
+ attribute \src "libresoc.v:199521.9-199521.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__ack_o$next[0:0]$13668 1'0
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13460 1'0
case
- assign $1\jtag_dmi0__ack_o$next[0:0]$13668 \dbg_dmi_ack_o
+ assign $1\jtag_dmi0__ack_o$next[0:0]$13460 \dbg_dmi_ack_o
end
sync always
- update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13667
+ update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13459
end
- attribute \src "libresoc.v:199633.3-199666.6"
- process $proc$libresoc.v:199633$13669
+ attribute \src "libresoc.v:199529.3-199562.6"
+ process $proc$libresoc.v:199529$13461
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:199634.5-199634.29"
+ attribute \src "libresoc.v:199530.5-199530.29"
switch \initial
- attribute \src "libresoc.v:199634.9-199634.17"
+ attribute \src "libresoc.v:199530.9-199530.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'11
assign { } { }
assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:199667.3-199700.6"
- process $proc$libresoc.v:199667$13670
+ attribute \src "libresoc.v:199563.3-199596.6"
+ process $proc$libresoc.v:199563$13462
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:199668.5-199668.29"
+ attribute \src "libresoc.v:199564.5-199564.29"
switch \initial
- attribute \src "libresoc.v:199668.9-199668.17"
+ attribute \src "libresoc.v:199564.9-199564.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'01
assign { } { }
assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 2'11
assign { } { }
assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:199701.3-199721.6"
- process $proc$libresoc.v:199701$13671
+ attribute \src "libresoc.v:199597.3-199617.6"
+ process $proc$libresoc.v:199597$13463
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_pc$next[63:0]$13672 $3\dec2_cur_pc$next[63:0]$13675
- attribute \src "libresoc.v:199702.5-199702.29"
+ assign $0\dec2_cur_pc$next[63:0]$13464 $3\dec2_cur_pc$next[63:0]$13467
+ attribute \src "libresoc.v:199598.5-199598.29"
switch \initial
- attribute \src "libresoc.v:199702.9-199702.17"
+ attribute \src "libresoc.v:199598.9-199598.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\dec2_cur_pc$next[63:0]$13673 $2\dec2_cur_pc$next[63:0]$13674
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ assign $1\dec2_cur_pc$next[63:0]$13465 $2\dec2_cur_pc$next[63:0]$13466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_pc$next[63:0]$13674 \pc
+ assign $2\dec2_cur_pc$next[63:0]$13466 \pc
case
- assign $2\dec2_cur_pc$next[63:0]$13674 \dec2_cur_pc
+ assign $2\dec2_cur_pc$next[63:0]$13466 \dec2_cur_pc
end
case
- assign $1\dec2_cur_pc$next[63:0]$13673 \dec2_cur_pc
+ assign $1\dec2_cur_pc$next[63:0]$13465 \dec2_cur_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_pc$next[63:0]$13675 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_pc$next[63:0]$13467 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_pc$next[63:0]$13675 $1\dec2_cur_pc$next[63:0]$13673
+ assign $3\dec2_cur_pc$next[63:0]$13467 $1\dec2_cur_pc$next[63:0]$13465
end
sync always
- update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13672
+ update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13464
end
- attribute \src "libresoc.v:199722.3-199760.6"
- process $proc$libresoc.v:199722$13676
+ attribute \src "libresoc.v:199618.3-199656.6"
+ process $proc$libresoc.v:199618$13468
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cur_cur_dststep$next[6:0]$13677 $4\cur_cur_dststep$next[6:0]$13701
- assign $0\cur_cur_maxvl$next[6:0]$13678 $4\cur_cur_maxvl$next[6:0]$13702
- assign $0\cur_cur_srcstep$next[6:0]$13679 $4\cur_cur_srcstep$next[6:0]$13703
- assign $0\cur_cur_subvl$next[1:0]$13680 $4\cur_cur_subvl$next[1:0]$13704
- assign $0\cur_cur_svstep$next[1:0]$13681 $4\cur_cur_svstep$next[1:0]$13705
- assign $0\cur_cur_vl$next[6:0]$13682 $4\cur_cur_vl$next[6:0]$13706
- attribute \src "libresoc.v:199723.5-199723.29"
+ assign $0\cur_cur_dststep$next[6:0]$13469 $4\cur_cur_dststep$next[6:0]$13493
+ assign $0\cur_cur_maxvl$next[6:0]$13470 $4\cur_cur_maxvl$next[6:0]$13494
+ assign $0\cur_cur_srcstep$next[6:0]$13471 $4\cur_cur_srcstep$next[6:0]$13495
+ assign $0\cur_cur_subvl$next[1:0]$13472 $4\cur_cur_subvl$next[1:0]$13496
+ assign $0\cur_cur_svstep$next[1:0]$13473 $4\cur_cur_svstep$next[1:0]$13497
+ assign $0\cur_cur_vl$next[6:0]$13474 $4\cur_cur_vl$next[6:0]$13498
+ attribute \src "libresoc.v:199619.5-199619.29"
switch \initial
- attribute \src "libresoc.v:199723.9-199723.17"
+ attribute \src "libresoc.v:199619.9-199619.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
assign { } { }
assign { } { }
- assign $1\cur_cur_dststep$next[6:0]$13683 $2\cur_cur_dststep$next[6:0]$13689
- assign $1\cur_cur_maxvl$next[6:0]$13684 $2\cur_cur_maxvl$next[6:0]$13690
- assign $1\cur_cur_srcstep$next[6:0]$13685 $2\cur_cur_srcstep$next[6:0]$13691
- assign $1\cur_cur_subvl$next[1:0]$13686 $2\cur_cur_subvl$next[1:0]$13692
- assign $1\cur_cur_svstep$next[1:0]$13687 $2\cur_cur_svstep$next[1:0]$13693
- assign $1\cur_cur_vl$next[6:0]$13688 $2\cur_cur_vl$next[6:0]$13694
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ assign $1\cur_cur_dststep$next[6:0]$13475 $2\cur_cur_dststep$next[6:0]$13481
+ assign $1\cur_cur_maxvl$next[6:0]$13476 $2\cur_cur_maxvl$next[6:0]$13482
+ assign $1\cur_cur_srcstep$next[6:0]$13477 $2\cur_cur_srcstep$next[6:0]$13483
+ assign $1\cur_cur_subvl$next[1:0]$13478 $2\cur_cur_subvl$next[1:0]$13484
+ assign $1\cur_cur_svstep$next[1:0]$13479 $2\cur_cur_svstep$next[1:0]$13485
+ assign $1\cur_cur_vl$next[6:0]$13480 $2\cur_cur_vl$next[6:0]$13486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\cur_cur_maxvl$next[6:0]$13690 $2\cur_cur_vl$next[6:0]$13694 $2\cur_cur_srcstep$next[6:0]$13691 $2\cur_cur_dststep$next[6:0]$13689 $2\cur_cur_subvl$next[1:0]$13692 $2\cur_cur_svstep$next[1:0]$13693 } \svstate [31:0]
+ assign { $2\cur_cur_maxvl$next[6:0]$13482 $2\cur_cur_vl$next[6:0]$13486 $2\cur_cur_srcstep$next[6:0]$13483 $2\cur_cur_dststep$next[6:0]$13481 $2\cur_cur_subvl$next[1:0]$13484 $2\cur_cur_svstep$next[1:0]$13485 } \svstate [31:0]
case
- assign $2\cur_cur_dststep$next[6:0]$13689 \cur_cur_dststep
- assign $2\cur_cur_maxvl$next[6:0]$13690 \cur_cur_maxvl
- assign $2\cur_cur_srcstep$next[6:0]$13691 \cur_cur_srcstep
- assign $2\cur_cur_subvl$next[1:0]$13692 \cur_cur_subvl
- assign $2\cur_cur_svstep$next[1:0]$13693 \cur_cur_svstep
- assign $2\cur_cur_vl$next[6:0]$13694 \cur_cur_vl
+ assign $2\cur_cur_dststep$next[6:0]$13481 \cur_cur_dststep
+ assign $2\cur_cur_maxvl$next[6:0]$13482 \cur_cur_maxvl
+ assign $2\cur_cur_srcstep$next[6:0]$13483 \cur_cur_srcstep
+ assign $2\cur_cur_subvl$next[1:0]$13484 \cur_cur_subvl
+ assign $2\cur_cur_svstep$next[1:0]$13485 \cur_cur_svstep
+ assign $2\cur_cur_vl$next[6:0]$13486 \cur_cur_vl
end
case
- assign $1\cur_cur_dststep$next[6:0]$13683 \cur_cur_dststep
- assign $1\cur_cur_maxvl$next[6:0]$13684 \cur_cur_maxvl
- assign $1\cur_cur_srcstep$next[6:0]$13685 \cur_cur_srcstep
- assign $1\cur_cur_subvl$next[1:0]$13686 \cur_cur_subvl
- assign $1\cur_cur_svstep$next[1:0]$13687 \cur_cur_svstep
- assign $1\cur_cur_vl$next[6:0]$13688 \cur_cur_vl
+ assign $1\cur_cur_dststep$next[6:0]$13475 \cur_cur_dststep
+ assign $1\cur_cur_maxvl$next[6:0]$13476 \cur_cur_maxvl
+ assign $1\cur_cur_srcstep$next[6:0]$13477 \cur_cur_srcstep
+ assign $1\cur_cur_subvl$next[1:0]$13478 \cur_cur_subvl
+ assign $1\cur_cur_svstep$next[1:0]$13479 \cur_cur_svstep
+ assign $1\cur_cur_vl$next[6:0]$13480 \cur_cur_vl
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692"
switch \update_svstate
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $3\cur_cur_maxvl$next[6:0]$13696 $3\cur_cur_vl$next[6:0]$13700 $3\cur_cur_srcstep$next[6:0]$13697 $3\cur_cur_dststep$next[6:0]$13695 $3\cur_cur_subvl$next[1:0]$13698 $3\cur_cur_svstep$next[1:0]$13699 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
+ assign { $3\cur_cur_maxvl$next[6:0]$13488 $3\cur_cur_vl$next[6:0]$13492 $3\cur_cur_srcstep$next[6:0]$13489 $3\cur_cur_dststep$next[6:0]$13487 $3\cur_cur_subvl$next[1:0]$13490 $3\cur_cur_svstep$next[1:0]$13491 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep }
case
- assign $3\cur_cur_dststep$next[6:0]$13695 $1\cur_cur_dststep$next[6:0]$13683
- assign $3\cur_cur_maxvl$next[6:0]$13696 $1\cur_cur_maxvl$next[6:0]$13684
- assign $3\cur_cur_srcstep$next[6:0]$13697 $1\cur_cur_srcstep$next[6:0]$13685
- assign $3\cur_cur_subvl$next[1:0]$13698 $1\cur_cur_subvl$next[1:0]$13686
- assign $3\cur_cur_svstep$next[1:0]$13699 $1\cur_cur_svstep$next[1:0]$13687
- assign $3\cur_cur_vl$next[6:0]$13700 $1\cur_cur_vl$next[6:0]$13688
+ assign $3\cur_cur_dststep$next[6:0]$13487 $1\cur_cur_dststep$next[6:0]$13475
+ assign $3\cur_cur_maxvl$next[6:0]$13488 $1\cur_cur_maxvl$next[6:0]$13476
+ assign $3\cur_cur_srcstep$next[6:0]$13489 $1\cur_cur_srcstep$next[6:0]$13477
+ assign $3\cur_cur_subvl$next[1:0]$13490 $1\cur_cur_subvl$next[1:0]$13478
+ assign $3\cur_cur_svstep$next[1:0]$13491 $1\cur_cur_svstep$next[1:0]$13479
+ assign $3\cur_cur_vl$next[6:0]$13492 $1\cur_cur_vl$next[6:0]$13480
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\cur_cur_svstep$next[1:0]$13705 2'00
- assign $4\cur_cur_subvl$next[1:0]$13704 2'00
- assign $4\cur_cur_dststep$next[6:0]$13701 7'0000000
- assign $4\cur_cur_srcstep$next[6:0]$13703 7'0000000
- assign $4\cur_cur_vl$next[6:0]$13706 7'0000000
- assign $4\cur_cur_maxvl$next[6:0]$13702 7'0000000
+ assign $4\cur_cur_svstep$next[1:0]$13497 2'00
+ assign $4\cur_cur_subvl$next[1:0]$13496 2'00
+ assign $4\cur_cur_dststep$next[6:0]$13493 7'0000000
+ assign $4\cur_cur_srcstep$next[6:0]$13495 7'0000000
+ assign $4\cur_cur_vl$next[6:0]$13498 7'0000000
+ assign $4\cur_cur_maxvl$next[6:0]$13494 7'0000000
case
- assign $4\cur_cur_dststep$next[6:0]$13701 $3\cur_cur_dststep$next[6:0]$13695
- assign $4\cur_cur_maxvl$next[6:0]$13702 $3\cur_cur_maxvl$next[6:0]$13696
- assign $4\cur_cur_srcstep$next[6:0]$13703 $3\cur_cur_srcstep$next[6:0]$13697
- assign $4\cur_cur_subvl$next[1:0]$13704 $3\cur_cur_subvl$next[1:0]$13698
- assign $4\cur_cur_svstep$next[1:0]$13705 $3\cur_cur_svstep$next[1:0]$13699
- assign $4\cur_cur_vl$next[6:0]$13706 $3\cur_cur_vl$next[6:0]$13700
+ assign $4\cur_cur_dststep$next[6:0]$13493 $3\cur_cur_dststep$next[6:0]$13487
+ assign $4\cur_cur_maxvl$next[6:0]$13494 $3\cur_cur_maxvl$next[6:0]$13488
+ assign $4\cur_cur_srcstep$next[6:0]$13495 $3\cur_cur_srcstep$next[6:0]$13489
+ assign $4\cur_cur_subvl$next[1:0]$13496 $3\cur_cur_subvl$next[1:0]$13490
+ assign $4\cur_cur_svstep$next[1:0]$13497 $3\cur_cur_svstep$next[1:0]$13491
+ assign $4\cur_cur_vl$next[6:0]$13498 $3\cur_cur_vl$next[6:0]$13492
end
sync always
- update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13677
- update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13678
- update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13679
- update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13680
- update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13681
- update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13682
+ update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13469
+ update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13470
+ update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13471
+ update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13472
+ update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13473
+ update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13474
end
- attribute \src "libresoc.v:199761.3-199790.6"
- process $proc$libresoc.v:199761$13707
+ attribute \src "libresoc.v:199657.3-199686.6"
+ process $proc$libresoc.v:199657$13499
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr_read$next[0:0]$13708 $4\msr_read$next[0:0]$13712
- attribute \src "libresoc.v:199762.5-199762.29"
+ assign $0\msr_read$next[0:0]$13500 $4\msr_read$next[0:0]$13504
+ attribute \src "libresoc.v:199658.5-199658.29"
switch \initial
- attribute \src "libresoc.v:199762.9-199762.17"
+ attribute \src "libresoc.v:199658.9-199658.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\msr_read$next[0:0]$13709 $2\msr_read$next[0:0]$13710
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ assign $1\msr_read$next[0:0]$13501 $2\msr_read$next[0:0]$13502
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_read$next[0:0]$13710 1'0
+ assign $2\msr_read$next[0:0]$13502 1'0
case
- assign $2\msr_read$next[0:0]$13710 \msr_read
+ assign $2\msr_read$next[0:0]$13502 \msr_read
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\msr_read$next[0:0]$13709 $3\msr_read$next[0:0]$13711
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ assign $1\msr_read$next[0:0]$13501 $3\msr_read$next[0:0]$13503
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
switch \$88
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr_read$next[0:0]$13711 1'1
+ assign $3\msr_read$next[0:0]$13503 1'1
case
- assign $3\msr_read$next[0:0]$13711 \msr_read
+ assign $3\msr_read$next[0:0]$13503 \msr_read
end
case
- assign $1\msr_read$next[0:0]$13709 \msr_read
+ assign $1\msr_read$next[0:0]$13501 \msr_read
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr_read$next[0:0]$13712 1'1
+ assign $4\msr_read$next[0:0]$13504 1'1
case
- assign $4\msr_read$next[0:0]$13712 $1\msr_read$next[0:0]$13709
+ assign $4\msr_read$next[0:0]$13504 $1\msr_read$next[0:0]$13501
end
sync always
- update \msr_read$next $0\msr_read$next[0:0]$13708
+ update \msr_read$next $0\msr_read$next[0:0]$13500
end
- attribute \src "libresoc.v:199791.3-199799.6"
- process $proc$libresoc.v:199791$13713
+ attribute \src "libresoc.v:199687.3-199695.6"
+ process $proc$libresoc.v:199687$13505
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__dout$next[63:0]$13714 $1\jtag_dmi0__dout$next[63:0]$13715
- attribute \src "libresoc.v:199792.5-199792.29"
+ assign $0\jtag_dmi0__dout$next[63:0]$13506 $1\jtag_dmi0__dout$next[63:0]$13507
+ attribute \src "libresoc.v:199688.5-199688.29"
switch \initial
- attribute \src "libresoc.v:199792.9-199792.17"
+ attribute \src "libresoc.v:199688.9-199688.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__dout$next[63:0]$13715 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\jtag_dmi0__dout$next[63:0]$13507 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\jtag_dmi0__dout$next[63:0]$13715 \dbg_dmi_dout
+ assign $1\jtag_dmi0__dout$next[63:0]$13507 \dbg_dmi_dout
end
sync always
- update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13714
+ update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13506
end
- attribute \src "libresoc.v:199800.3-199853.6"
- process $proc$libresoc.v:199800$13716
+ attribute \src "libresoc.v:199696.3-199749.6"
+ process $proc$libresoc.v:199696$13508
assign { } { }
assign { } { }
assign { } { }
- assign $0\fetch_fsm_state$next[1:0]$13717 $6\fetch_fsm_state$next[1:0]$13723
- attribute \src "libresoc.v:199801.5-199801.29"
+ assign $0\fetch_fsm_state$next[1:0]$13509 $6\fetch_fsm_state$next[1:0]$13515
+ attribute \src "libresoc.v:199697.5-199697.29"
switch \initial
- attribute \src "libresoc.v:199801.9-199801.17"
+ attribute \src "libresoc.v:199697.9-199697.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13718 $2\fetch_fsm_state$next[1:0]$13719
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
+ assign $1\fetch_fsm_state$next[1:0]$13510 $2\fetch_fsm_state$next[1:0]$13511
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288"
switch \fetch_pc_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fetch_fsm_state$next[1:0]$13719 2'01
+ assign $2\fetch_fsm_state$next[1:0]$13511 2'01
case
- assign $2\fetch_fsm_state$next[1:0]$13719 \fetch_fsm_state
+ assign $2\fetch_fsm_state$next[1:0]$13511 \fetch_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13718 $3\fetch_fsm_state$next[1:0]$13720
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
+ assign $1\fetch_fsm_state$next[1:0]$13510 $3\fetch_fsm_state$next[1:0]$13512
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\fetch_fsm_state$next[1:0]$13720 \fetch_fsm_state
+ assign $3\fetch_fsm_state$next[1:0]$13512 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\fetch_fsm_state$next[1:0]$13720 2'10
+ assign $3\fetch_fsm_state$next[1:0]$13512 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13718 $4\fetch_fsm_state$next[1:0]$13721
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ assign $1\fetch_fsm_state$next[1:0]$13510 $4\fetch_fsm_state$next[1:0]$13513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\fetch_fsm_state$next[1:0]$13721 \fetch_fsm_state
+ assign $4\fetch_fsm_state$next[1:0]$13513 \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\fetch_fsm_state$next[1:0]$13721 2'10
+ assign $4\fetch_fsm_state$next[1:0]$13513 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fetch_fsm_state$next[1:0]$13718 $5\fetch_fsm_state$next[1:0]$13722
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372"
+ assign $1\fetch_fsm_state$next[1:0]$13510 $5\fetch_fsm_state$next[1:0]$13514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:377"
switch \fetch_insn_ready_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fetch_fsm_state$next[1:0]$13722 2'00
+ assign $5\fetch_fsm_state$next[1:0]$13514 2'00
case
- assign $5\fetch_fsm_state$next[1:0]$13722 \fetch_fsm_state
+ assign $5\fetch_fsm_state$next[1:0]$13514 \fetch_fsm_state
end
case
- assign $1\fetch_fsm_state$next[1:0]$13718 \fetch_fsm_state
+ assign $1\fetch_fsm_state$next[1:0]$13510 \fetch_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\fetch_fsm_state$next[1:0]$13723 2'00
+ assign $6\fetch_fsm_state$next[1:0]$13515 2'00
case
- assign $6\fetch_fsm_state$next[1:0]$13723 $1\fetch_fsm_state$next[1:0]$13718
+ assign $6\fetch_fsm_state$next[1:0]$13515 $1\fetch_fsm_state$next[1:0]$13510
end
sync always
- update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13717
+ update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13509
end
- attribute \src "libresoc.v:199854.3-199878.6"
- process $proc$libresoc.v:199854$13724
+ attribute \src "libresoc.v:199750.3-199774.6"
+ process $proc$libresoc.v:199750$13516
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_msr$next[63:0]$13725 $3\dec2_cur_msr$next[63:0]$13728
- attribute \src "libresoc.v:199855.5-199855.29"
+ assign $0\dec2_cur_msr$next[63:0]$13517 $3\dec2_cur_msr$next[63:0]$13520
+ attribute \src "libresoc.v:199751.5-199751.29"
switch \initial
- attribute \src "libresoc.v:199855.9-199855.17"
+ attribute \src "libresoc.v:199751.9-199751.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_cur_msr$next[63:0]$13726 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$13518 \dec2_cur_msr
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_msr$next[63:0]$13726 $2\dec2_cur_msr$next[63:0]$13727
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:303"
+ assign $1\dec2_cur_msr$next[63:0]$13518 $2\dec2_cur_msr$next[63:0]$13519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308"
switch \$90
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_msr$next[63:0]$13727 \core_msr__data_o
+ assign $2\dec2_cur_msr$next[63:0]$13519 \core_msr__data_o
case
- assign $2\dec2_cur_msr$next[63:0]$13727 \dec2_cur_msr
+ assign $2\dec2_cur_msr$next[63:0]$13519 \dec2_cur_msr
end
case
- assign $1\dec2_cur_msr$next[63:0]$13726 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$13518 \dec2_cur_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_msr$next[63:0]$13728 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_msr$next[63:0]$13520 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_msr$next[63:0]$13728 $1\dec2_cur_msr$next[63:0]$13726
+ assign $3\dec2_cur_msr$next[63:0]$13520 $1\dec2_cur_msr$next[63:0]$13518
end
sync always
- update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13725
+ update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13517
end
- attribute \src "libresoc.v:199879.3-199901.6"
- process $proc$libresoc.v:199879$13729
+ attribute \src "libresoc.v:199775.3-199797.6"
+ process $proc$libresoc.v:199775$13521
assign { } { }
assign { } { }
- assign $0\nia$next[63:0]$13730 $1\nia$next[63:0]$13731
- attribute \src "libresoc.v:199880.5-199880.29"
+ assign $0\nia$next[63:0]$13522 $1\nia$next[63:0]$13523
+ attribute \src "libresoc.v:199776.5-199776.29"
switch \initial
- attribute \src "libresoc.v:199880.9-199880.17"
+ attribute \src "libresoc.v:199776.9-199776.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\nia$next[63:0]$13731 \nia
+ assign $1\nia$next[63:0]$13523 \nia
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\nia$next[63:0]$13731 $2\nia$next[63:0]$13732
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
+ assign $1\nia$next[63:0]$13523 $2\nia$next[63:0]$13524
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\nia$next[63:0]$13732 \nia
+ assign $2\nia$next[63:0]$13524 \nia
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\nia$next[63:0]$13732 \$92 [63:0]
+ assign $2\nia$next[63:0]$13524 \$92 [63:0]
end
case
- assign $1\nia$next[63:0]$13731 \nia
+ assign $1\nia$next[63:0]$13523 \nia
end
sync always
- update \nia$next $0\nia$next[63:0]$13730
+ update \nia$next $0\nia$next[63:0]$13522
end
- attribute \src "libresoc.v:199902.3-199936.6"
- process $proc$libresoc.v:199902$13733
+ attribute \src "libresoc.v:199798.3-199832.6"
+ process $proc$libresoc.v:199798$13525
assign { } { }
assign { } { }
- assign $0\dec2_raw_opcode_in$next[31:0]$13734 $1\dec2_raw_opcode_in$next[31:0]$13735
- attribute \src "libresoc.v:199903.5-199903.29"
+ assign $0\dec2_raw_opcode_in$next[31:0]$13526 $1\dec2_raw_opcode_in$next[31:0]$13527
+ attribute \src "libresoc.v:199799.5-199799.29"
switch \initial
- attribute \src "libresoc.v:199903.9-199903.17"
+ attribute \src "libresoc.v:199799.9-199799.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
- assign $1\dec2_raw_opcode_in$next[31:0]$13735 \dec2_raw_opcode_in
+ assign $1\dec2_raw_opcode_in$next[31:0]$13527 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_raw_opcode_in$next[31:0]$13735 $2\dec2_raw_opcode_in$next[31:0]$13736
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306"
+ assign $1\dec2_raw_opcode_in$next[31:0]$13527 $2\dec2_raw_opcode_in$next[31:0]$13528
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\dec2_raw_opcode_in$next[31:0]$13736 \dec2_raw_opcode_in
+ assign $2\dec2_raw_opcode_in$next[31:0]$13528 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\dec2_raw_opcode_in$next[31:0]$13736 \$95
+ assign $2\dec2_raw_opcode_in$next[31:0]$13528 \$95
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\dec2_raw_opcode_in$next[31:0]$13735 $3\dec2_raw_opcode_in$next[31:0]$13737
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344"
+ assign $1\dec2_raw_opcode_in$next[31:0]$13527 $3\dec2_raw_opcode_in$next[31:0]$13529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\dec2_raw_opcode_in$next[31:0]$13737 \dec2_raw_opcode_in
+ assign $3\dec2_raw_opcode_in$next[31:0]$13529 \dec2_raw_opcode_in
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\dec2_raw_opcode_in$next[31:0]$13737 \$99
+ assign $3\dec2_raw_opcode_in$next[31:0]$13529 \$99
end
case
- assign $1\dec2_raw_opcode_in$next[31:0]$13735 \dec2_raw_opcode_in
+ assign $1\dec2_raw_opcode_in$next[31:0]$13527 \dec2_raw_opcode_in
end
sync always
- update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13734
+ update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13526
end
- attribute \src "libresoc.v:199937.3-199959.6"
- process $proc$libresoc.v:199937$13738
+ attribute \src "libresoc.v:199833.3-199855.6"
+ process $proc$libresoc.v:199833$13530
assign { } { }
assign { } { }
assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0]
- attribute \src "libresoc.v:199938.5-199938.29"
+ attribute \src "libresoc.v:199834.5-199834.29"
switch \initial
- attribute \src "libresoc.v:199938.9-199938.17"
+ attribute \src "libresoc.v:199834.9-199834.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:283"
switch \fetch_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 2'00
sync always
update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0]
end
- attribute \src "libresoc.v:199960.3-200035.6"
- process $proc$libresoc.v:199960$13739
+ attribute \src "libresoc.v:199856.3-199931.6"
+ process $proc$libresoc.v:199856$13531
assign { } { }
assign { } { }
assign { } { }
assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0]
assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0]
assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0]
- attribute \src "libresoc.v:199961.5-199961.29"
+ attribute \src "libresoc.v:199857.5-199857.29"
switch \initial
- attribute \src "libresoc.v:199961.9-199961.17"
+ attribute \src "libresoc.v:199857.9-199857.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0]
assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0]
assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$110
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0]
assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0]
assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0]
assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0]
assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$116
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign $4\new_svstate_vl[6:0] \cur_cur_vl
assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0]
assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0]
assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch { \$122 \$118 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0]
assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0]
assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
update \new_svstate_svstep $0\new_svstate_svstep[1:0]
update \new_svstate_vl $0\new_svstate_vl[6:0]
end
- attribute \src "libresoc.v:200036.3-200051.6"
- process $proc$libresoc.v:200036$13740
+ attribute \src "libresoc.v:199932.3-199947.6"
+ process $proc$libresoc.v:199932$13532
assign { } { }
assign { } { }
assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0]
- attribute \src "libresoc.v:200037.5-200037.29"
+ attribute \src "libresoc.v:199933.5-199933.29"
switch \initial
- attribute \src "libresoc.v:200037.9-200037.17"
+ attribute \src "libresoc.v:199933.9-199933.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$134
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0]
end
- attribute \src "libresoc.v:200052.3-200150.6"
- process $proc$libresoc.v:200052$13741
+ attribute \src "libresoc.v:199948.3-200046.6"
+ process $proc$libresoc.v:199948$13533
assign { } { }
assign { } { }
assign { } { }
- assign $0\issue_fsm_state$next[2:0]$13742 $12\issue_fsm_state$next[2:0]$13754
- attribute \src "libresoc.v:200053.5-200053.29"
+ assign $0\issue_fsm_state$next[2:0]$13534 $12\issue_fsm_state$next[2:0]$13546
+ attribute \src "libresoc.v:199949.5-199949.29"
switch \initial
- attribute \src "libresoc.v:200053.9-200053.17"
+ attribute \src "libresoc.v:199949.9-199949.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $2\issue_fsm_state$next[2:0]$13744
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ assign $1\issue_fsm_state$next[2:0]$13535 $2\issue_fsm_state$next[2:0]$13536
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$140
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\issue_fsm_state$next[2:0]$13744 $3\issue_fsm_state$next[2:0]$13745
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523"
+ assign $2\issue_fsm_state$next[2:0]$13536 $3\issue_fsm_state$next[2:0]$13537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:528"
switch \fetch_pc_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\issue_fsm_state$next[2:0]$13745 3'001
+ assign $3\issue_fsm_state$next[2:0]$13537 3'001
case
- assign $3\issue_fsm_state$next[2:0]$13745 \issue_fsm_state
+ assign $3\issue_fsm_state$next[2:0]$13537 \issue_fsm_state
end
case
- assign $2\issue_fsm_state$next[2:0]$13744 \issue_fsm_state
+ assign $2\issue_fsm_state$next[2:0]$13536 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $4\issue_fsm_state$next[2:0]$13746
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\issue_fsm_state$next[2:0]$13535 $4\issue_fsm_state$next[2:0]$13538
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\issue_fsm_state$next[2:0]$13746 $5\issue_fsm_state$next[2:0]$13747
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:554"
+ assign $4\issue_fsm_state$next[2:0]$13538 $5\issue_fsm_state$next[2:0]$13539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559"
switch \$144
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\issue_fsm_state$next[2:0]$13747 3'000
+ assign $5\issue_fsm_state$next[2:0]$13539 3'000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $5\issue_fsm_state$next[2:0]$13747 3'010
+ assign $5\issue_fsm_state$next[2:0]$13539 3'010
end
case
- assign $4\issue_fsm_state$next[2:0]$13746 \issue_fsm_state
+ assign $4\issue_fsm_state$next[2:0]$13538 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $6\issue_fsm_state$next[2:0]$13748
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:570"
+ assign $1\issue_fsm_state$next[2:0]$13535 $6\issue_fsm_state$next[2:0]$13540
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:575"
switch \pred_insn_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\issue_fsm_state$next[2:0]$13748 3'100
+ assign $6\issue_fsm_state$next[2:0]$13540 3'100
case
- assign $6\issue_fsm_state$next[2:0]$13748 \issue_fsm_state
+ assign $6\issue_fsm_state$next[2:0]$13540 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'100
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $7\issue_fsm_state$next[2:0]$13749
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:575"
+ assign $1\issue_fsm_state$next[2:0]$13535 $7\issue_fsm_state$next[2:0]$13541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580"
switch \pred_mask_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\issue_fsm_state$next[2:0]$13749 3'010
+ assign $7\issue_fsm_state$next[2:0]$13541 3'010
case
- assign $7\issue_fsm_state$next[2:0]$13749 \issue_fsm_state
+ assign $7\issue_fsm_state$next[2:0]$13541 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'010
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $8\issue_fsm_state$next[2:0]$13750
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616"
+ assign $1\issue_fsm_state$next[2:0]$13535 $8\issue_fsm_state$next[2:0]$13542
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621"
switch \exec_insn_ready_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\issue_fsm_state$next[2:0]$13750 3'101
+ assign $8\issue_fsm_state$next[2:0]$13542 3'101
case
- assign $8\issue_fsm_state$next[2:0]$13750 \issue_fsm_state
+ assign $8\issue_fsm_state$next[2:0]$13542 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 $9\issue_fsm_state$next[2:0]$13751
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ assign $1\issue_fsm_state$next[2:0]$13535 $9\issue_fsm_state$next[2:0]$13543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$150
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\issue_fsm_state$next[2:0]$13751 $10\issue_fsm_state$next[2:0]$13752
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ assign $9\issue_fsm_state$next[2:0]$13543 $10\issue_fsm_state$next[2:0]$13544
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $10\issue_fsm_state$next[2:0]$13752 $11\issue_fsm_state$next[2:0]$13753
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ assign $10\issue_fsm_state$next[2:0]$13544 $11\issue_fsm_state$next[2:0]$13545
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch { \$156 \$152 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13753 3'000
+ assign $11\issue_fsm_state$next[2:0]$13545 3'000
attribute \src "libresoc.v:0.0-0.0"
case 2'1-
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13753 3'000
+ assign $11\issue_fsm_state$next[2:0]$13545 3'000
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $11\issue_fsm_state$next[2:0]$13753 3'110
+ assign $11\issue_fsm_state$next[2:0]$13545 3'110
end
case
- assign $10\issue_fsm_state$next[2:0]$13752 \issue_fsm_state
+ assign $10\issue_fsm_state$next[2:0]$13544 \issue_fsm_state
end
case
- assign $9\issue_fsm_state$next[2:0]$13751 \issue_fsm_state
+ assign $9\issue_fsm_state$next[2:0]$13543 \issue_fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
- assign $1\issue_fsm_state$next[2:0]$13743 3'010
+ assign $1\issue_fsm_state$next[2:0]$13535 3'010
case
- assign $1\issue_fsm_state$next[2:0]$13743 \issue_fsm_state
+ assign $1\issue_fsm_state$next[2:0]$13535 \issue_fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $12\issue_fsm_state$next[2:0]$13754 3'000
+ assign $12\issue_fsm_state$next[2:0]$13546 3'000
case
- assign $12\issue_fsm_state$next[2:0]$13754 $1\issue_fsm_state$next[2:0]$13743
+ assign $12\issue_fsm_state$next[2:0]$13546 $1\issue_fsm_state$next[2:0]$13535
end
sync always
- update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13742
+ update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13534
end
- attribute \src "libresoc.v:200151.3-200197.6"
- process $proc$libresoc.v:200151$13755
+ attribute \src "libresoc.v:200047.3-200093.6"
+ process $proc$libresoc.v:200047$13547
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:200152.5-200152.29"
+ attribute \src "libresoc.v:200048.5-200048.29"
switch \initial
- attribute \src "libresoc.v:200152.9-200152.17"
+ attribute \src "libresoc.v:200048.9-200048.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$162
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$168
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:200198.3-200244.6"
- process $proc$libresoc.v:200198$13756
+ attribute \src "libresoc.v:200094.3-200140.6"
+ process $proc$libresoc.v:200094$13548
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:200199.5-200199.29"
+ attribute \src "libresoc.v:200095.5-200095.29"
switch \initial
- attribute \src "libresoc.v:200199.9-200199.17"
+ attribute \src "libresoc.v:200095.9-200095.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$174
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$180
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- attribute \src "libresoc.v:200245.3-200327.6"
- process $proc$libresoc.v:200245$13757
+ attribute \src "libresoc.v:200141.3-200223.6"
+ process $proc$libresoc.v:200141$13549
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\pc_changed$next[0:0]$13758 $9\pc_changed$next[0:0]$13767
- attribute \src "libresoc.v:200246.5-200246.29"
+ assign $0\pc_changed$next[0:0]$13550 $9\pc_changed$next[0:0]$13559
+ attribute \src "libresoc.v:200142.5-200142.29"
switch \initial
- attribute \src "libresoc.v:200246.9-200246.17"
+ attribute \src "libresoc.v:200142.9-200142.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\pc_changed$next[0:0]$13759 $2\pc_changed$next[0:0]$13760
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ assign $1\pc_changed$next[0:0]$13551 $2\pc_changed$next[0:0]$13552
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$186
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\pc_changed$next[0:0]$13760 \pc_changed
+ assign $2\pc_changed$next[0:0]$13552 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\pc_changed$next[0:0]$13760 $3\pc_changed$next[0:0]$13761
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:530"
+ assign $2\pc_changed$next[0:0]$13552 $3\pc_changed$next[0:0]$13553
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\pc_changed$next[0:0]$13761 1'1
+ assign $3\pc_changed$next[0:0]$13553 1'1
case
- assign $3\pc_changed$next[0:0]$13761 \pc_changed
+ assign $3\pc_changed$next[0:0]$13553 \pc_changed
end
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\pc_changed$next[0:0]$13759 \pc_changed
+ assign $1\pc_changed$next[0:0]$13551 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\pc_changed$next[0:0]$13759 \pc_changed
+ assign $1\pc_changed$next[0:0]$13551 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\pc_changed$next[0:0]$13759 \pc_changed
+ assign $1\pc_changed$next[0:0]$13551 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\pc_changed$next[0:0]$13759 \pc_changed
+ assign $1\pc_changed$next[0:0]$13551 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\pc_changed$next[0:0]$13759 $4\pc_changed$next[0:0]$13762
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ assign $1\pc_changed$next[0:0]$13551 $4\pc_changed$next[0:0]$13554
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$192
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\pc_changed$next[0:0]$13762 \pc_changed
+ assign $4\pc_changed$next[0:0]$13554 \pc_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\pc_changed$next[0:0]$13762 $5\pc_changed$next[0:0]$13763
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666"
+ assign $4\pc_changed$next[0:0]$13554 $5\pc_changed$next[0:0]$13555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:671"
switch \pc_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\pc_changed$next[0:0]$13763 1'1
+ assign $5\pc_changed$next[0:0]$13555 1'1
case
- assign $5\pc_changed$next[0:0]$13763 \pc_changed
+ assign $5\pc_changed$next[0:0]$13555 \pc_changed
end
end
case
- assign $1\pc_changed$next[0:0]$13759 \pc_changed
+ assign $1\pc_changed$next[0:0]$13551 \pc_changed
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $6\pc_changed$next[0:0]$13764 $7\pc_changed$next[0:0]$13765
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ assign $6\pc_changed$next[0:0]$13556 $7\pc_changed$next[0:0]$13557
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\pc_changed$next[0:0]$13765 1'0
+ assign $7\pc_changed$next[0:0]$13557 1'0
case
- assign $7\pc_changed$next[0:0]$13765 $1\pc_changed$next[0:0]$13759
+ assign $7\pc_changed$next[0:0]$13557 $1\pc_changed$next[0:0]$13551
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\pc_changed$next[0:0]$13764 $8\pc_changed$next[0:0]$13766
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732"
+ assign $6\pc_changed$next[0:0]$13556 $8\pc_changed$next[0:0]$13558
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:737"
switch \$194
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\pc_changed$next[0:0]$13766 1'1
+ assign $8\pc_changed$next[0:0]$13558 1'1
case
- assign $8\pc_changed$next[0:0]$13766 $1\pc_changed$next[0:0]$13759
+ assign $8\pc_changed$next[0:0]$13558 $1\pc_changed$next[0:0]$13551
end
case
- assign $6\pc_changed$next[0:0]$13764 $1\pc_changed$next[0:0]$13759
+ assign $6\pc_changed$next[0:0]$13556 $1\pc_changed$next[0:0]$13551
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\pc_changed$next[0:0]$13767 1'0
+ assign $9\pc_changed$next[0:0]$13559 1'0
case
- assign $9\pc_changed$next[0:0]$13767 $6\pc_changed$next[0:0]$13764
+ assign $9\pc_changed$next[0:0]$13559 $6\pc_changed$next[0:0]$13556
end
sync always
- update \pc_changed$next $0\pc_changed$next[0:0]$13758
+ update \pc_changed$next $0\pc_changed$next[0:0]$13550
end
- attribute \src "libresoc.v:200328.3-200400.6"
- process $proc$libresoc.v:200328$13768
+ attribute \src "libresoc.v:200224.3-200296.6"
+ process $proc$libresoc.v:200224$13560
assign { } { }
assign { } { }
assign $0\update_svstate[0:0] $1\update_svstate[0:0]
- attribute \src "libresoc.v:200329.5-200329.29"
+ attribute \src "libresoc.v:200225.5-200225.29"
switch \initial
- attribute \src "libresoc.v:200329.9-200329.17"
+ attribute \src "libresoc.v:200225.9-200225.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
assign $1\update_svstate[0:0] $2\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$202
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case
assign { } { }
assign $2\update_svstate[0:0] $3\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
case 3'101
assign { } { }
assign $1\update_svstate[0:0] $4\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$208
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $4\update_svstate[0:0] $5\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:629"
switch \exec_pc_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign $5\update_svstate[0:0] $6\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639"
switch { \$214 \$210 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
case
assign { } { }
assign $4\update_svstate[0:0] $7\update_svstate[0:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
sync always
update \update_svstate $0\update_svstate[0:0]
end
- attribute \src "libresoc.v:200401.3-200483.6"
- process $proc$libresoc.v:200401$13769
+ attribute \src "libresoc.v:200297.3-200379.6"
+ process $proc$libresoc.v:200297$13561
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\sv_changed$next[0:0]$13770 $9\sv_changed$next[0:0]$13779
- attribute \src "libresoc.v:200402.5-200402.29"
+ assign $0\sv_changed$next[0:0]$13562 $9\sv_changed$next[0:0]$13571
+ attribute \src "libresoc.v:200298.5-200298.29"
switch \initial
- attribute \src "libresoc.v:200402.9-200402.17"
+ attribute \src "libresoc.v:200298.9-200298.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
assign { } { }
- assign $1\sv_changed$next[0:0]$13771 $2\sv_changed$next[0:0]$13772
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521"
+ assign $1\sv_changed$next[0:0]$13563 $2\sv_changed$next[0:0]$13564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526"
switch \$220
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\sv_changed$next[0:0]$13772 \sv_changed
+ assign $2\sv_changed$next[0:0]$13564 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\sv_changed$next[0:0]$13772 $3\sv_changed$next[0:0]$13773
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534"
+ assign $2\sv_changed$next[0:0]$13564 $3\sv_changed$next[0:0]$13565
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\sv_changed$next[0:0]$13773 1'1
+ assign $3\sv_changed$next[0:0]$13565 1'1
case
- assign $3\sv_changed$next[0:0]$13773 \sv_changed
+ assign $3\sv_changed$next[0:0]$13565 \sv_changed
end
end
attribute \src "libresoc.v:0.0-0.0"
case 3'001
- assign $1\sv_changed$next[0:0]$13771 \sv_changed
+ assign $1\sv_changed$next[0:0]$13563 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\sv_changed$next[0:0]$13771 \sv_changed
+ assign $1\sv_changed$next[0:0]$13563 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\sv_changed$next[0:0]$13771 \sv_changed
+ assign $1\sv_changed$next[0:0]$13563 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\sv_changed$next[0:0]$13771 \sv_changed
+ assign $1\sv_changed$next[0:0]$13563 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case 3'101
assign { } { }
- assign $1\sv_changed$next[0:0]$13771 $4\sv_changed$next[0:0]$13774
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622"
+ assign $1\sv_changed$next[0:0]$13563 $4\sv_changed$next[0:0]$13566
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627"
switch \$226
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $4\sv_changed$next[0:0]$13774 \sv_changed
+ assign $4\sv_changed$next[0:0]$13566 \sv_changed
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $4\sv_changed$next[0:0]$13774 $5\sv_changed$next[0:0]$13775
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:670"
+ assign $4\sv_changed$next[0:0]$13566 $5\sv_changed$next[0:0]$13567
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675"
switch \svstate_i_ok
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\sv_changed$next[0:0]$13775 1'1
+ assign $5\sv_changed$next[0:0]$13567 1'1
case
- assign $5\sv_changed$next[0:0]$13775 \sv_changed
+ assign $5\sv_changed$next[0:0]$13567 \sv_changed
end
end
case
- assign $1\sv_changed$next[0:0]$13771 \sv_changed
+ assign $1\sv_changed$next[0:0]$13563 \sv_changed
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:713"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
switch \exec_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 1'0
assign { } { }
- assign $6\sv_changed$next[0:0]$13776 $7\sv_changed$next[0:0]$13777
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:718"
+ assign $6\sv_changed$next[0:0]$13568 $7\sv_changed$next[0:0]$13569
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723"
switch \exec_insn_valid_i
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $7\sv_changed$next[0:0]$13777 1'0
+ assign $7\sv_changed$next[0:0]$13569 1'0
case
- assign $7\sv_changed$next[0:0]$13777 $1\sv_changed$next[0:0]$13771
+ assign $7\sv_changed$next[0:0]$13569 $1\sv_changed$next[0:0]$13563
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $6\sv_changed$next[0:0]$13776 $8\sv_changed$next[0:0]$13778
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730"
+ assign $6\sv_changed$next[0:0]$13568 $8\sv_changed$next[0:0]$13570
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735"
switch \$228
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $8\sv_changed$next[0:0]$13778 1'1
+ assign $8\sv_changed$next[0:0]$13570 1'1
case
- assign $8\sv_changed$next[0:0]$13778 $1\sv_changed$next[0:0]$13771
+ assign $8\sv_changed$next[0:0]$13570 $1\sv_changed$next[0:0]$13563
end
case
- assign $6\sv_changed$next[0:0]$13776 $1\sv_changed$next[0:0]$13771
+ assign $6\sv_changed$next[0:0]$13568 $1\sv_changed$next[0:0]$13563
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $9\sv_changed$next[0:0]$13779 1'0
+ assign $9\sv_changed$next[0:0]$13571 1'0
case
- assign $9\sv_changed$next[0:0]$13779 $6\sv_changed$next[0:0]$13776
+ assign $9\sv_changed$next[0:0]$13571 $6\sv_changed$next[0:0]$13568
end
sync always
- update \sv_changed$next $0\sv_changed$next[0:0]$13770
+ update \sv_changed$next $0\sv_changed$next[0:0]$13562
end
- attribute \src "libresoc.v:200484.3-200498.6"
- process $proc$libresoc.v:200484$13780
+ attribute \src "libresoc.v:200380.3-200394.6"
+ process $proc$libresoc.v:200380$13572
assign { } { }
assign { } { }
assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0]
- attribute \src "libresoc.v:200485.5-200485.29"
+ attribute \src "libresoc.v:200381.5-200381.29"
switch \initial
- attribute \src "libresoc.v:200485.9-200485.17"
+ attribute \src "libresoc.v:200381.9-200381.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
sync always
update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0]
end
- attribute \src "libresoc.v:200499.3-200629.6"
- process $proc$libresoc.v:200499$13781
+ attribute \src "libresoc.v:200395.3-200525.6"
+ process $proc$libresoc.v:200395$13573
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_asmcode$next[7:0]$13782 $1\core_asmcode$next[7:0]$13841
- assign $0\core_core_core_cia$next[63:0]$13783 $1\core_core_core_cia$next[63:0]$13842
- assign $0\core_core_core_cr_rd$next[7:0]$13784 $1\core_core_core_cr_rd$next[7:0]$13843
+ assign $0\core_asmcode$next[7:0]$13574 $1\core_asmcode$next[7:0]$13633
+ assign $0\core_core_core_cia$next[63:0]$13575 $1\core_core_core_cia$next[63:0]$13634
+ assign $0\core_core_core_cr_rd$next[7:0]$13576 $1\core_core_core_cr_rd$next[7:0]$13635
assign { } { }
- assign $0\core_core_core_cr_wr$next[7:0]$13786 $1\core_core_core_cr_wr$next[7:0]$13845
+ assign $0\core_core_core_cr_wr$next[7:0]$13578 $1\core_core_core_cr_wr$next[7:0]$13637
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_core_fn_unit$next[13:0]$13795 $1\core_core_core_fn_unit$next[13:0]$13854
- assign $0\core_core_core_input_carry$next[1:0]$13796 $1\core_core_core_input_carry$next[1:0]$13855
- assign $0\core_core_core_insn$next[31:0]$13797 $1\core_core_core_insn$next[31:0]$13856
- assign $0\core_core_core_insn_type$next[6:0]$13798 $1\core_core_core_insn_type$next[6:0]$13857
- assign $0\core_core_core_is_32bit$next[0:0]$13799 $1\core_core_core_is_32bit$next[0:0]$13858
- assign $0\core_core_core_msr$next[63:0]$13800 $1\core_core_core_msr$next[63:0]$13859
- assign $0\core_core_core_oe$next[0:0]$13801 $1\core_core_core_oe$next[0:0]$13860
+ assign $0\core_core_core_fn_unit$next[13:0]$13587 $1\core_core_core_fn_unit$next[13:0]$13646
+ assign $0\core_core_core_input_carry$next[1:0]$13588 $1\core_core_core_input_carry$next[1:0]$13647
+ assign $0\core_core_core_insn$next[31:0]$13589 $1\core_core_core_insn$next[31:0]$13648
+ assign $0\core_core_core_insn_type$next[6:0]$13590 $1\core_core_core_insn_type$next[6:0]$13649
+ assign $0\core_core_core_is_32bit$next[0:0]$13591 $1\core_core_core_is_32bit$next[0:0]$13650
+ assign $0\core_core_core_msr$next[63:0]$13592 $1\core_core_core_msr$next[63:0]$13651
+ assign $0\core_core_core_oe$next[0:0]$13593 $1\core_core_core_oe$next[0:0]$13652
assign { } { }
- assign $0\core_core_core_rc$next[0:0]$13803 $1\core_core_core_rc$next[0:0]$13862
+ assign $0\core_core_core_rc$next[0:0]$13595 $1\core_core_core_rc$next[0:0]$13654
assign { } { }
- assign $0\core_core_core_trapaddr$next[12:0]$13805 $1\core_core_core_trapaddr$next[12:0]$13864
- assign $0\core_core_core_traptype$next[7:0]$13806 $1\core_core_core_traptype$next[7:0]$13865
- assign $0\core_core_cr_in1$next[6:0]$13807 $1\core_core_cr_in1$next[6:0]$13866
+ assign $0\core_core_core_trapaddr$next[12:0]$13597 $1\core_core_core_trapaddr$next[12:0]$13656
+ assign $0\core_core_core_traptype$next[7:0]$13598 $1\core_core_core_traptype$next[7:0]$13657
+ assign $0\core_core_cr_in1$next[6:0]$13599 $1\core_core_cr_in1$next[6:0]$13658
assign { } { }
- assign $0\core_core_cr_in2$1$next[6:0]$13809 $1\core_core_cr_in2$1$next[6:0]$13868
- assign $0\core_core_cr_in2$next[6:0]$13810 $1\core_core_cr_in2$next[6:0]$13869
+ assign $0\core_core_cr_in2$1$next[6:0]$13601 $1\core_core_cr_in2$1$next[6:0]$13660
+ assign $0\core_core_cr_in2$next[6:0]$13602 $1\core_core_cr_in2$next[6:0]$13661
assign { } { }
assign { } { }
- assign $0\core_core_cr_out$next[6:0]$13813 $1\core_core_cr_out$next[6:0]$13872
+ assign $0\core_core_cr_out$next[6:0]$13605 $1\core_core_cr_out$next[6:0]$13664
assign { } { }
- assign $0\core_core_ea$next[6:0]$13815 $1\core_core_ea$next[6:0]$13874
- assign $0\core_core_fast1$next[2:0]$13816 $1\core_core_fast1$next[2:0]$13875
+ assign $0\core_core_ea$next[6:0]$13607 $1\core_core_ea$next[6:0]$13666
+ assign $0\core_core_fast1$next[2:0]$13608 $1\core_core_fast1$next[2:0]$13667
assign { } { }
- assign $0\core_core_fast2$next[2:0]$13818 $1\core_core_fast2$next[2:0]$13877
+ assign $0\core_core_fast2$next[2:0]$13610 $1\core_core_fast2$next[2:0]$13669
assign { } { }
- assign $0\core_core_fasto1$next[2:0]$13820 $1\core_core_fasto1$next[2:0]$13879
- assign $0\core_core_fasto2$next[2:0]$13821 $1\core_core_fasto2$next[2:0]$13880
- assign $0\core_core_lk$next[0:0]$13822 $1\core_core_lk$next[0:0]$13881
- assign $0\core_core_reg1$next[6:0]$13823 $1\core_core_reg1$next[6:0]$13882
+ assign $0\core_core_fasto1$next[2:0]$13612 $1\core_core_fasto1$next[2:0]$13671
+ assign $0\core_core_fasto2$next[2:0]$13613 $1\core_core_fasto2$next[2:0]$13672
+ assign $0\core_core_lk$next[0:0]$13614 $1\core_core_lk$next[0:0]$13673
+ assign $0\core_core_reg1$next[6:0]$13615 $1\core_core_reg1$next[6:0]$13674
assign { } { }
- assign $0\core_core_reg2$next[6:0]$13825 $1\core_core_reg2$next[6:0]$13884
+ assign $0\core_core_reg2$next[6:0]$13617 $1\core_core_reg2$next[6:0]$13676
assign { } { }
- assign $0\core_core_reg3$next[6:0]$13827 $1\core_core_reg3$next[6:0]$13886
+ assign $0\core_core_reg3$next[6:0]$13619 $1\core_core_reg3$next[6:0]$13678
assign { } { }
- assign $0\core_core_rego$next[6:0]$13829 $1\core_core_rego$next[6:0]$13888
- assign $0\core_core_spr1$next[9:0]$13830 $1\core_core_spr1$next[9:0]$13889
+ assign $0\core_core_rego$next[6:0]$13621 $1\core_core_rego$next[6:0]$13680
+ assign $0\core_core_spr1$next[9:0]$13622 $1\core_core_spr1$next[9:0]$13681
assign { } { }
- assign $0\core_core_spro$next[9:0]$13832 $1\core_core_spro$next[9:0]$13891
- assign $0\core_core_xer_in$next[2:0]$13833 $1\core_core_xer_in$next[2:0]$13892
+ assign $0\core_core_spro$next[9:0]$13624 $1\core_core_spro$next[9:0]$13683
+ assign $0\core_core_xer_in$next[2:0]$13625 $1\core_core_xer_in$next[2:0]$13684
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_xer_out$next[0:0]$13840 $1\core_xer_out$next[0:0]$13899
- assign $0\core_core_core_cr_rd_ok$next[0:0]$13785 $3\core_core_core_cr_rd_ok$next[0:0]$13959
- assign $0\core_core_core_exc_$signal$3$next[0:0]$13787 $3\core_core_core_exc_$signal$3$next[0:0]$13960
- assign $0\core_core_core_exc_$signal$4$next[0:0]$13788 $3\core_core_core_exc_$signal$4$next[0:0]$13961
- assign $0\core_core_core_exc_$signal$5$next[0:0]$13789 $3\core_core_core_exc_$signal$5$next[0:0]$13962
- assign $0\core_core_core_exc_$signal$6$next[0:0]$13790 $3\core_core_core_exc_$signal$6$next[0:0]$13963
- assign $0\core_core_core_exc_$signal$7$next[0:0]$13791 $3\core_core_core_exc_$signal$7$next[0:0]$13964
- assign $0\core_core_core_exc_$signal$8$next[0:0]$13792 $3\core_core_core_exc_$signal$8$next[0:0]$13965
- assign $0\core_core_core_exc_$signal$9$next[0:0]$13793 $3\core_core_core_exc_$signal$9$next[0:0]$13966
- assign $0\core_core_core_exc_$signal$next[0:0]$13794 $3\core_core_core_exc_$signal$next[0:0]$13967
- assign $0\core_core_core_oe_ok$next[0:0]$13802 $3\core_core_core_oe_ok$next[0:0]$13968
- assign $0\core_core_core_rc_ok$next[0:0]$13804 $3\core_core_core_rc_ok$next[0:0]$13969
- assign $0\core_core_cr_in1_ok$next[0:0]$13808 $3\core_core_cr_in1_ok$next[0:0]$13970
- assign $0\core_core_cr_in2_ok$2$next[0:0]$13811 $3\core_core_cr_in2_ok$2$next[0:0]$13971
- assign $0\core_core_cr_in2_ok$next[0:0]$13812 $3\core_core_cr_in2_ok$next[0:0]$13972
- assign $0\core_core_cr_wr_ok$next[0:0]$13814 $3\core_core_cr_wr_ok$next[0:0]$13973
- assign $0\core_core_fast1_ok$next[0:0]$13817 $3\core_core_fast1_ok$next[0:0]$13974
- assign $0\core_core_fast2_ok$next[0:0]$13819 $3\core_core_fast2_ok$next[0:0]$13975
- assign $0\core_core_reg1_ok$next[0:0]$13824 $3\core_core_reg1_ok$next[0:0]$13976
- assign $0\core_core_reg2_ok$next[0:0]$13826 $3\core_core_reg2_ok$next[0:0]$13977
- assign $0\core_core_reg3_ok$next[0:0]$13828 $3\core_core_reg3_ok$next[0:0]$13978
- assign $0\core_core_spr1_ok$next[0:0]$13831 $3\core_core_spr1_ok$next[0:0]$13979
- assign $0\core_cr_out_ok$next[0:0]$13834 $3\core_cr_out_ok$next[0:0]$13980
- assign $0\core_ea_ok$next[0:0]$13835 $3\core_ea_ok$next[0:0]$13981
- assign $0\core_fasto1_ok$next[0:0]$13836 $3\core_fasto1_ok$next[0:0]$13982
- assign $0\core_fasto2_ok$next[0:0]$13837 $3\core_fasto2_ok$next[0:0]$13983
- assign $0\core_rego_ok$next[0:0]$13838 $3\core_rego_ok$next[0:0]$13984
- assign $0\core_spro_ok$next[0:0]$13839 $3\core_spro_ok$next[0:0]$13985
- attribute \src "libresoc.v:200500.5-200500.29"
+ assign $0\core_xer_out$next[0:0]$13632 $1\core_xer_out$next[0:0]$13691
+ assign $0\core_core_core_cr_rd_ok$next[0:0]$13577 $3\core_core_core_cr_rd_ok$next[0:0]$13751
+ assign $0\core_core_core_exc_$signal$3$next[0:0]$13579 $3\core_core_core_exc_$signal$3$next[0:0]$13752
+ assign $0\core_core_core_exc_$signal$4$next[0:0]$13580 $3\core_core_core_exc_$signal$4$next[0:0]$13753
+ assign $0\core_core_core_exc_$signal$5$next[0:0]$13581 $3\core_core_core_exc_$signal$5$next[0:0]$13754
+ assign $0\core_core_core_exc_$signal$6$next[0:0]$13582 $3\core_core_core_exc_$signal$6$next[0:0]$13755
+ assign $0\core_core_core_exc_$signal$7$next[0:0]$13583 $3\core_core_core_exc_$signal$7$next[0:0]$13756
+ assign $0\core_core_core_exc_$signal$8$next[0:0]$13584 $3\core_core_core_exc_$signal$8$next[0:0]$13757
+ assign $0\core_core_core_exc_$signal$9$next[0:0]$13585 $3\core_core_core_exc_$signal$9$next[0:0]$13758
+ assign $0\core_core_core_exc_$signal$next[0:0]$13586 $3\core_core_core_exc_$signal$next[0:0]$13759
+ assign $0\core_core_core_oe_ok$next[0:0]$13594 $3\core_core_core_oe_ok$next[0:0]$13760
+ assign $0\core_core_core_rc_ok$next[0:0]$13596 $3\core_core_core_rc_ok$next[0:0]$13761
+ assign $0\core_core_cr_in1_ok$next[0:0]$13600 $3\core_core_cr_in1_ok$next[0:0]$13762
+ assign $0\core_core_cr_in2_ok$2$next[0:0]$13603 $3\core_core_cr_in2_ok$2$next[0:0]$13763
+ assign $0\core_core_cr_in2_ok$next[0:0]$13604 $3\core_core_cr_in2_ok$next[0:0]$13764
+ assign $0\core_core_cr_wr_ok$next[0:0]$13606 $3\core_core_cr_wr_ok$next[0:0]$13765
+ assign $0\core_core_fast1_ok$next[0:0]$13609 $3\core_core_fast1_ok$next[0:0]$13766
+ assign $0\core_core_fast2_ok$next[0:0]$13611 $3\core_core_fast2_ok$next[0:0]$13767
+ assign $0\core_core_reg1_ok$next[0:0]$13616 $3\core_core_reg1_ok$next[0:0]$13768
+ assign $0\core_core_reg2_ok$next[0:0]$13618 $3\core_core_reg2_ok$next[0:0]$13769
+ assign $0\core_core_reg3_ok$next[0:0]$13620 $3\core_core_reg3_ok$next[0:0]$13770
+ assign $0\core_core_spr1_ok$next[0:0]$13623 $3\core_core_spr1_ok$next[0:0]$13771
+ assign $0\core_cr_out_ok$next[0:0]$13626 $3\core_cr_out_ok$next[0:0]$13772
+ assign $0\core_ea_ok$next[0:0]$13627 $3\core_ea_ok$next[0:0]$13773
+ assign $0\core_fasto1_ok$next[0:0]$13628 $3\core_fasto1_ok$next[0:0]$13774
+ assign $0\core_fasto2_ok$next[0:0]$13629 $3\core_fasto2_ok$next[0:0]$13775
+ assign $0\core_rego_ok$next[0:0]$13630 $3\core_rego_ok$next[0:0]$13776
+ assign $0\core_spro_ok$next[0:0]$13631 $3\core_spro_ok$next[0:0]$13777
+ attribute \src "libresoc.v:200396.5-200396.29"
switch \initial
- attribute \src "libresoc.v:200500.9-200500.17"
+ attribute \src "libresoc.v:200396.9-200396.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518"
switch \issue_fsm_state
attribute \src "libresoc.v:0.0-0.0"
case 3'000
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'001
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$13841 $2\core_asmcode$next[7:0]$13900
- assign $1\core_core_core_cia$next[63:0]$13842 $2\core_core_core_cia$next[63:0]$13901
- assign $1\core_core_core_cr_rd$next[7:0]$13843 $2\core_core_core_cr_rd$next[7:0]$13902
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 $2\core_core_core_cr_rd_ok$next[0:0]$13903
- assign $1\core_core_core_cr_wr$next[7:0]$13845 $2\core_core_core_cr_wr$next[7:0]$13904
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 $2\core_core_core_exc_$signal$3$next[0:0]$13905
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 $2\core_core_core_exc_$signal$4$next[0:0]$13906
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 $2\core_core_core_exc_$signal$5$next[0:0]$13907
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 $2\core_core_core_exc_$signal$6$next[0:0]$13908
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 $2\core_core_core_exc_$signal$7$next[0:0]$13909
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 $2\core_core_core_exc_$signal$8$next[0:0]$13910
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 $2\core_core_core_exc_$signal$9$next[0:0]$13911
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 $2\core_core_core_exc_$signal$next[0:0]$13912
- assign $1\core_core_core_fn_unit$next[13:0]$13854 $2\core_core_core_fn_unit$next[13:0]$13913
- assign $1\core_core_core_input_carry$next[1:0]$13855 $2\core_core_core_input_carry$next[1:0]$13914
- assign $1\core_core_core_insn$next[31:0]$13856 $2\core_core_core_insn$next[31:0]$13915
- assign $1\core_core_core_insn_type$next[6:0]$13857 $2\core_core_core_insn_type$next[6:0]$13916
- assign $1\core_core_core_is_32bit$next[0:0]$13858 $2\core_core_core_is_32bit$next[0:0]$13917
- assign $1\core_core_core_msr$next[63:0]$13859 $2\core_core_core_msr$next[63:0]$13918
- assign $1\core_core_core_oe$next[0:0]$13860 $2\core_core_core_oe$next[0:0]$13919
- assign $1\core_core_core_oe_ok$next[0:0]$13861 $2\core_core_core_oe_ok$next[0:0]$13920
- assign $1\core_core_core_rc$next[0:0]$13862 $2\core_core_core_rc$next[0:0]$13921
- assign $1\core_core_core_rc_ok$next[0:0]$13863 $2\core_core_core_rc_ok$next[0:0]$13922
- assign $1\core_core_core_trapaddr$next[12:0]$13864 $2\core_core_core_trapaddr$next[12:0]$13923
- assign $1\core_core_core_traptype$next[7:0]$13865 $2\core_core_core_traptype$next[7:0]$13924
- assign $1\core_core_cr_in1$next[6:0]$13866 $2\core_core_cr_in1$next[6:0]$13925
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 $2\core_core_cr_in1_ok$next[0:0]$13926
- assign $1\core_core_cr_in2$1$next[6:0]$13868 $2\core_core_cr_in2$1$next[6:0]$13927
- assign $1\core_core_cr_in2$next[6:0]$13869 $2\core_core_cr_in2$next[6:0]$13928
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 $2\core_core_cr_in2_ok$2$next[0:0]$13929
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 $2\core_core_cr_in2_ok$next[0:0]$13930
- assign $1\core_core_cr_out$next[6:0]$13872 $2\core_core_cr_out$next[6:0]$13931
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 $2\core_core_cr_wr_ok$next[0:0]$13932
- assign $1\core_core_ea$next[6:0]$13874 $2\core_core_ea$next[6:0]$13933
- assign $1\core_core_fast1$next[2:0]$13875 $2\core_core_fast1$next[2:0]$13934
- assign $1\core_core_fast1_ok$next[0:0]$13876 $2\core_core_fast1_ok$next[0:0]$13935
- assign $1\core_core_fast2$next[2:0]$13877 $2\core_core_fast2$next[2:0]$13936
- assign $1\core_core_fast2_ok$next[0:0]$13878 $2\core_core_fast2_ok$next[0:0]$13937
- assign $1\core_core_fasto1$next[2:0]$13879 $2\core_core_fasto1$next[2:0]$13938
- assign $1\core_core_fasto2$next[2:0]$13880 $2\core_core_fasto2$next[2:0]$13939
- assign $1\core_core_lk$next[0:0]$13881 $2\core_core_lk$next[0:0]$13940
- assign $1\core_core_reg1$next[6:0]$13882 $2\core_core_reg1$next[6:0]$13941
- assign $1\core_core_reg1_ok$next[0:0]$13883 $2\core_core_reg1_ok$next[0:0]$13942
- assign $1\core_core_reg2$next[6:0]$13884 $2\core_core_reg2$next[6:0]$13943
- assign $1\core_core_reg2_ok$next[0:0]$13885 $2\core_core_reg2_ok$next[0:0]$13944
- assign $1\core_core_reg3$next[6:0]$13886 $2\core_core_reg3$next[6:0]$13945
- assign $1\core_core_reg3_ok$next[0:0]$13887 $2\core_core_reg3_ok$next[0:0]$13946
- assign $1\core_core_rego$next[6:0]$13888 $2\core_core_rego$next[6:0]$13947
- assign $1\core_core_spr1$next[9:0]$13889 $2\core_core_spr1$next[9:0]$13948
- assign $1\core_core_spr1_ok$next[0:0]$13890 $2\core_core_spr1_ok$next[0:0]$13949
- assign $1\core_core_spro$next[9:0]$13891 $2\core_core_spro$next[9:0]$13950
- assign $1\core_core_xer_in$next[2:0]$13892 $2\core_core_xer_in$next[2:0]$13951
- assign $1\core_cr_out_ok$next[0:0]$13893 $2\core_cr_out_ok$next[0:0]$13952
- assign $1\core_ea_ok$next[0:0]$13894 $2\core_ea_ok$next[0:0]$13953
- assign $1\core_fasto1_ok$next[0:0]$13895 $2\core_fasto1_ok$next[0:0]$13954
- assign $1\core_fasto2_ok$next[0:0]$13896 $2\core_fasto2_ok$next[0:0]$13955
- assign $1\core_rego_ok$next[0:0]$13897 $2\core_rego_ok$next[0:0]$13956
- assign $1\core_spro_ok$next[0:0]$13898 $2\core_spro_ok$next[0:0]$13957
- assign $1\core_xer_out$next[0:0]$13899 $2\core_xer_out$next[0:0]$13958
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:542"
+ assign $1\core_asmcode$next[7:0]$13633 $2\core_asmcode$next[7:0]$13692
+ assign $1\core_core_core_cia$next[63:0]$13634 $2\core_core_core_cia$next[63:0]$13693
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 $2\core_core_core_cr_rd$next[7:0]$13694
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 $2\core_core_core_cr_rd_ok$next[0:0]$13695
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 $2\core_core_core_cr_wr$next[7:0]$13696
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 $2\core_core_core_exc_$signal$3$next[0:0]$13697
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 $2\core_core_core_exc_$signal$4$next[0:0]$13698
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 $2\core_core_core_exc_$signal$5$next[0:0]$13699
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 $2\core_core_core_exc_$signal$6$next[0:0]$13700
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 $2\core_core_core_exc_$signal$7$next[0:0]$13701
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 $2\core_core_core_exc_$signal$8$next[0:0]$13702
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 $2\core_core_core_exc_$signal$9$next[0:0]$13703
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 $2\core_core_core_exc_$signal$next[0:0]$13704
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 $2\core_core_core_fn_unit$next[13:0]$13705
+ assign $1\core_core_core_input_carry$next[1:0]$13647 $2\core_core_core_input_carry$next[1:0]$13706
+ assign $1\core_core_core_insn$next[31:0]$13648 $2\core_core_core_insn$next[31:0]$13707
+ assign $1\core_core_core_insn_type$next[6:0]$13649 $2\core_core_core_insn_type$next[6:0]$13708
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 $2\core_core_core_is_32bit$next[0:0]$13709
+ assign $1\core_core_core_msr$next[63:0]$13651 $2\core_core_core_msr$next[63:0]$13710
+ assign $1\core_core_core_oe$next[0:0]$13652 $2\core_core_core_oe$next[0:0]$13711
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 $2\core_core_core_oe_ok$next[0:0]$13712
+ assign $1\core_core_core_rc$next[0:0]$13654 $2\core_core_core_rc$next[0:0]$13713
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 $2\core_core_core_rc_ok$next[0:0]$13714
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 $2\core_core_core_trapaddr$next[12:0]$13715
+ assign $1\core_core_core_traptype$next[7:0]$13657 $2\core_core_core_traptype$next[7:0]$13716
+ assign $1\core_core_cr_in1$next[6:0]$13658 $2\core_core_cr_in1$next[6:0]$13717
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 $2\core_core_cr_in1_ok$next[0:0]$13718
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 $2\core_core_cr_in2$1$next[6:0]$13719
+ assign $1\core_core_cr_in2$next[6:0]$13661 $2\core_core_cr_in2$next[6:0]$13720
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 $2\core_core_cr_in2_ok$2$next[0:0]$13721
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 $2\core_core_cr_in2_ok$next[0:0]$13722
+ assign $1\core_core_cr_out$next[6:0]$13664 $2\core_core_cr_out$next[6:0]$13723
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 $2\core_core_cr_wr_ok$next[0:0]$13724
+ assign $1\core_core_ea$next[6:0]$13666 $2\core_core_ea$next[6:0]$13725
+ assign $1\core_core_fast1$next[2:0]$13667 $2\core_core_fast1$next[2:0]$13726
+ assign $1\core_core_fast1_ok$next[0:0]$13668 $2\core_core_fast1_ok$next[0:0]$13727
+ assign $1\core_core_fast2$next[2:0]$13669 $2\core_core_fast2$next[2:0]$13728
+ assign $1\core_core_fast2_ok$next[0:0]$13670 $2\core_core_fast2_ok$next[0:0]$13729
+ assign $1\core_core_fasto1$next[2:0]$13671 $2\core_core_fasto1$next[2:0]$13730
+ assign $1\core_core_fasto2$next[2:0]$13672 $2\core_core_fasto2$next[2:0]$13731
+ assign $1\core_core_lk$next[0:0]$13673 $2\core_core_lk$next[0:0]$13732
+ assign $1\core_core_reg1$next[6:0]$13674 $2\core_core_reg1$next[6:0]$13733
+ assign $1\core_core_reg1_ok$next[0:0]$13675 $2\core_core_reg1_ok$next[0:0]$13734
+ assign $1\core_core_reg2$next[6:0]$13676 $2\core_core_reg2$next[6:0]$13735
+ assign $1\core_core_reg2_ok$next[0:0]$13677 $2\core_core_reg2_ok$next[0:0]$13736
+ assign $1\core_core_reg3$next[6:0]$13678 $2\core_core_reg3$next[6:0]$13737
+ assign $1\core_core_reg3_ok$next[0:0]$13679 $2\core_core_reg3_ok$next[0:0]$13738
+ assign $1\core_core_rego$next[6:0]$13680 $2\core_core_rego$next[6:0]$13739
+ assign $1\core_core_spr1$next[9:0]$13681 $2\core_core_spr1$next[9:0]$13740
+ assign $1\core_core_spr1_ok$next[0:0]$13682 $2\core_core_spr1_ok$next[0:0]$13741
+ assign $1\core_core_spro$next[9:0]$13683 $2\core_core_spro$next[9:0]$13742
+ assign $1\core_core_xer_in$next[2:0]$13684 $2\core_core_xer_in$next[2:0]$13743
+ assign $1\core_cr_out_ok$next[0:0]$13685 $2\core_cr_out_ok$next[0:0]$13744
+ assign $1\core_ea_ok$next[0:0]$13686 $2\core_ea_ok$next[0:0]$13745
+ assign $1\core_fasto1_ok$next[0:0]$13687 $2\core_fasto1_ok$next[0:0]$13746
+ assign $1\core_fasto2_ok$next[0:0]$13688 $2\core_fasto2_ok$next[0:0]$13747
+ assign $1\core_rego_ok$next[0:0]$13689 $2\core_rego_ok$next[0:0]$13748
+ assign $1\core_spro_ok$next[0:0]$13690 $2\core_spro_ok$next[0:0]$13749
+ assign $1\core_xer_out$next[0:0]$13691 $2\core_xer_out$next[0:0]$13750
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547"
switch \fetch_insn_valid_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_core_is_32bit$next[0:0]$13917 $2\core_core_cr_wr_ok$next[0:0]$13932 $2\core_core_core_cr_wr$next[7:0]$13904 $2\core_core_core_cr_rd_ok$next[0:0]$13903 $2\core_core_core_cr_rd$next[7:0]$13902 $2\core_core_core_trapaddr$next[12:0]$13923 $2\core_core_core_exc_$signal$9$next[0:0]$13911 $2\core_core_core_exc_$signal$8$next[0:0]$13910 $2\core_core_core_exc_$signal$7$next[0:0]$13909 $2\core_core_core_exc_$signal$6$next[0:0]$13908 $2\core_core_core_exc_$signal$5$next[0:0]$13907 $2\core_core_core_exc_$signal$4$next[0:0]$13906 $2\core_core_core_exc_$signal$3$next[0:0]$13905 $2\core_core_core_exc_$signal$next[0:0]$13912 $2\core_core_core_traptype$next[7:0]$13924 $2\core_core_core_input_carry$next[1:0]$13914 $2\core_core_core_oe_ok$next[0:0]$13920 $2\core_core_core_oe$next[0:0]$13919 $2\core_core_core_rc_ok$next[0:0]$13922 $2\core_core_core_rc$next[0:0]$13921 $2\core_core_lk$next[0:0]$13940 $2\core_core_core_fn_unit$next[13:0]$13913 $2\core_core_core_insn_type$next[6:0]$13916 $2\core_core_core_insn$next[31:0]$13915 $2\core_core_core_cia$next[63:0]$13901 $2\core_core_core_msr$next[63:0]$13918 $2\core_cr_out_ok$next[0:0]$13952 $2\core_core_cr_out$next[6:0]$13931 $2\core_core_cr_in2_ok$2$next[0:0]$13929 $2\core_core_cr_in2$1$next[6:0]$13927 $2\core_core_cr_in2_ok$next[0:0]$13930 $2\core_core_cr_in2$next[6:0]$13928 $2\core_core_cr_in1_ok$next[0:0]$13926 $2\core_core_cr_in1$next[6:0]$13925 $2\core_fasto2_ok$next[0:0]$13955 $2\core_core_fasto2$next[2:0]$13939 $2\core_fasto1_ok$next[0:0]$13954 $2\core_core_fasto1$next[2:0]$13938 $2\core_core_fast2_ok$next[0:0]$13937 $2\core_core_fast2$next[2:0]$13936 $2\core_core_fast1_ok$next[0:0]$13935 $2\core_core_fast1$next[2:0]$13934 $2\core_xer_out$next[0:0]$13958 $2\core_core_xer_in$next[2:0]$13951 $2\core_core_spr1_ok$next[0:0]$13949 $2\core_core_spr1$next[9:0]$13948 $2\core_spro_ok$next[0:0]$13957 $2\core_core_spro$next[9:0]$13950 $2\core_core_reg3_ok$next[0:0]$13946 $2\core_core_reg3$next[6:0]$13945 $2\core_core_reg2_ok$next[0:0]$13944 $2\core_core_reg2$next[6:0]$13943 $2\core_core_reg1_ok$next[0:0]$13942 $2\core_core_reg1$next[6:0]$13941 $2\core_ea_ok$next[0:0]$13953 $2\core_core_ea$next[6:0]$13933 $2\core_rego_ok$next[0:0]$13956 $2\core_core_rego$next[6:0]$13947 $2\core_asmcode$next[7:0]$13900 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $2\core_core_core_is_32bit$next[0:0]$13709 $2\core_core_cr_wr_ok$next[0:0]$13724 $2\core_core_core_cr_wr$next[7:0]$13696 $2\core_core_core_cr_rd_ok$next[0:0]$13695 $2\core_core_core_cr_rd$next[7:0]$13694 $2\core_core_core_trapaddr$next[12:0]$13715 $2\core_core_core_exc_$signal$9$next[0:0]$13703 $2\core_core_core_exc_$signal$8$next[0:0]$13702 $2\core_core_core_exc_$signal$7$next[0:0]$13701 $2\core_core_core_exc_$signal$6$next[0:0]$13700 $2\core_core_core_exc_$signal$5$next[0:0]$13699 $2\core_core_core_exc_$signal$4$next[0:0]$13698 $2\core_core_core_exc_$signal$3$next[0:0]$13697 $2\core_core_core_exc_$signal$next[0:0]$13704 $2\core_core_core_traptype$next[7:0]$13716 $2\core_core_core_input_carry$next[1:0]$13706 $2\core_core_core_oe_ok$next[0:0]$13712 $2\core_core_core_oe$next[0:0]$13711 $2\core_core_core_rc_ok$next[0:0]$13714 $2\core_core_core_rc$next[0:0]$13713 $2\core_core_lk$next[0:0]$13732 $2\core_core_core_fn_unit$next[13:0]$13705 $2\core_core_core_insn_type$next[6:0]$13708 $2\core_core_core_insn$next[31:0]$13707 $2\core_core_core_cia$next[63:0]$13693 $2\core_core_core_msr$next[63:0]$13710 $2\core_cr_out_ok$next[0:0]$13744 $2\core_core_cr_out$next[6:0]$13723 $2\core_core_cr_in2_ok$2$next[0:0]$13721 $2\core_core_cr_in2$1$next[6:0]$13719 $2\core_core_cr_in2_ok$next[0:0]$13722 $2\core_core_cr_in2$next[6:0]$13720 $2\core_core_cr_in1_ok$next[0:0]$13718 $2\core_core_cr_in1$next[6:0]$13717 $2\core_fasto2_ok$next[0:0]$13747 $2\core_core_fasto2$next[2:0]$13731 $2\core_fasto1_ok$next[0:0]$13746 $2\core_core_fasto1$next[2:0]$13730 $2\core_core_fast2_ok$next[0:0]$13729 $2\core_core_fast2$next[2:0]$13728 $2\core_core_fast1_ok$next[0:0]$13727 $2\core_core_fast1$next[2:0]$13726 $2\core_xer_out$next[0:0]$13750 $2\core_core_xer_in$next[2:0]$13743 $2\core_core_spr1_ok$next[0:0]$13741 $2\core_core_spr1$next[9:0]$13740 $2\core_spro_ok$next[0:0]$13749 $2\core_core_spro$next[9:0]$13742 $2\core_core_reg3_ok$next[0:0]$13738 $2\core_core_reg3$next[6:0]$13737 $2\core_core_reg2_ok$next[0:0]$13736 $2\core_core_reg2$next[6:0]$13735 $2\core_core_reg1_ok$next[0:0]$13734 $2\core_core_reg1$next[6:0]$13733 $2\core_ea_ok$next[0:0]$13745 $2\core_core_ea$next[6:0]$13725 $2\core_rego_ok$next[0:0]$13748 $2\core_core_rego$next[6:0]$13739 $2\core_asmcode$next[7:0]$13692 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $2\core_asmcode$next[7:0]$13900 \core_asmcode
- assign $2\core_core_core_cia$next[63:0]$13901 \core_core_core_cia
- assign $2\core_core_core_cr_rd$next[7:0]$13902 \core_core_core_cr_rd
- assign $2\core_core_core_cr_rd_ok$next[0:0]$13903 \core_core_core_cr_rd_ok
- assign $2\core_core_core_cr_wr$next[7:0]$13904 \core_core_core_cr_wr
- assign $2\core_core_core_exc_$signal$3$next[0:0]$13905 \core_core_core_exc_$signal$3
- assign $2\core_core_core_exc_$signal$4$next[0:0]$13906 \core_core_core_exc_$signal$4
- assign $2\core_core_core_exc_$signal$5$next[0:0]$13907 \core_core_core_exc_$signal$5
- assign $2\core_core_core_exc_$signal$6$next[0:0]$13908 \core_core_core_exc_$signal$6
- assign $2\core_core_core_exc_$signal$7$next[0:0]$13909 \core_core_core_exc_$signal$7
- assign $2\core_core_core_exc_$signal$8$next[0:0]$13910 \core_core_core_exc_$signal$8
- assign $2\core_core_core_exc_$signal$9$next[0:0]$13911 \core_core_core_exc_$signal$9
- assign $2\core_core_core_exc_$signal$next[0:0]$13912 \core_core_core_exc_$signal
- assign $2\core_core_core_fn_unit$next[13:0]$13913 \core_core_core_fn_unit
- assign $2\core_core_core_input_carry$next[1:0]$13914 \core_core_core_input_carry
- assign $2\core_core_core_insn$next[31:0]$13915 \core_core_core_insn
- assign $2\core_core_core_insn_type$next[6:0]$13916 \core_core_core_insn_type
- assign $2\core_core_core_is_32bit$next[0:0]$13917 \core_core_core_is_32bit
- assign $2\core_core_core_msr$next[63:0]$13918 \core_core_core_msr
- assign $2\core_core_core_oe$next[0:0]$13919 \core_core_core_oe
- assign $2\core_core_core_oe_ok$next[0:0]$13920 \core_core_core_oe_ok
- assign $2\core_core_core_rc$next[0:0]$13921 \core_core_core_rc
- assign $2\core_core_core_rc_ok$next[0:0]$13922 \core_core_core_rc_ok
- assign $2\core_core_core_trapaddr$next[12:0]$13923 \core_core_core_trapaddr
- assign $2\core_core_core_traptype$next[7:0]$13924 \core_core_core_traptype
- assign $2\core_core_cr_in1$next[6:0]$13925 \core_core_cr_in1
- assign $2\core_core_cr_in1_ok$next[0:0]$13926 \core_core_cr_in1_ok
- assign $2\core_core_cr_in2$1$next[6:0]$13927 \core_core_cr_in2$1
- assign $2\core_core_cr_in2$next[6:0]$13928 \core_core_cr_in2
- assign $2\core_core_cr_in2_ok$2$next[0:0]$13929 \core_core_cr_in2_ok$2
- assign $2\core_core_cr_in2_ok$next[0:0]$13930 \core_core_cr_in2_ok
- assign $2\core_core_cr_out$next[6:0]$13931 \core_core_cr_out
- assign $2\core_core_cr_wr_ok$next[0:0]$13932 \core_core_cr_wr_ok
- assign $2\core_core_ea$next[6:0]$13933 \core_core_ea
- assign $2\core_core_fast1$next[2:0]$13934 \core_core_fast1
- assign $2\core_core_fast1_ok$next[0:0]$13935 \core_core_fast1_ok
- assign $2\core_core_fast2$next[2:0]$13936 \core_core_fast2
- assign $2\core_core_fast2_ok$next[0:0]$13937 \core_core_fast2_ok
- assign $2\core_core_fasto1$next[2:0]$13938 \core_core_fasto1
- assign $2\core_core_fasto2$next[2:0]$13939 \core_core_fasto2
- assign $2\core_core_lk$next[0:0]$13940 \core_core_lk
- assign $2\core_core_reg1$next[6:0]$13941 \core_core_reg1
- assign $2\core_core_reg1_ok$next[0:0]$13942 \core_core_reg1_ok
- assign $2\core_core_reg2$next[6:0]$13943 \core_core_reg2
- assign $2\core_core_reg2_ok$next[0:0]$13944 \core_core_reg2_ok
- assign $2\core_core_reg3$next[6:0]$13945 \core_core_reg3
- assign $2\core_core_reg3_ok$next[0:0]$13946 \core_core_reg3_ok
- assign $2\core_core_rego$next[6:0]$13947 \core_core_rego
- assign $2\core_core_spr1$next[9:0]$13948 \core_core_spr1
- assign $2\core_core_spr1_ok$next[0:0]$13949 \core_core_spr1_ok
- assign $2\core_core_spro$next[9:0]$13950 \core_core_spro
- assign $2\core_core_xer_in$next[2:0]$13951 \core_core_xer_in
- assign $2\core_cr_out_ok$next[0:0]$13952 \core_cr_out_ok
- assign $2\core_ea_ok$next[0:0]$13953 \core_ea_ok
- assign $2\core_fasto1_ok$next[0:0]$13954 \core_fasto1_ok
- assign $2\core_fasto2_ok$next[0:0]$13955 \core_fasto2_ok
- assign $2\core_rego_ok$next[0:0]$13956 \core_rego_ok
- assign $2\core_spro_ok$next[0:0]$13957 \core_spro_ok
- assign $2\core_xer_out$next[0:0]$13958 \core_xer_out
+ assign $2\core_asmcode$next[7:0]$13692 \core_asmcode
+ assign $2\core_core_core_cia$next[63:0]$13693 \core_core_core_cia
+ assign $2\core_core_core_cr_rd$next[7:0]$13694 \core_core_core_cr_rd
+ assign $2\core_core_core_cr_rd_ok$next[0:0]$13695 \core_core_core_cr_rd_ok
+ assign $2\core_core_core_cr_wr$next[7:0]$13696 \core_core_core_cr_wr
+ assign $2\core_core_core_exc_$signal$3$next[0:0]$13697 \core_core_core_exc_$signal$3
+ assign $2\core_core_core_exc_$signal$4$next[0:0]$13698 \core_core_core_exc_$signal$4
+ assign $2\core_core_core_exc_$signal$5$next[0:0]$13699 \core_core_core_exc_$signal$5
+ assign $2\core_core_core_exc_$signal$6$next[0:0]$13700 \core_core_core_exc_$signal$6
+ assign $2\core_core_core_exc_$signal$7$next[0:0]$13701 \core_core_core_exc_$signal$7
+ assign $2\core_core_core_exc_$signal$8$next[0:0]$13702 \core_core_core_exc_$signal$8
+ assign $2\core_core_core_exc_$signal$9$next[0:0]$13703 \core_core_core_exc_$signal$9
+ assign $2\core_core_core_exc_$signal$next[0:0]$13704 \core_core_core_exc_$signal
+ assign $2\core_core_core_fn_unit$next[13:0]$13705 \core_core_core_fn_unit
+ assign $2\core_core_core_input_carry$next[1:0]$13706 \core_core_core_input_carry
+ assign $2\core_core_core_insn$next[31:0]$13707 \core_core_core_insn
+ assign $2\core_core_core_insn_type$next[6:0]$13708 \core_core_core_insn_type
+ assign $2\core_core_core_is_32bit$next[0:0]$13709 \core_core_core_is_32bit
+ assign $2\core_core_core_msr$next[63:0]$13710 \core_core_core_msr
+ assign $2\core_core_core_oe$next[0:0]$13711 \core_core_core_oe
+ assign $2\core_core_core_oe_ok$next[0:0]$13712 \core_core_core_oe_ok
+ assign $2\core_core_core_rc$next[0:0]$13713 \core_core_core_rc
+ assign $2\core_core_core_rc_ok$next[0:0]$13714 \core_core_core_rc_ok
+ assign $2\core_core_core_trapaddr$next[12:0]$13715 \core_core_core_trapaddr
+ assign $2\core_core_core_traptype$next[7:0]$13716 \core_core_core_traptype
+ assign $2\core_core_cr_in1$next[6:0]$13717 \core_core_cr_in1
+ assign $2\core_core_cr_in1_ok$next[0:0]$13718 \core_core_cr_in1_ok
+ assign $2\core_core_cr_in2$1$next[6:0]$13719 \core_core_cr_in2$1
+ assign $2\core_core_cr_in2$next[6:0]$13720 \core_core_cr_in2
+ assign $2\core_core_cr_in2_ok$2$next[0:0]$13721 \core_core_cr_in2_ok$2
+ assign $2\core_core_cr_in2_ok$next[0:0]$13722 \core_core_cr_in2_ok
+ assign $2\core_core_cr_out$next[6:0]$13723 \core_core_cr_out
+ assign $2\core_core_cr_wr_ok$next[0:0]$13724 \core_core_cr_wr_ok
+ assign $2\core_core_ea$next[6:0]$13725 \core_core_ea
+ assign $2\core_core_fast1$next[2:0]$13726 \core_core_fast1
+ assign $2\core_core_fast1_ok$next[0:0]$13727 \core_core_fast1_ok
+ assign $2\core_core_fast2$next[2:0]$13728 \core_core_fast2
+ assign $2\core_core_fast2_ok$next[0:0]$13729 \core_core_fast2_ok
+ assign $2\core_core_fasto1$next[2:0]$13730 \core_core_fasto1
+ assign $2\core_core_fasto2$next[2:0]$13731 \core_core_fasto2
+ assign $2\core_core_lk$next[0:0]$13732 \core_core_lk
+ assign $2\core_core_reg1$next[6:0]$13733 \core_core_reg1
+ assign $2\core_core_reg1_ok$next[0:0]$13734 \core_core_reg1_ok
+ assign $2\core_core_reg2$next[6:0]$13735 \core_core_reg2
+ assign $2\core_core_reg2_ok$next[0:0]$13736 \core_core_reg2_ok
+ assign $2\core_core_reg3$next[6:0]$13737 \core_core_reg3
+ assign $2\core_core_reg3_ok$next[0:0]$13738 \core_core_reg3_ok
+ assign $2\core_core_rego$next[6:0]$13739 \core_core_rego
+ assign $2\core_core_spr1$next[9:0]$13740 \core_core_spr1
+ assign $2\core_core_spr1_ok$next[0:0]$13741 \core_core_spr1_ok
+ assign $2\core_core_spro$next[9:0]$13742 \core_core_spro
+ assign $2\core_core_xer_in$next[2:0]$13743 \core_core_xer_in
+ assign $2\core_cr_out_ok$next[0:0]$13744 \core_cr_out_ok
+ assign $2\core_ea_ok$next[0:0]$13745 \core_ea_ok
+ assign $2\core_fasto1_ok$next[0:0]$13746 \core_fasto1_ok
+ assign $2\core_fasto2_ok$next[0:0]$13747 \core_fasto2_ok
+ assign $2\core_rego_ok$next[0:0]$13748 \core_rego_ok
+ assign $2\core_spro_ok$next[0:0]$13749 \core_spro_ok
+ assign $2\core_xer_out$next[0:0]$13750 \core_xer_out
end
attribute \src "libresoc.v:0.0-0.0"
case 3'011
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'100
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'010
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'101
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case 3'110
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_core_is_32bit$next[0:0]$13858 $1\core_core_cr_wr_ok$next[0:0]$13873 $1\core_core_core_cr_wr$next[7:0]$13845 $1\core_core_core_cr_rd_ok$next[0:0]$13844 $1\core_core_core_cr_rd$next[7:0]$13843 $1\core_core_core_trapaddr$next[12:0]$13864 $1\core_core_core_exc_$signal$9$next[0:0]$13852 $1\core_core_core_exc_$signal$8$next[0:0]$13851 $1\core_core_core_exc_$signal$7$next[0:0]$13850 $1\core_core_core_exc_$signal$6$next[0:0]$13849 $1\core_core_core_exc_$signal$5$next[0:0]$13848 $1\core_core_core_exc_$signal$4$next[0:0]$13847 $1\core_core_core_exc_$signal$3$next[0:0]$13846 $1\core_core_core_exc_$signal$next[0:0]$13853 $1\core_core_core_traptype$next[7:0]$13865 $1\core_core_core_input_carry$next[1:0]$13855 $1\core_core_core_oe_ok$next[0:0]$13861 $1\core_core_core_oe$next[0:0]$13860 $1\core_core_core_rc_ok$next[0:0]$13863 $1\core_core_core_rc$next[0:0]$13862 $1\core_core_lk$next[0:0]$13881 $1\core_core_core_fn_unit$next[13:0]$13854 $1\core_core_core_insn_type$next[6:0]$13857 $1\core_core_core_insn$next[31:0]$13856 $1\core_core_core_cia$next[63:0]$13842 $1\core_core_core_msr$next[63:0]$13859 $1\core_cr_out_ok$next[0:0]$13893 $1\core_core_cr_out$next[6:0]$13872 $1\core_core_cr_in2_ok$2$next[0:0]$13870 $1\core_core_cr_in2$1$next[6:0]$13868 $1\core_core_cr_in2_ok$next[0:0]$13871 $1\core_core_cr_in2$next[6:0]$13869 $1\core_core_cr_in1_ok$next[0:0]$13867 $1\core_core_cr_in1$next[6:0]$13866 $1\core_fasto2_ok$next[0:0]$13896 $1\core_core_fasto2$next[2:0]$13880 $1\core_fasto1_ok$next[0:0]$13895 $1\core_core_fasto1$next[2:0]$13879 $1\core_core_fast2_ok$next[0:0]$13878 $1\core_core_fast2$next[2:0]$13877 $1\core_core_fast1_ok$next[0:0]$13876 $1\core_core_fast1$next[2:0]$13875 $1\core_xer_out$next[0:0]$13899 $1\core_core_xer_in$next[2:0]$13892 $1\core_core_spr1_ok$next[0:0]$13890 $1\core_core_spr1$next[9:0]$13889 $1\core_spro_ok$next[0:0]$13898 $1\core_core_spro$next[9:0]$13891 $1\core_core_reg3_ok$next[0:0]$13887 $1\core_core_reg3$next[6:0]$13886 $1\core_core_reg2_ok$next[0:0]$13885 $1\core_core_reg2$next[6:0]$13884 $1\core_core_reg1_ok$next[0:0]$13883 $1\core_core_reg1$next[6:0]$13882 $1\core_ea_ok$next[0:0]$13894 $1\core_core_ea$next[6:0]$13874 $1\core_rego_ok$next[0:0]$13897 $1\core_core_rego$next[6:0]$13888 $1\core_asmcode$next[7:0]$13841 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $1\core_core_core_is_32bit$next[0:0]$13650 $1\core_core_cr_wr_ok$next[0:0]$13665 $1\core_core_core_cr_wr$next[7:0]$13637 $1\core_core_core_cr_rd_ok$next[0:0]$13636 $1\core_core_core_cr_rd$next[7:0]$13635 $1\core_core_core_trapaddr$next[12:0]$13656 $1\core_core_core_exc_$signal$9$next[0:0]$13644 $1\core_core_core_exc_$signal$8$next[0:0]$13643 $1\core_core_core_exc_$signal$7$next[0:0]$13642 $1\core_core_core_exc_$signal$6$next[0:0]$13641 $1\core_core_core_exc_$signal$5$next[0:0]$13640 $1\core_core_core_exc_$signal$4$next[0:0]$13639 $1\core_core_core_exc_$signal$3$next[0:0]$13638 $1\core_core_core_exc_$signal$next[0:0]$13645 $1\core_core_core_traptype$next[7:0]$13657 $1\core_core_core_input_carry$next[1:0]$13647 $1\core_core_core_oe_ok$next[0:0]$13653 $1\core_core_core_oe$next[0:0]$13652 $1\core_core_core_rc_ok$next[0:0]$13655 $1\core_core_core_rc$next[0:0]$13654 $1\core_core_lk$next[0:0]$13673 $1\core_core_core_fn_unit$next[13:0]$13646 $1\core_core_core_insn_type$next[6:0]$13649 $1\core_core_core_insn$next[31:0]$13648 $1\core_core_core_cia$next[63:0]$13634 $1\core_core_core_msr$next[63:0]$13651 $1\core_cr_out_ok$next[0:0]$13685 $1\core_core_cr_out$next[6:0]$13664 $1\core_core_cr_in2_ok$2$next[0:0]$13662 $1\core_core_cr_in2$1$next[6:0]$13660 $1\core_core_cr_in2_ok$next[0:0]$13663 $1\core_core_cr_in2$next[6:0]$13661 $1\core_core_cr_in1_ok$next[0:0]$13659 $1\core_core_cr_in1$next[6:0]$13658 $1\core_fasto2_ok$next[0:0]$13688 $1\core_core_fasto2$next[2:0]$13672 $1\core_fasto1_ok$next[0:0]$13687 $1\core_core_fasto1$next[2:0]$13671 $1\core_core_fast2_ok$next[0:0]$13670 $1\core_core_fast2$next[2:0]$13669 $1\core_core_fast1_ok$next[0:0]$13668 $1\core_core_fast1$next[2:0]$13667 $1\core_xer_out$next[0:0]$13691 $1\core_core_xer_in$next[2:0]$13684 $1\core_core_spr1_ok$next[0:0]$13682 $1\core_core_spr1$next[9:0]$13681 $1\core_spro_ok$next[0:0]$13690 $1\core_core_spro$next[9:0]$13683 $1\core_core_reg3_ok$next[0:0]$13679 $1\core_core_reg3$next[6:0]$13678 $1\core_core_reg2_ok$next[0:0]$13677 $1\core_core_reg2$next[6:0]$13676 $1\core_core_reg1_ok$next[0:0]$13675 $1\core_core_reg1$next[6:0]$13674 $1\core_ea_ok$next[0:0]$13686 $1\core_core_ea$next[6:0]$13666 $1\core_rego_ok$next[0:0]$13689 $1\core_core_rego$next[6:0]$13680 $1\core_asmcode$next[7:0]$13633 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
case
- assign $1\core_asmcode$next[7:0]$13841 \core_asmcode
- assign $1\core_core_core_cia$next[63:0]$13842 \core_core_core_cia
- assign $1\core_core_core_cr_rd$next[7:0]$13843 \core_core_core_cr_rd
- assign $1\core_core_core_cr_rd_ok$next[0:0]$13844 \core_core_core_cr_rd_ok
- assign $1\core_core_core_cr_wr$next[7:0]$13845 \core_core_core_cr_wr
- assign $1\core_core_core_exc_$signal$3$next[0:0]$13846 \core_core_core_exc_$signal$3
- assign $1\core_core_core_exc_$signal$4$next[0:0]$13847 \core_core_core_exc_$signal$4
- assign $1\core_core_core_exc_$signal$5$next[0:0]$13848 \core_core_core_exc_$signal$5
- assign $1\core_core_core_exc_$signal$6$next[0:0]$13849 \core_core_core_exc_$signal$6
- assign $1\core_core_core_exc_$signal$7$next[0:0]$13850 \core_core_core_exc_$signal$7
- assign $1\core_core_core_exc_$signal$8$next[0:0]$13851 \core_core_core_exc_$signal$8
- assign $1\core_core_core_exc_$signal$9$next[0:0]$13852 \core_core_core_exc_$signal$9
- assign $1\core_core_core_exc_$signal$next[0:0]$13853 \core_core_core_exc_$signal
- assign $1\core_core_core_fn_unit$next[13:0]$13854 \core_core_core_fn_unit
- assign $1\core_core_core_input_carry$next[1:0]$13855 \core_core_core_input_carry
- assign $1\core_core_core_insn$next[31:0]$13856 \core_core_core_insn
- assign $1\core_core_core_insn_type$next[6:0]$13857 \core_core_core_insn_type
- assign $1\core_core_core_is_32bit$next[0:0]$13858 \core_core_core_is_32bit
- assign $1\core_core_core_msr$next[63:0]$13859 \core_core_core_msr
- assign $1\core_core_core_oe$next[0:0]$13860 \core_core_core_oe
- assign $1\core_core_core_oe_ok$next[0:0]$13861 \core_core_core_oe_ok
- assign $1\core_core_core_rc$next[0:0]$13862 \core_core_core_rc
- assign $1\core_core_core_rc_ok$next[0:0]$13863 \core_core_core_rc_ok
- assign $1\core_core_core_trapaddr$next[12:0]$13864 \core_core_core_trapaddr
- assign $1\core_core_core_traptype$next[7:0]$13865 \core_core_core_traptype
- assign $1\core_core_cr_in1$next[6:0]$13866 \core_core_cr_in1
- assign $1\core_core_cr_in1_ok$next[0:0]$13867 \core_core_cr_in1_ok
- assign $1\core_core_cr_in2$1$next[6:0]$13868 \core_core_cr_in2$1
- assign $1\core_core_cr_in2$next[6:0]$13869 \core_core_cr_in2
- assign $1\core_core_cr_in2_ok$2$next[0:0]$13870 \core_core_cr_in2_ok$2
- assign $1\core_core_cr_in2_ok$next[0:0]$13871 \core_core_cr_in2_ok
- assign $1\core_core_cr_out$next[6:0]$13872 \core_core_cr_out
- assign $1\core_core_cr_wr_ok$next[0:0]$13873 \core_core_cr_wr_ok
- assign $1\core_core_ea$next[6:0]$13874 \core_core_ea
- assign $1\core_core_fast1$next[2:0]$13875 \core_core_fast1
- assign $1\core_core_fast1_ok$next[0:0]$13876 \core_core_fast1_ok
- assign $1\core_core_fast2$next[2:0]$13877 \core_core_fast2
- assign $1\core_core_fast2_ok$next[0:0]$13878 \core_core_fast2_ok
- assign $1\core_core_fasto1$next[2:0]$13879 \core_core_fasto1
- assign $1\core_core_fasto2$next[2:0]$13880 \core_core_fasto2
- assign $1\core_core_lk$next[0:0]$13881 \core_core_lk
- assign $1\core_core_reg1$next[6:0]$13882 \core_core_reg1
- assign $1\core_core_reg1_ok$next[0:0]$13883 \core_core_reg1_ok
- assign $1\core_core_reg2$next[6:0]$13884 \core_core_reg2
- assign $1\core_core_reg2_ok$next[0:0]$13885 \core_core_reg2_ok
- assign $1\core_core_reg3$next[6:0]$13886 \core_core_reg3
- assign $1\core_core_reg3_ok$next[0:0]$13887 \core_core_reg3_ok
- assign $1\core_core_rego$next[6:0]$13888 \core_core_rego
- assign $1\core_core_spr1$next[9:0]$13889 \core_core_spr1
- assign $1\core_core_spr1_ok$next[0:0]$13890 \core_core_spr1_ok
- assign $1\core_core_spro$next[9:0]$13891 \core_core_spro
- assign $1\core_core_xer_in$next[2:0]$13892 \core_core_xer_in
- assign $1\core_cr_out_ok$next[0:0]$13893 \core_cr_out_ok
- assign $1\core_ea_ok$next[0:0]$13894 \core_ea_ok
- assign $1\core_fasto1_ok$next[0:0]$13895 \core_fasto1_ok
- assign $1\core_fasto2_ok$next[0:0]$13896 \core_fasto2_ok
- assign $1\core_rego_ok$next[0:0]$13897 \core_rego_ok
- assign $1\core_spro_ok$next[0:0]$13898 \core_spro_ok
- assign $1\core_xer_out$next[0:0]$13899 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$13633 \core_asmcode
+ assign $1\core_core_core_cia$next[63:0]$13634 \core_core_core_cia
+ assign $1\core_core_core_cr_rd$next[7:0]$13635 \core_core_core_cr_rd
+ assign $1\core_core_core_cr_rd_ok$next[0:0]$13636 \core_core_core_cr_rd_ok
+ assign $1\core_core_core_cr_wr$next[7:0]$13637 \core_core_core_cr_wr
+ assign $1\core_core_core_exc_$signal$3$next[0:0]$13638 \core_core_core_exc_$signal$3
+ assign $1\core_core_core_exc_$signal$4$next[0:0]$13639 \core_core_core_exc_$signal$4
+ assign $1\core_core_core_exc_$signal$5$next[0:0]$13640 \core_core_core_exc_$signal$5
+ assign $1\core_core_core_exc_$signal$6$next[0:0]$13641 \core_core_core_exc_$signal$6
+ assign $1\core_core_core_exc_$signal$7$next[0:0]$13642 \core_core_core_exc_$signal$7
+ assign $1\core_core_core_exc_$signal$8$next[0:0]$13643 \core_core_core_exc_$signal$8
+ assign $1\core_core_core_exc_$signal$9$next[0:0]$13644 \core_core_core_exc_$signal$9
+ assign $1\core_core_core_exc_$signal$next[0:0]$13645 \core_core_core_exc_$signal
+ assign $1\core_core_core_fn_unit$next[13:0]$13646 \core_core_core_fn_unit
+ assign $1\core_core_core_input_carry$next[1:0]$13647 \core_core_core_input_carry
+ assign $1\core_core_core_insn$next[31:0]$13648 \core_core_core_insn
+ assign $1\core_core_core_insn_type$next[6:0]$13649 \core_core_core_insn_type
+ assign $1\core_core_core_is_32bit$next[0:0]$13650 \core_core_core_is_32bit
+ assign $1\core_core_core_msr$next[63:0]$13651 \core_core_core_msr
+ assign $1\core_core_core_oe$next[0:0]$13652 \core_core_core_oe
+ assign $1\core_core_core_oe_ok$next[0:0]$13653 \core_core_core_oe_ok
+ assign $1\core_core_core_rc$next[0:0]$13654 \core_core_core_rc
+ assign $1\core_core_core_rc_ok$next[0:0]$13655 \core_core_core_rc_ok
+ assign $1\core_core_core_trapaddr$next[12:0]$13656 \core_core_core_trapaddr
+ assign $1\core_core_core_traptype$next[7:0]$13657 \core_core_core_traptype
+ assign $1\core_core_cr_in1$next[6:0]$13658 \core_core_cr_in1
+ assign $1\core_core_cr_in1_ok$next[0:0]$13659 \core_core_cr_in1_ok
+ assign $1\core_core_cr_in2$1$next[6:0]$13660 \core_core_cr_in2$1
+ assign $1\core_core_cr_in2$next[6:0]$13661 \core_core_cr_in2
+ assign $1\core_core_cr_in2_ok$2$next[0:0]$13662 \core_core_cr_in2_ok$2
+ assign $1\core_core_cr_in2_ok$next[0:0]$13663 \core_core_cr_in2_ok
+ assign $1\core_core_cr_out$next[6:0]$13664 \core_core_cr_out
+ assign $1\core_core_cr_wr_ok$next[0:0]$13665 \core_core_cr_wr_ok
+ assign $1\core_core_ea$next[6:0]$13666 \core_core_ea
+ assign $1\core_core_fast1$next[2:0]$13667 \core_core_fast1
+ assign $1\core_core_fast1_ok$next[0:0]$13668 \core_core_fast1_ok
+ assign $1\core_core_fast2$next[2:0]$13669 \core_core_fast2
+ assign $1\core_core_fast2_ok$next[0:0]$13670 \core_core_fast2_ok
+ assign $1\core_core_fasto1$next[2:0]$13671 \core_core_fasto1
+ assign $1\core_core_fasto2$next[2:0]$13672 \core_core_fasto2
+ assign $1\core_core_lk$next[0:0]$13673 \core_core_lk
+ assign $1\core_core_reg1$next[6:0]$13674 \core_core_reg1
+ assign $1\core_core_reg1_ok$next[0:0]$13675 \core_core_reg1_ok
+ assign $1\core_core_reg2$next[6:0]$13676 \core_core_reg2
+ assign $1\core_core_reg2_ok$next[0:0]$13677 \core_core_reg2_ok
+ assign $1\core_core_reg3$next[6:0]$13678 \core_core_reg3
+ assign $1\core_core_reg3_ok$next[0:0]$13679 \core_core_reg3_ok
+ assign $1\core_core_rego$next[6:0]$13680 \core_core_rego
+ assign $1\core_core_spr1$next[9:0]$13681 \core_core_spr1
+ assign $1\core_core_spr1_ok$next[0:0]$13682 \core_core_spr1_ok
+ assign $1\core_core_spro$next[9:0]$13683 \core_core_spro
+ assign $1\core_core_xer_in$next[2:0]$13684 \core_core_xer_in
+ assign $1\core_cr_out_ok$next[0:0]$13685 \core_cr_out_ok
+ assign $1\core_ea_ok$next[0:0]$13686 \core_ea_ok
+ assign $1\core_fasto1_ok$next[0:0]$13687 \core_fasto1_ok
+ assign $1\core_fasto2_ok$next[0:0]$13688 \core_fasto2_ok
+ assign $1\core_rego_ok$next[0:0]$13689 \core_rego_ok
+ assign $1\core_spro_ok$next[0:0]$13690 \core_spro_ok
+ assign $1\core_xer_out$next[0:0]$13691 \core_xer_out
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_rego_ok$next[0:0]$13984 1'0
- assign $3\core_ea_ok$next[0:0]$13981 1'0
- assign $3\core_core_reg1_ok$next[0:0]$13976 1'0
- assign $3\core_core_reg2_ok$next[0:0]$13977 1'0
- assign $3\core_core_reg3_ok$next[0:0]$13978 1'0
- assign $3\core_spro_ok$next[0:0]$13985 1'0
- assign $3\core_core_spr1_ok$next[0:0]$13979 1'0
- assign $3\core_core_fast1_ok$next[0:0]$13974 1'0
- assign $3\core_core_fast2_ok$next[0:0]$13975 1'0
- assign $3\core_fasto1_ok$next[0:0]$13982 1'0
- assign $3\core_fasto2_ok$next[0:0]$13983 1'0
- assign $3\core_core_cr_in1_ok$next[0:0]$13970 1'0
- assign $3\core_core_cr_in2_ok$next[0:0]$13972 1'0
- assign $3\core_core_cr_in2_ok$2$next[0:0]$13971 1'0
- assign $3\core_cr_out_ok$next[0:0]$13980 1'0
- assign $3\core_core_core_rc_ok$next[0:0]$13969 1'0
- assign $3\core_core_core_oe_ok$next[0:0]$13968 1'0
- assign $3\core_core_core_exc_$signal$next[0:0]$13967 1'0
- assign $3\core_core_core_exc_$signal$3$next[0:0]$13960 1'0
- assign $3\core_core_core_exc_$signal$4$next[0:0]$13961 1'0
- assign $3\core_core_core_exc_$signal$5$next[0:0]$13962 1'0
- assign $3\core_core_core_exc_$signal$6$next[0:0]$13963 1'0
- assign $3\core_core_core_exc_$signal$7$next[0:0]$13964 1'0
- assign $3\core_core_core_exc_$signal$8$next[0:0]$13965 1'0
- assign $3\core_core_core_exc_$signal$9$next[0:0]$13966 1'0
- assign $3\core_core_core_cr_rd_ok$next[0:0]$13959 1'0
- assign $3\core_core_cr_wr_ok$next[0:0]$13973 1'0
+ assign $3\core_rego_ok$next[0:0]$13776 1'0
+ assign $3\core_ea_ok$next[0:0]$13773 1'0
+ assign $3\core_core_reg1_ok$next[0:0]$13768 1'0
+ assign $3\core_core_reg2_ok$next[0:0]$13769 1'0
+ assign $3\core_core_reg3_ok$next[0:0]$13770 1'0
+ assign $3\core_spro_ok$next[0:0]$13777 1'0
+ assign $3\core_core_spr1_ok$next[0:0]$13771 1'0
+ assign $3\core_core_fast1_ok$next[0:0]$13766 1'0
+ assign $3\core_core_fast2_ok$next[0:0]$13767 1'0
+ assign $3\core_fasto1_ok$next[0:0]$13774 1'0
+ assign $3\core_fasto2_ok$next[0:0]$13775 1'0
+ assign $3\core_core_cr_in1_ok$next[0:0]$13762 1'0
+ assign $3\core_core_cr_in2_ok$next[0:0]$13764 1'0
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13763 1'0
+ assign $3\core_cr_out_ok$next[0:0]$13772 1'0
+ assign $3\core_core_core_rc_ok$next[0:0]$13761 1'0
+ assign $3\core_core_core_oe_ok$next[0:0]$13760 1'0
+ assign $3\core_core_core_exc_$signal$next[0:0]$13759 1'0
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13752 1'0
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13753 1'0
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13754 1'0
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13755 1'0
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13756 1'0
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13757 1'0
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13758 1'0
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13751 1'0
+ assign $3\core_core_cr_wr_ok$next[0:0]$13765 1'0
case
- assign $3\core_core_core_cr_rd_ok$next[0:0]$13959 $1\core_core_core_cr_rd_ok$next[0:0]$13844
- assign $3\core_core_core_exc_$signal$3$next[0:0]$13960 $1\core_core_core_exc_$signal$3$next[0:0]$13846
- assign $3\core_core_core_exc_$signal$4$next[0:0]$13961 $1\core_core_core_exc_$signal$4$next[0:0]$13847
- assign $3\core_core_core_exc_$signal$5$next[0:0]$13962 $1\core_core_core_exc_$signal$5$next[0:0]$13848
- assign $3\core_core_core_exc_$signal$6$next[0:0]$13963 $1\core_core_core_exc_$signal$6$next[0:0]$13849
- assign $3\core_core_core_exc_$signal$7$next[0:0]$13964 $1\core_core_core_exc_$signal$7$next[0:0]$13850
- assign $3\core_core_core_exc_$signal$8$next[0:0]$13965 $1\core_core_core_exc_$signal$8$next[0:0]$13851
- assign $3\core_core_core_exc_$signal$9$next[0:0]$13966 $1\core_core_core_exc_$signal$9$next[0:0]$13852
- assign $3\core_core_core_exc_$signal$next[0:0]$13967 $1\core_core_core_exc_$signal$next[0:0]$13853
- assign $3\core_core_core_oe_ok$next[0:0]$13968 $1\core_core_core_oe_ok$next[0:0]$13861
- assign $3\core_core_core_rc_ok$next[0:0]$13969 $1\core_core_core_rc_ok$next[0:0]$13863
- assign $3\core_core_cr_in1_ok$next[0:0]$13970 $1\core_core_cr_in1_ok$next[0:0]$13867
- assign $3\core_core_cr_in2_ok$2$next[0:0]$13971 $1\core_core_cr_in2_ok$2$next[0:0]$13870
- assign $3\core_core_cr_in2_ok$next[0:0]$13972 $1\core_core_cr_in2_ok$next[0:0]$13871
- assign $3\core_core_cr_wr_ok$next[0:0]$13973 $1\core_core_cr_wr_ok$next[0:0]$13873
- assign $3\core_core_fast1_ok$next[0:0]$13974 $1\core_core_fast1_ok$next[0:0]$13876
- assign $3\core_core_fast2_ok$next[0:0]$13975 $1\core_core_fast2_ok$next[0:0]$13878
- assign $3\core_core_reg1_ok$next[0:0]$13976 $1\core_core_reg1_ok$next[0:0]$13883
- assign $3\core_core_reg2_ok$next[0:0]$13977 $1\core_core_reg2_ok$next[0:0]$13885
- assign $3\core_core_reg3_ok$next[0:0]$13978 $1\core_core_reg3_ok$next[0:0]$13887
- assign $3\core_core_spr1_ok$next[0:0]$13979 $1\core_core_spr1_ok$next[0:0]$13890
- assign $3\core_cr_out_ok$next[0:0]$13980 $1\core_cr_out_ok$next[0:0]$13893
- assign $3\core_ea_ok$next[0:0]$13981 $1\core_ea_ok$next[0:0]$13894
- assign $3\core_fasto1_ok$next[0:0]$13982 $1\core_fasto1_ok$next[0:0]$13895
- assign $3\core_fasto2_ok$next[0:0]$13983 $1\core_fasto2_ok$next[0:0]$13896
- assign $3\core_rego_ok$next[0:0]$13984 $1\core_rego_ok$next[0:0]$13897
- assign $3\core_spro_ok$next[0:0]$13985 $1\core_spro_ok$next[0:0]$13898
+ assign $3\core_core_core_cr_rd_ok$next[0:0]$13751 $1\core_core_core_cr_rd_ok$next[0:0]$13636
+ assign $3\core_core_core_exc_$signal$3$next[0:0]$13752 $1\core_core_core_exc_$signal$3$next[0:0]$13638
+ assign $3\core_core_core_exc_$signal$4$next[0:0]$13753 $1\core_core_core_exc_$signal$4$next[0:0]$13639
+ assign $3\core_core_core_exc_$signal$5$next[0:0]$13754 $1\core_core_core_exc_$signal$5$next[0:0]$13640
+ assign $3\core_core_core_exc_$signal$6$next[0:0]$13755 $1\core_core_core_exc_$signal$6$next[0:0]$13641
+ assign $3\core_core_core_exc_$signal$7$next[0:0]$13756 $1\core_core_core_exc_$signal$7$next[0:0]$13642
+ assign $3\core_core_core_exc_$signal$8$next[0:0]$13757 $1\core_core_core_exc_$signal$8$next[0:0]$13643
+ assign $3\core_core_core_exc_$signal$9$next[0:0]$13758 $1\core_core_core_exc_$signal$9$next[0:0]$13644
+ assign $3\core_core_core_exc_$signal$next[0:0]$13759 $1\core_core_core_exc_$signal$next[0:0]$13645
+ assign $3\core_core_core_oe_ok$next[0:0]$13760 $1\core_core_core_oe_ok$next[0:0]$13653
+ assign $3\core_core_core_rc_ok$next[0:0]$13761 $1\core_core_core_rc_ok$next[0:0]$13655
+ assign $3\core_core_cr_in1_ok$next[0:0]$13762 $1\core_core_cr_in1_ok$next[0:0]$13659
+ assign $3\core_core_cr_in2_ok$2$next[0:0]$13763 $1\core_core_cr_in2_ok$2$next[0:0]$13662
+ assign $3\core_core_cr_in2_ok$next[0:0]$13764 $1\core_core_cr_in2_ok$next[0:0]$13663
+ assign $3\core_core_cr_wr_ok$next[0:0]$13765 $1\core_core_cr_wr_ok$next[0:0]$13665
+ assign $3\core_core_fast1_ok$next[0:0]$13766 $1\core_core_fast1_ok$next[0:0]$13668
+ assign $3\core_core_fast2_ok$next[0:0]$13767 $1\core_core_fast2_ok$next[0:0]$13670
+ assign $3\core_core_reg1_ok$next[0:0]$13768 $1\core_core_reg1_ok$next[0:0]$13675
+ assign $3\core_core_reg2_ok$next[0:0]$13769 $1\core_core_reg2_ok$next[0:0]$13677
+ assign $3\core_core_reg3_ok$next[0:0]$13770 $1\core_core_reg3_ok$next[0:0]$13679
+ assign $3\core_core_spr1_ok$next[0:0]$13771 $1\core_core_spr1_ok$next[0:0]$13682
+ assign $3\core_cr_out_ok$next[0:0]$13772 $1\core_cr_out_ok$next[0:0]$13685
+ assign $3\core_ea_ok$next[0:0]$13773 $1\core_ea_ok$next[0:0]$13686
+ assign $3\core_fasto1_ok$next[0:0]$13774 $1\core_fasto1_ok$next[0:0]$13687
+ assign $3\core_fasto2_ok$next[0:0]$13775 $1\core_fasto2_ok$next[0:0]$13688
+ assign $3\core_rego_ok$next[0:0]$13776 $1\core_rego_ok$next[0:0]$13689
+ assign $3\core_spro_ok$next[0:0]$13777 $1\core_spro_ok$next[0:0]$13690
end
sync always
- update \core_asmcode$next $0\core_asmcode$next[7:0]$13782
- update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13783
- update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13784
- update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13785
- update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13786
- update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13787
- update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13788
- update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13789
- update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13790
- update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13791
- update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13792
- update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13793
- update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13794
- update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13795
- update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13796
- update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13797
- update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13798
- update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13799
- update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13800
- update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13801
- update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13802
- update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13803
- update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13804
- update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13805
- update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13806
- update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13807
- update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13808
- update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13809
- update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13810
- update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13811
- update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13812
- update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13813
- update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13814
- update \core_core_ea$next $0\core_core_ea$next[6:0]$13815
- update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13816
- update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13817
- update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13818
- update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13819
- update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13820
- update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13821
- update \core_core_lk$next $0\core_core_lk$next[0:0]$13822
- update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13823
- update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13824
- update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13825
- update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13826
- update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13827
- update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13828
- update \core_core_rego$next $0\core_core_rego$next[6:0]$13829
- update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13830
- update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13831
- update \core_core_spro$next $0\core_core_spro$next[9:0]$13832
- update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13833
- update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13834
- update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13835
- update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13836
- update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13837
- update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13838
- update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13839
- update \core_xer_out$next $0\core_xer_out$next[0:0]$13840
- end
- attribute \src "libresoc.v:200630.3-200638.6"
- process $proc$libresoc.v:200630$13986
- assign { } { }
- assign { } { }
- assign $0\dec2_cur_eint$next[0:0]$13987 $1\dec2_cur_eint$next[0:0]$13988
- attribute \src "libresoc.v:200631.5-200631.29"
- switch \initial
- attribute \src "libresoc.v:200631.9-200631.17"
+ update \core_asmcode$next $0\core_asmcode$next[7:0]$13574
+ update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13575
+ update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13576
+ update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13577
+ update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13578
+ update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13579
+ update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13580
+ update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13581
+ update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13582
+ update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13583
+ update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13584
+ update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13585
+ update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13586
+ update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13587
+ update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13588
+ update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13589
+ update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13590
+ update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13591
+ update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13592
+ update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13593
+ update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13594
+ update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13595
+ update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13596
+ update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13597
+ update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13598
+ update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13599
+ update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13600
+ update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13601
+ update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13602
+ update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13603
+ update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13604
+ update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13605
+ update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13606
+ update \core_core_ea$next $0\core_core_ea$next[6:0]$13607
+ update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13608
+ update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13609
+ update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13610
+ update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13611
+ update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13612
+ update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13613
+ update \core_core_lk$next $0\core_core_lk$next[0:0]$13614
+ update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13615
+ update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13616
+ update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13617
+ update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13618
+ update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13619
+ update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13620
+ update \core_core_rego$next $0\core_core_rego$next[6:0]$13621
+ update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13622
+ update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13623
+ update \core_core_spro$next $0\core_core_spro$next[9:0]$13624
+ update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13625
+ update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13626
+ update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13627
+ update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13628
+ update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13629
+ update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13630
+ update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13631
+ update \core_xer_out$next $0\core_xer_out$next[0:0]$13632
+ end
+ attribute \src "libresoc.v:200526.3-200534.6"
+ process $proc$libresoc.v:200526$13778
+ assign { } { }
+ assign { } { }
+ assign $0\dec2_cur_eint$next[0:0]$13779 $1\dec2_cur_eint$next[0:0]$13780
+ attribute \src "libresoc.v:200527.5-200527.29"
+ switch \initial
+ attribute \src "libresoc.v:200527.9-200527.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dec2_cur_eint$next[0:0]$13988 1'0
+ assign $1\dec2_cur_eint$next[0:0]$13780 1'0
case
- assign $1\dec2_cur_eint$next[0:0]$13988 \xics_icp_core_irq_o
+ assign $1\dec2_cur_eint$next[0:0]$13780 \xics_icp_core_irq_o
end
sync always
- update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13987
+ update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13779
end
- attribute \src "libresoc.v:200639.3-200648.6"
- process $proc$libresoc.v:200639$13989
+ attribute \src "libresoc.v:200535.3-200544.6"
+ process $proc$libresoc.v:200535$13781
assign { } { }
assign { } { }
- assign $0\delay$next[1:0]$13990 $1\delay$next[1:0]$13991
- attribute \src "libresoc.v:200640.5-200640.29"
+ assign $0\delay$next[1:0]$13782 $1\delay$next[1:0]$13783
+ attribute \src "libresoc.v:200536.5-200536.29"
switch \initial
- attribute \src "libresoc.v:200640.9-200640.17"
+ attribute \src "libresoc.v:200536.9-200536.17"
case 1'1
case
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800"
switch \$23
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\delay$next[1:0]$13991 \$25 [1:0]
+ assign $1\delay$next[1:0]$13783 \$25 [1:0]
case
- assign $1\delay$next[1:0]$13991 \delay
+ assign $1\delay$next[1:0]$13783 \delay
end
sync always
- update \delay$next $0\delay$next[1:0]$13990
+ update \delay$next $0\delay$next[1:0]$13782
end
- connect \$101 $add$libresoc.v:197633$13291_Y
- connect \$103 $mul$libresoc.v:197634$13292_Y
- connect \$99 $shr$libresoc.v:197635$13293_Y [31:0]
- connect \$106 $not$libresoc.v:197636$13294_Y
- connect \$108 $not$libresoc.v:197637$13295_Y
- connect \$110 $and$libresoc.v:197638$13296_Y
- connect \$112 $not$libresoc.v:197639$13297_Y
- connect \$114 $not$libresoc.v:197640$13298_Y
- connect \$116 $and$libresoc.v:197641$13299_Y
- connect \$118 $or$libresoc.v:197642$13300_Y
+ connect \$101 $add$libresoc.v:197529$13083_Y
+ connect \$103 $mul$libresoc.v:197530$13084_Y
+ connect \$99 $shr$libresoc.v:197531$13085_Y [31:0]
+ connect \$106 $not$libresoc.v:197532$13086_Y
+ connect \$108 $not$libresoc.v:197533$13087_Y
+ connect \$110 $and$libresoc.v:197534$13088_Y
+ connect \$112 $not$libresoc.v:197535$13089_Y
+ connect \$114 $not$libresoc.v:197536$13090_Y
+ connect \$116 $and$libresoc.v:197537$13091_Y
+ connect \$118 $or$libresoc.v:197538$13092_Y
connect \$120 1'1
- connect \$122 $or$libresoc.v:197644$13301_Y
- connect \$125 $add$libresoc.v:197645$13302_Y
- connect \$128 $add$libresoc.v:197646$13303_Y
- connect \$130 $not$libresoc.v:197647$13304_Y
- connect \$132 $not$libresoc.v:197648$13305_Y
- connect \$134 $and$libresoc.v:197649$13306_Y
- connect \$136 $not$libresoc.v:197650$13307_Y
- connect \$138 $not$libresoc.v:197651$13308_Y
- connect \$140 $and$libresoc.v:197652$13309_Y
- connect \$142 $eq$libresoc.v:197653$13310_Y
- connect \$144 $and$libresoc.v:197654$13311_Y
- connect \$146 $not$libresoc.v:197655$13312_Y
- connect \$148 $not$libresoc.v:197656$13313_Y
- connect \$150 $and$libresoc.v:197657$13314_Y
- connect \$152 $or$libresoc.v:197658$13315_Y
+ connect \$122 $or$libresoc.v:197540$13093_Y
+ connect \$125 $add$libresoc.v:197541$13094_Y
+ connect \$128 $add$libresoc.v:197542$13095_Y
+ connect \$130 $not$libresoc.v:197543$13096_Y
+ connect \$132 $not$libresoc.v:197544$13097_Y
+ connect \$134 $and$libresoc.v:197545$13098_Y
+ connect \$136 $not$libresoc.v:197546$13099_Y
+ connect \$138 $not$libresoc.v:197547$13100_Y
+ connect \$140 $and$libresoc.v:197548$13101_Y
+ connect \$142 $eq$libresoc.v:197549$13102_Y
+ connect \$144 $and$libresoc.v:197550$13103_Y
+ connect \$146 $not$libresoc.v:197551$13104_Y
+ connect \$148 $not$libresoc.v:197552$13105_Y
+ connect \$150 $and$libresoc.v:197553$13106_Y
+ connect \$152 $or$libresoc.v:197554$13107_Y
connect \$154 1'1
- connect \$156 $or$libresoc.v:197660$13316_Y
- connect \$158 $not$libresoc.v:197661$13317_Y
- connect \$160 $not$libresoc.v:197662$13318_Y
- connect \$162 $and$libresoc.v:197663$13319_Y
- connect \$164 $not$libresoc.v:197664$13320_Y
- connect \$166 $not$libresoc.v:197665$13321_Y
- connect \$168 $and$libresoc.v:197666$13322_Y
- connect \$170 $not$libresoc.v:197667$13323_Y
- connect \$172 $not$libresoc.v:197668$13324_Y
- connect \$174 $and$libresoc.v:197669$13325_Y
- connect \$176 $not$libresoc.v:197670$13326_Y
- connect \$178 $not$libresoc.v:197671$13327_Y
- connect \$180 $and$libresoc.v:197672$13328_Y
- connect \$182 $not$libresoc.v:197673$13329_Y
- connect \$184 $not$libresoc.v:197674$13330_Y
- connect \$186 $and$libresoc.v:197675$13331_Y
- connect \$188 $not$libresoc.v:197676$13332_Y
- connect \$190 $not$libresoc.v:197677$13333_Y
- connect \$192 $and$libresoc.v:197678$13334_Y
- connect \$195 $and$libresoc.v:197679$13335_Y
- connect \$194 $reduce_or$libresoc.v:197680$13336_Y
- connect \$198 $not$libresoc.v:197681$13337_Y
- connect \$200 $not$libresoc.v:197682$13338_Y
- connect \$202 $and$libresoc.v:197683$13339_Y
- connect \$204 $not$libresoc.v:197684$13340_Y
- connect \$206 $not$libresoc.v:197685$13341_Y
- connect \$208 $and$libresoc.v:197686$13342_Y
- connect \$210 $or$libresoc.v:197687$13343_Y
+ connect \$156 $or$libresoc.v:197556$13108_Y
+ connect \$158 $not$libresoc.v:197557$13109_Y
+ connect \$160 $not$libresoc.v:197558$13110_Y
+ connect \$162 $and$libresoc.v:197559$13111_Y
+ connect \$164 $not$libresoc.v:197560$13112_Y
+ connect \$166 $not$libresoc.v:197561$13113_Y
+ connect \$168 $and$libresoc.v:197562$13114_Y
+ connect \$170 $not$libresoc.v:197563$13115_Y
+ connect \$172 $not$libresoc.v:197564$13116_Y
+ connect \$174 $and$libresoc.v:197565$13117_Y
+ connect \$176 $not$libresoc.v:197566$13118_Y
+ connect \$178 $not$libresoc.v:197567$13119_Y
+ connect \$180 $and$libresoc.v:197568$13120_Y
+ connect \$182 $not$libresoc.v:197569$13121_Y
+ connect \$184 $not$libresoc.v:197570$13122_Y
+ connect \$186 $and$libresoc.v:197571$13123_Y
+ connect \$188 $not$libresoc.v:197572$13124_Y
+ connect \$190 $not$libresoc.v:197573$13125_Y
+ connect \$192 $and$libresoc.v:197574$13126_Y
+ connect \$195 $and$libresoc.v:197575$13127_Y
+ connect \$194 $reduce_or$libresoc.v:197576$13128_Y
+ connect \$198 $not$libresoc.v:197577$13129_Y
+ connect \$200 $not$libresoc.v:197578$13130_Y
+ connect \$202 $and$libresoc.v:197579$13131_Y
+ connect \$204 $not$libresoc.v:197580$13132_Y
+ connect \$206 $not$libresoc.v:197581$13133_Y
+ connect \$208 $and$libresoc.v:197582$13134_Y
+ connect \$210 $or$libresoc.v:197583$13135_Y
connect \$212 1'1
- connect \$214 $or$libresoc.v:197689$13344_Y
- connect \$216 $not$libresoc.v:197690$13345_Y
- connect \$218 $not$libresoc.v:197691$13346_Y
- connect \$220 $and$libresoc.v:197692$13347_Y
- connect \$222 $not$libresoc.v:197693$13348_Y
- connect \$224 $not$libresoc.v:197694$13349_Y
- connect \$226 $and$libresoc.v:197695$13350_Y
- connect \$229 $and$libresoc.v:197696$13351_Y
- connect \$228 $reduce_or$libresoc.v:197697$13352_Y
- connect \$232 $eq$libresoc.v:197698$13353_Y
- connect \$234 $and$libresoc.v:197699$13354_Y
- connect \$236 $not$libresoc.v:197700$13355_Y
- connect \$238 $not$libresoc.v:197701$13356_Y
- connect \$23 $ne$libresoc.v:197702$13357_Y
- connect \$240 $not$libresoc.v:197703$13358_Y
- connect \$242 $and$libresoc.v:197704$13359_Y
- connect \$244 $not$libresoc.v:197705$13360_Y
- connect \$246 $not$libresoc.v:197706$13361_Y
- connect \$248 $and$libresoc.v:197707$13362_Y
- connect \$250 $eq$libresoc.v:197708$13363_Y
- connect \$252 $pos$libresoc.v:197709$13364_Y
- connect \$254 $ne$libresoc.v:197710$13365_Y
- connect \$256 $not$libresoc.v:197711$13366_Y
- connect \$258 $not$libresoc.v:197712$13367_Y
- connect \$260 $pos$libresoc.v:197713$13369_Y
- connect \$262 $pos$libresoc.v:197714$13371_Y
- connect \$265 $sub$libresoc.v:197715$13372_Y
- connect \$268 $add$libresoc.v:197716$13373_Y
- connect \$26 $sub$libresoc.v:197717$13374_Y
- connect \$28 $or$libresoc.v:197718$13375_Y
- connect \$30 $or$libresoc.v:197719$13376_Y
- connect \$32 $ne$libresoc.v:197720$13377_Y
- connect \$34 $not$libresoc.v:197721$13378_Y
- connect \$36 $and$libresoc.v:197722$13379_Y
- connect \$38 $not$libresoc.v:197723$13380_Y
- connect \$40 $not$libresoc.v:197724$13381_Y
- connect \$42 $pos$libresoc.v:197725$13383_Y
- connect \$44 $not$libresoc.v:197726$13384_Y
- connect \$46 $not$libresoc.v:197727$13385_Y
- connect \$48 $and$libresoc.v:197728$13386_Y
- connect \$50 $eq$libresoc.v:197729$13387_Y
- connect \$52 $and$libresoc.v:197730$13388_Y
- connect \$54 $not$libresoc.v:197731$13389_Y
- connect \$56 $not$libresoc.v:197732$13390_Y
- connect \$58 $and$libresoc.v:197733$13391_Y
- connect \$60 $or$libresoc.v:197734$13392_Y
+ connect \$214 $or$libresoc.v:197585$13136_Y
+ connect \$216 $not$libresoc.v:197586$13137_Y
+ connect \$218 $not$libresoc.v:197587$13138_Y
+ connect \$220 $and$libresoc.v:197588$13139_Y
+ connect \$222 $not$libresoc.v:197589$13140_Y
+ connect \$224 $not$libresoc.v:197590$13141_Y
+ connect \$226 $and$libresoc.v:197591$13142_Y
+ connect \$229 $and$libresoc.v:197592$13143_Y
+ connect \$228 $reduce_or$libresoc.v:197593$13144_Y
+ connect \$232 $eq$libresoc.v:197594$13145_Y
+ connect \$234 $and$libresoc.v:197595$13146_Y
+ connect \$236 $not$libresoc.v:197596$13147_Y
+ connect \$238 $not$libresoc.v:197597$13148_Y
+ connect \$23 $ne$libresoc.v:197598$13149_Y
+ connect \$240 $not$libresoc.v:197599$13150_Y
+ connect \$242 $and$libresoc.v:197600$13151_Y
+ connect \$244 $not$libresoc.v:197601$13152_Y
+ connect \$246 $not$libresoc.v:197602$13153_Y
+ connect \$248 $and$libresoc.v:197603$13154_Y
+ connect \$250 $eq$libresoc.v:197604$13155_Y
+ connect \$252 $pos$libresoc.v:197605$13156_Y
+ connect \$254 $ne$libresoc.v:197606$13157_Y
+ connect \$256 $not$libresoc.v:197607$13158_Y
+ connect \$258 $not$libresoc.v:197608$13159_Y
+ connect \$260 $pos$libresoc.v:197609$13161_Y
+ connect \$262 $pos$libresoc.v:197610$13163_Y
+ connect \$265 $sub$libresoc.v:197611$13164_Y
+ connect \$268 $add$libresoc.v:197612$13165_Y
+ connect \$26 $sub$libresoc.v:197613$13166_Y
+ connect \$28 $or$libresoc.v:197614$13167_Y
+ connect \$30 $or$libresoc.v:197615$13168_Y
+ connect \$32 $ne$libresoc.v:197616$13169_Y
+ connect \$34 $not$libresoc.v:197617$13170_Y
+ connect \$36 $and$libresoc.v:197618$13171_Y
+ connect \$38 $not$libresoc.v:197619$13172_Y
+ connect \$40 $not$libresoc.v:197620$13173_Y
+ connect \$42 $pos$libresoc.v:197621$13175_Y
+ connect \$44 $not$libresoc.v:197622$13176_Y
+ connect \$46 $not$libresoc.v:197623$13177_Y
+ connect \$48 $and$libresoc.v:197624$13178_Y
+ connect \$50 $eq$libresoc.v:197625$13179_Y
+ connect \$52 $and$libresoc.v:197626$13180_Y
+ connect \$54 $not$libresoc.v:197627$13181_Y
+ connect \$56 $not$libresoc.v:197628$13182_Y
+ connect \$58 $and$libresoc.v:197629$13183_Y
+ connect \$60 $or$libresoc.v:197630$13184_Y
connect \$62 1'1
- connect \$64 $or$libresoc.v:197736$13393_Y
- connect \$66 $not$libresoc.v:197737$13394_Y
- connect \$68 $not$libresoc.v:197738$13395_Y
- connect \$70 $and$libresoc.v:197739$13396_Y
- connect \$72 $eq$libresoc.v:197740$13397_Y
- connect \$74 $and$libresoc.v:197741$13398_Y
- connect \$76 $not$libresoc.v:197742$13399_Y
- connect \$78 $not$libresoc.v:197743$13400_Y
- connect \$80 $and$libresoc.v:197744$13401_Y
- connect \$82 $or$libresoc.v:197745$13402_Y
+ connect \$64 $or$libresoc.v:197632$13185_Y
+ connect \$66 $not$libresoc.v:197633$13186_Y
+ connect \$68 $not$libresoc.v:197634$13187_Y
+ connect \$70 $and$libresoc.v:197635$13188_Y
+ connect \$72 $eq$libresoc.v:197636$13189_Y
+ connect \$74 $and$libresoc.v:197637$13190_Y
+ connect \$76 $not$libresoc.v:197638$13191_Y
+ connect \$78 $not$libresoc.v:197639$13192_Y
+ connect \$80 $and$libresoc.v:197640$13193_Y
+ connect \$82 $or$libresoc.v:197641$13194_Y
connect \$84 1'1
- connect \$86 $or$libresoc.v:197747$13403_Y
- connect \$88 $not$libresoc.v:197748$13404_Y
- connect \$90 $not$libresoc.v:197749$13405_Y
- connect \$93 $add$libresoc.v:197750$13406_Y
- connect \$96 $mul$libresoc.v:197751$13407_Y
- connect \$95 $shr$libresoc.v:197752$13408_Y [31:0]
+ connect \$86 $or$libresoc.v:197643$13195_Y
+ connect \$88 $not$libresoc.v:197644$13196_Y
+ connect \$90 $not$libresoc.v:197645$13197_Y
+ connect \$93 $add$libresoc.v:197646$13198_Y
+ connect \$96 $mul$libresoc.v:197647$13199_Y
+ connect \$95 $shr$libresoc.v:197648$13200_Y [31:0]
connect \$25 \$26
connect \$92 \$93
connect \$100 \$101
connect \por_clk \clk
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
end
-attribute \src "libresoc.v:200683.1-201874.10"
+attribute \src "libresoc.v:200579.1-201770.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0"
attribute \generator "nMigen"
module \trap0
- attribute \src "libresoc.v:201419.3-201420.25"
+ attribute \src "libresoc.v:201315.3-201316.25"
wire $0\all_rd_dly[0:0]
- attribute \src "libresoc.v:201417.3-201418.41"
+ attribute \src "libresoc.v:201313.3-201314.41"
wire $0\alu_done_dly[0:0]
- attribute \src "libresoc.v:201777.3-201785.6"
- wire $0\alu_l_r_alu$next[0:0]$14313
- attribute \src "libresoc.v:201345.3-201346.39"
+ attribute \src "libresoc.v:201673.3-201681.6"
+ wire $0\alu_l_r_alu$next[0:0]$14105
+ attribute \src "libresoc.v:201241.3-201242.39"
wire $0\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14239
- attribute \src "libresoc.v:201385.3-201386.61"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14031
+ attribute \src "libresoc.v:201281.3-201282.61"
wire width 64 $0\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240
- attribute \src "libresoc.v:201379.3-201380.69"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032
+ attribute \src "libresoc.v:201275.3-201276.69"
wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14241
- attribute \src "libresoc.v:201381.3-201382.63"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14033
+ attribute \src "libresoc.v:201277.3-201278.63"
wire width 32 $0\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14242
- attribute \src "libresoc.v:201377.3-201378.73"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14034
+ attribute \src "libresoc.v:201273.3-201274.73"
wire width 7 $0\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243
- attribute \src "libresoc.v:201387.3-201388.71"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035
+ attribute \src "libresoc.v:201283.3-201284.71"
wire $0\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244
- attribute \src "libresoc.v:201393.3-201394.71"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036
+ attribute \src "libresoc.v:201289.3-201290.71"
wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14245
- attribute \src "libresoc.v:201383.3-201384.61"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14037
+ attribute \src "libresoc.v:201279.3-201280.61"
wire width 64 $0\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246
- attribute \src "libresoc.v:201391.3-201392.71"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038
+ attribute \src "libresoc.v:201287.3-201288.71"
wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14247
- attribute \src "libresoc.v:201389.3-201390.71"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14039
+ attribute \src "libresoc.v:201285.3-201286.71"
wire width 8 $0\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:201768.3-201776.6"
- wire $0\alui_l_r_alui$next[0:0]$14310
- attribute \src "libresoc.v:201347.3-201348.43"
+ attribute \src "libresoc.v:201664.3-201672.6"
+ wire $0\alui_l_r_alui$next[0:0]$14102
+ attribute \src "libresoc.v:201243.3-201244.43"
wire $0\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:201618.3-201639.6"
- wire width 64 $0\data_r0__o$next[63:0]$14258
- attribute \src "libresoc.v:201373.3-201374.37"
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire width 64 $0\data_r0__o$next[63:0]$14050
+ attribute \src "libresoc.v:201269.3-201270.37"
wire width 64 $0\data_r0__o[63:0]
- attribute \src "libresoc.v:201618.3-201639.6"
- wire $0\data_r0__o_ok$next[0:0]$14259
- attribute \src "libresoc.v:201375.3-201376.43"
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire $0\data_r0__o_ok$next[0:0]$14051
+ attribute \src "libresoc.v:201271.3-201272.43"
wire $0\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:201640.3-201661.6"
- wire width 64 $0\data_r1__fast1$next[63:0]$14266
- attribute \src "libresoc.v:201369.3-201370.45"
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire width 64 $0\data_r1__fast1$next[63:0]$14058
+ attribute \src "libresoc.v:201265.3-201266.45"
wire width 64 $0\data_r1__fast1[63:0]
- attribute \src "libresoc.v:201640.3-201661.6"
- wire $0\data_r1__fast1_ok$next[0:0]$14267
- attribute \src "libresoc.v:201371.3-201372.51"
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire $0\data_r1__fast1_ok$next[0:0]$14059
+ attribute \src "libresoc.v:201267.3-201268.51"
wire $0\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:201662.3-201683.6"
- wire width 64 $0\data_r2__fast2$next[63:0]$14274
- attribute \src "libresoc.v:201365.3-201366.45"
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire width 64 $0\data_r2__fast2$next[63:0]$14066
+ attribute \src "libresoc.v:201261.3-201262.45"
wire width 64 $0\data_r2__fast2[63:0]
- attribute \src "libresoc.v:201662.3-201683.6"
- wire $0\data_r2__fast2_ok$next[0:0]$14275
- attribute \src "libresoc.v:201367.3-201368.51"
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire $0\data_r2__fast2_ok$next[0:0]$14067
+ attribute \src "libresoc.v:201263.3-201264.51"
wire $0\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:201684.3-201705.6"
- wire width 64 $0\data_r3__nia$next[63:0]$14282
- attribute \src "libresoc.v:201361.3-201362.41"
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire width 64 $0\data_r3__nia$next[63:0]$14074
+ attribute \src "libresoc.v:201257.3-201258.41"
wire width 64 $0\data_r3__nia[63:0]
- attribute \src "libresoc.v:201684.3-201705.6"
- wire $0\data_r3__nia_ok$next[0:0]$14283
- attribute \src "libresoc.v:201363.3-201364.47"
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire $0\data_r3__nia_ok$next[0:0]$14075
+ attribute \src "libresoc.v:201259.3-201260.47"
wire $0\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:201706.3-201727.6"
- wire width 64 $0\data_r4__msr$next[63:0]$14290
- attribute \src "libresoc.v:201357.3-201358.41"
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire width 64 $0\data_r4__msr$next[63:0]$14082
+ attribute \src "libresoc.v:201253.3-201254.41"
wire width 64 $0\data_r4__msr[63:0]
- attribute \src "libresoc.v:201706.3-201727.6"
- wire $0\data_r4__msr_ok$next[0:0]$14291
- attribute \src "libresoc.v:201359.3-201360.47"
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire $0\data_r4__msr_ok$next[0:0]$14083
+ attribute \src "libresoc.v:201255.3-201256.47"
wire $0\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:201786.3-201795.6"
+ attribute \src "libresoc.v:201682.3-201691.6"
wire width 64 $0\dest1_o[63:0]
- attribute \src "libresoc.v:201796.3-201805.6"
+ attribute \src "libresoc.v:201692.3-201701.6"
wire width 64 $0\dest2_o[63:0]
- attribute \src "libresoc.v:201806.3-201815.6"
+ attribute \src "libresoc.v:201702.3-201711.6"
wire width 64 $0\dest3_o[63:0]
- attribute \src "libresoc.v:201816.3-201825.6"
+ attribute \src "libresoc.v:201712.3-201721.6"
wire width 64 $0\dest4_o[63:0]
- attribute \src "libresoc.v:201826.3-201835.6"
+ attribute \src "libresoc.v:201722.3-201731.6"
wire width 64 $0\dest5_o[63:0]
- attribute \src "libresoc.v:200684.7-200684.20"
+ attribute \src "libresoc.v:200580.7-200580.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:201555.3-201563.6"
- wire $0\opc_l_r_opc$next[0:0]$14224
- attribute \src "libresoc.v:201403.3-201404.39"
+ attribute \src "libresoc.v:201451.3-201459.6"
+ wire $0\opc_l_r_opc$next[0:0]$14016
+ attribute \src "libresoc.v:201299.3-201300.39"
wire $0\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:201546.3-201554.6"
- wire $0\opc_l_s_opc$next[0:0]$14221
- attribute \src "libresoc.v:201405.3-201406.39"
+ attribute \src "libresoc.v:201442.3-201450.6"
+ wire $0\opc_l_s_opc$next[0:0]$14013
+ attribute \src "libresoc.v:201301.3-201302.39"
wire $0\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:201836.3-201844.6"
- wire width 5 $0\prev_wr_go$next[4:0]$14321
- attribute \src "libresoc.v:201415.3-201416.37"
+ attribute \src "libresoc.v:201732.3-201740.6"
+ wire width 5 $0\prev_wr_go$next[4:0]$14113
+ attribute \src "libresoc.v:201311.3-201312.37"
wire width 5 $0\prev_wr_go[4:0]
- attribute \src "libresoc.v:201500.3-201509.6"
+ attribute \src "libresoc.v:201396.3-201405.6"
wire $0\req_done[0:0]
- attribute \src "libresoc.v:201591.3-201599.6"
- wire width 5 $0\req_l_r_req$next[4:0]$14236
- attribute \src "libresoc.v:201395.3-201396.39"
+ attribute \src "libresoc.v:201487.3-201495.6"
+ wire width 5 $0\req_l_r_req$next[4:0]$14028
+ attribute \src "libresoc.v:201291.3-201292.39"
wire width 5 $0\req_l_r_req[4:0]
- attribute \src "libresoc.v:201582.3-201590.6"
- wire width 5 $0\req_l_s_req$next[4:0]$14233
- attribute \src "libresoc.v:201397.3-201398.39"
+ attribute \src "libresoc.v:201478.3-201486.6"
+ wire width 5 $0\req_l_s_req$next[4:0]$14025
+ attribute \src "libresoc.v:201293.3-201294.39"
wire width 5 $0\req_l_s_req[4:0]
- attribute \src "libresoc.v:201519.3-201527.6"
- wire $0\rok_l_r_rdok$next[0:0]$14212
- attribute \src "libresoc.v:201411.3-201412.41"
+ attribute \src "libresoc.v:201415.3-201423.6"
+ wire $0\rok_l_r_rdok$next[0:0]$14004
+ attribute \src "libresoc.v:201307.3-201308.41"
wire $0\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:201510.3-201518.6"
- wire $0\rok_l_s_rdok$next[0:0]$14209
- attribute \src "libresoc.v:201413.3-201414.41"
+ attribute \src "libresoc.v:201406.3-201414.6"
+ wire $0\rok_l_s_rdok$next[0:0]$14001
+ attribute \src "libresoc.v:201309.3-201310.41"
wire $0\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:201537.3-201545.6"
- wire $0\rst_l_r_rst$next[0:0]$14218
- attribute \src "libresoc.v:201407.3-201408.39"
+ attribute \src "libresoc.v:201433.3-201441.6"
+ wire $0\rst_l_r_rst$next[0:0]$14010
+ attribute \src "libresoc.v:201303.3-201304.39"
wire $0\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:201528.3-201536.6"
- wire $0\rst_l_s_rst$next[0:0]$14215
- attribute \src "libresoc.v:201409.3-201410.39"
+ attribute \src "libresoc.v:201424.3-201432.6"
+ wire $0\rst_l_s_rst$next[0:0]$14007
+ attribute \src "libresoc.v:201305.3-201306.39"
wire $0\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:201573.3-201581.6"
- wire width 4 $0\src_l_r_src$next[3:0]$14230
- attribute \src "libresoc.v:201399.3-201400.39"
+ attribute \src "libresoc.v:201469.3-201477.6"
+ wire width 4 $0\src_l_r_src$next[3:0]$14022
+ attribute \src "libresoc.v:201295.3-201296.39"
wire width 4 $0\src_l_r_src[3:0]
- attribute \src "libresoc.v:201564.3-201572.6"
- wire width 4 $0\src_l_s_src$next[3:0]$14227
- attribute \src "libresoc.v:201401.3-201402.39"
+ attribute \src "libresoc.v:201460.3-201468.6"
+ wire width 4 $0\src_l_s_src$next[3:0]$14019
+ attribute \src "libresoc.v:201297.3-201298.39"
wire width 4 $0\src_l_s_src[3:0]
- attribute \src "libresoc.v:201728.3-201737.6"
- wire width 64 $0\src_r0$next[63:0]$14298
- attribute \src "libresoc.v:201355.3-201356.29"
+ attribute \src "libresoc.v:201624.3-201633.6"
+ wire width 64 $0\src_r0$next[63:0]$14090
+ attribute \src "libresoc.v:201251.3-201252.29"
wire width 64 $0\src_r0[63:0]
- attribute \src "libresoc.v:201738.3-201747.6"
- wire width 64 $0\src_r1$next[63:0]$14301
- attribute \src "libresoc.v:201353.3-201354.29"
+ attribute \src "libresoc.v:201634.3-201643.6"
+ wire width 64 $0\src_r1$next[63:0]$14093
+ attribute \src "libresoc.v:201249.3-201250.29"
wire width 64 $0\src_r1[63:0]
- attribute \src "libresoc.v:201748.3-201757.6"
- wire width 64 $0\src_r2$next[63:0]$14304
- attribute \src "libresoc.v:201351.3-201352.29"
+ attribute \src "libresoc.v:201644.3-201653.6"
+ wire width 64 $0\src_r2$next[63:0]$14096
+ attribute \src "libresoc.v:201247.3-201248.29"
wire width 64 $0\src_r2[63:0]
- attribute \src "libresoc.v:201758.3-201767.6"
- wire width 64 $0\src_r3$next[63:0]$14307
- attribute \src "libresoc.v:201349.3-201350.29"
+ attribute \src "libresoc.v:201654.3-201663.6"
+ wire width 64 $0\src_r3$next[63:0]$14099
+ attribute \src "libresoc.v:201245.3-201246.29"
wire width 64 $0\src_r3[63:0]
- attribute \src "libresoc.v:200810.7-200810.24"
+ attribute \src "libresoc.v:200706.7-200706.24"
wire $1\all_rd_dly[0:0]
- attribute \src "libresoc.v:200820.7-200820.26"
+ attribute \src "libresoc.v:200716.7-200716.26"
wire $1\alu_done_dly[0:0]
- attribute \src "libresoc.v:201777.3-201785.6"
- wire $1\alu_l_r_alu$next[0:0]$14314
- attribute \src "libresoc.v:200828.7-200828.25"
+ attribute \src "libresoc.v:201673.3-201681.6"
+ wire $1\alu_l_r_alu$next[0:0]$14106
+ attribute \src "libresoc.v:200724.7-200724.25"
wire $1\alu_l_r_alu[0:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14248
- attribute \src "libresoc.v:200864.14-200864.59"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14040
+ attribute \src "libresoc.v:200760.14-200760.59"
wire width 64 $1\alu_trap0_trap_op__cia[63:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249
- attribute \src "libresoc.v:200883.14-200883.51"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041
+ attribute \src "libresoc.v:200779.14-200779.51"
wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14250
- attribute \src "libresoc.v:200887.14-200887.45"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14042
+ attribute \src "libresoc.v:200783.14-200783.45"
wire width 32 $1\alu_trap0_trap_op__insn[31:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251
- attribute \src "libresoc.v:200966.13-200966.49"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043
+ attribute \src "libresoc.v:200862.13-200862.49"
wire width 7 $1\alu_trap0_trap_op__insn_type[6:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252
- attribute \src "libresoc.v:200970.7-200970.41"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044
+ attribute \src "libresoc.v:200866.7-200866.41"
wire $1\alu_trap0_trap_op__is_32bit[0:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253
- attribute \src "libresoc.v:200974.13-200974.48"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045
+ attribute \src "libresoc.v:200870.13-200870.48"
wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14254
- attribute \src "libresoc.v:200978.14-200978.59"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14046
+ attribute \src "libresoc.v:200874.14-200874.59"
wire width 64 $1\alu_trap0_trap_op__msr[63:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255
- attribute \src "libresoc.v:200982.14-200982.52"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047
+ attribute \src "libresoc.v:200878.14-200878.52"
wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0]
- attribute \src "libresoc.v:201600.3-201617.6"
- wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14256
- attribute \src "libresoc.v:200986.13-200986.48"
+ attribute \src "libresoc.v:201496.3-201513.6"
+ wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14048
+ attribute \src "libresoc.v:200882.13-200882.48"
wire width 8 $1\alu_trap0_trap_op__traptype[7:0]
- attribute \src "libresoc.v:201768.3-201776.6"
- wire $1\alui_l_r_alui$next[0:0]$14311
- attribute \src "libresoc.v:200992.7-200992.27"
+ attribute \src "libresoc.v:201664.3-201672.6"
+ wire $1\alui_l_r_alui$next[0:0]$14103
+ attribute \src "libresoc.v:200888.7-200888.27"
wire $1\alui_l_r_alui[0:0]
- attribute \src "libresoc.v:201618.3-201639.6"
- wire width 64 $1\data_r0__o$next[63:0]$14260
- attribute \src "libresoc.v:201024.14-201024.47"
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire width 64 $1\data_r0__o$next[63:0]$14052
+ attribute \src "libresoc.v:200920.14-200920.47"
wire width 64 $1\data_r0__o[63:0]
- attribute \src "libresoc.v:201618.3-201639.6"
- wire $1\data_r0__o_ok$next[0:0]$14261
- attribute \src "libresoc.v:201028.7-201028.27"
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire $1\data_r0__o_ok$next[0:0]$14053
+ attribute \src "libresoc.v:200924.7-200924.27"
wire $1\data_r0__o_ok[0:0]
- attribute \src "libresoc.v:201640.3-201661.6"
- wire width 64 $1\data_r1__fast1$next[63:0]$14268
- attribute \src "libresoc.v:201032.14-201032.51"
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire width 64 $1\data_r1__fast1$next[63:0]$14060
+ attribute \src "libresoc.v:200928.14-200928.51"
wire width 64 $1\data_r1__fast1[63:0]
- attribute \src "libresoc.v:201640.3-201661.6"
- wire $1\data_r1__fast1_ok$next[0:0]$14269
- attribute \src "libresoc.v:201036.7-201036.31"
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire $1\data_r1__fast1_ok$next[0:0]$14061
+ attribute \src "libresoc.v:200932.7-200932.31"
wire $1\data_r1__fast1_ok[0:0]
- attribute \src "libresoc.v:201662.3-201683.6"
- wire width 64 $1\data_r2__fast2$next[63:0]$14276
- attribute \src "libresoc.v:201040.14-201040.51"
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire width 64 $1\data_r2__fast2$next[63:0]$14068
+ attribute \src "libresoc.v:200936.14-200936.51"
wire width 64 $1\data_r2__fast2[63:0]
- attribute \src "libresoc.v:201662.3-201683.6"
- wire $1\data_r2__fast2_ok$next[0:0]$14277
- attribute \src "libresoc.v:201044.7-201044.31"
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire $1\data_r2__fast2_ok$next[0:0]$14069
+ attribute \src "libresoc.v:200940.7-200940.31"
wire $1\data_r2__fast2_ok[0:0]
- attribute \src "libresoc.v:201684.3-201705.6"
- wire width 64 $1\data_r3__nia$next[63:0]$14284
- attribute \src "libresoc.v:201048.14-201048.49"
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire width 64 $1\data_r3__nia$next[63:0]$14076
+ attribute \src "libresoc.v:200944.14-200944.49"
wire width 64 $1\data_r3__nia[63:0]
- attribute \src "libresoc.v:201684.3-201705.6"
- wire $1\data_r3__nia_ok$next[0:0]$14285
- attribute \src "libresoc.v:201052.7-201052.29"
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire $1\data_r3__nia_ok$next[0:0]$14077
+ attribute \src "libresoc.v:200948.7-200948.29"
wire $1\data_r3__nia_ok[0:0]
- attribute \src "libresoc.v:201706.3-201727.6"
- wire width 64 $1\data_r4__msr$next[63:0]$14292
- attribute \src "libresoc.v:201056.14-201056.49"
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire width 64 $1\data_r4__msr$next[63:0]$14084
+ attribute \src "libresoc.v:200952.14-200952.49"
wire width 64 $1\data_r4__msr[63:0]
- attribute \src "libresoc.v:201706.3-201727.6"
- wire $1\data_r4__msr_ok$next[0:0]$14293
- attribute \src "libresoc.v:201060.7-201060.29"
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire $1\data_r4__msr_ok$next[0:0]$14085
+ attribute \src "libresoc.v:200956.7-200956.29"
wire $1\data_r4__msr_ok[0:0]
- attribute \src "libresoc.v:201786.3-201795.6"
+ attribute \src "libresoc.v:201682.3-201691.6"
wire width 64 $1\dest1_o[63:0]
- attribute \src "libresoc.v:201796.3-201805.6"
+ attribute \src "libresoc.v:201692.3-201701.6"
wire width 64 $1\dest2_o[63:0]
- attribute \src "libresoc.v:201806.3-201815.6"
+ attribute \src "libresoc.v:201702.3-201711.6"
wire width 64 $1\dest3_o[63:0]
- attribute \src "libresoc.v:201816.3-201825.6"
+ attribute \src "libresoc.v:201712.3-201721.6"
wire width 64 $1\dest4_o[63:0]
- attribute \src "libresoc.v:201826.3-201835.6"
+ attribute \src "libresoc.v:201722.3-201731.6"
wire width 64 $1\dest5_o[63:0]
- attribute \src "libresoc.v:201555.3-201563.6"
- wire $1\opc_l_r_opc$next[0:0]$14225
- attribute \src "libresoc.v:201091.7-201091.25"
+ attribute \src "libresoc.v:201451.3-201459.6"
+ wire $1\opc_l_r_opc$next[0:0]$14017
+ attribute \src "libresoc.v:200987.7-200987.25"
wire $1\opc_l_r_opc[0:0]
- attribute \src "libresoc.v:201546.3-201554.6"
- wire $1\opc_l_s_opc$next[0:0]$14222
- attribute \src "libresoc.v:201095.7-201095.25"
+ attribute \src "libresoc.v:201442.3-201450.6"
+ wire $1\opc_l_s_opc$next[0:0]$14014
+ attribute \src "libresoc.v:200991.7-200991.25"
wire $1\opc_l_s_opc[0:0]
- attribute \src "libresoc.v:201836.3-201844.6"
- wire width 5 $1\prev_wr_go$next[4:0]$14322
- attribute \src "libresoc.v:201207.13-201207.31"
+ attribute \src "libresoc.v:201732.3-201740.6"
+ wire width 5 $1\prev_wr_go$next[4:0]$14114
+ attribute \src "libresoc.v:201103.13-201103.31"
wire width 5 $1\prev_wr_go[4:0]
- attribute \src "libresoc.v:201500.3-201509.6"
+ attribute \src "libresoc.v:201396.3-201405.6"
wire $1\req_done[0:0]
- attribute \src "libresoc.v:201591.3-201599.6"
- wire width 5 $1\req_l_r_req$next[4:0]$14237
- attribute \src "libresoc.v:201215.13-201215.32"
+ attribute \src "libresoc.v:201487.3-201495.6"
+ wire width 5 $1\req_l_r_req$next[4:0]$14029
+ attribute \src "libresoc.v:201111.13-201111.32"
wire width 5 $1\req_l_r_req[4:0]
- attribute \src "libresoc.v:201582.3-201590.6"
- wire width 5 $1\req_l_s_req$next[4:0]$14234
- attribute \src "libresoc.v:201219.13-201219.32"
+ attribute \src "libresoc.v:201478.3-201486.6"
+ wire width 5 $1\req_l_s_req$next[4:0]$14026
+ attribute \src "libresoc.v:201115.13-201115.32"
wire width 5 $1\req_l_s_req[4:0]
- attribute \src "libresoc.v:201519.3-201527.6"
- wire $1\rok_l_r_rdok$next[0:0]$14213
- attribute \src "libresoc.v:201231.7-201231.26"
+ attribute \src "libresoc.v:201415.3-201423.6"
+ wire $1\rok_l_r_rdok$next[0:0]$14005
+ attribute \src "libresoc.v:201127.7-201127.26"
wire $1\rok_l_r_rdok[0:0]
- attribute \src "libresoc.v:201510.3-201518.6"
- wire $1\rok_l_s_rdok$next[0:0]$14210
- attribute \src "libresoc.v:201235.7-201235.26"
+ attribute \src "libresoc.v:201406.3-201414.6"
+ wire $1\rok_l_s_rdok$next[0:0]$14002
+ attribute \src "libresoc.v:201131.7-201131.26"
wire $1\rok_l_s_rdok[0:0]
- attribute \src "libresoc.v:201537.3-201545.6"
- wire $1\rst_l_r_rst$next[0:0]$14219
- attribute \src "libresoc.v:201239.7-201239.25"
+ attribute \src "libresoc.v:201433.3-201441.6"
+ wire $1\rst_l_r_rst$next[0:0]$14011
+ attribute \src "libresoc.v:201135.7-201135.25"
wire $1\rst_l_r_rst[0:0]
- attribute \src "libresoc.v:201528.3-201536.6"
- wire $1\rst_l_s_rst$next[0:0]$14216
- attribute \src "libresoc.v:201243.7-201243.25"
+ attribute \src "libresoc.v:201424.3-201432.6"
+ wire $1\rst_l_s_rst$next[0:0]$14008
+ attribute \src "libresoc.v:201139.7-201139.25"
wire $1\rst_l_s_rst[0:0]
- attribute \src "libresoc.v:201573.3-201581.6"
- wire width 4 $1\src_l_r_src$next[3:0]$14231
- attribute \src "libresoc.v:201259.13-201259.31"
+ attribute \src "libresoc.v:201469.3-201477.6"
+ wire width 4 $1\src_l_r_src$next[3:0]$14023
+ attribute \src "libresoc.v:201155.13-201155.31"
wire width 4 $1\src_l_r_src[3:0]
- attribute \src "libresoc.v:201564.3-201572.6"
- wire width 4 $1\src_l_s_src$next[3:0]$14228
- attribute \src "libresoc.v:201263.13-201263.31"
+ attribute \src "libresoc.v:201460.3-201468.6"
+ wire width 4 $1\src_l_s_src$next[3:0]$14020
+ attribute \src "libresoc.v:201159.13-201159.31"
wire width 4 $1\src_l_s_src[3:0]
- attribute \src "libresoc.v:201728.3-201737.6"
- wire width 64 $1\src_r0$next[63:0]$14299
- attribute \src "libresoc.v:201267.14-201267.43"
+ attribute \src "libresoc.v:201624.3-201633.6"
+ wire width 64 $1\src_r0$next[63:0]$14091
+ attribute \src "libresoc.v:201163.14-201163.43"
wire width 64 $1\src_r0[63:0]
- attribute \src "libresoc.v:201738.3-201747.6"
- wire width 64 $1\src_r1$next[63:0]$14302
- attribute \src "libresoc.v:201271.14-201271.43"
+ attribute \src "libresoc.v:201634.3-201643.6"
+ wire width 64 $1\src_r1$next[63:0]$14094
+ attribute \src "libresoc.v:201167.14-201167.43"
wire width 64 $1\src_r1[63:0]
- attribute \src "libresoc.v:201748.3-201757.6"
- wire width 64 $1\src_r2$next[63:0]$14305
- attribute \src "libresoc.v:201275.14-201275.43"
+ attribute \src "libresoc.v:201644.3-201653.6"
+ wire width 64 $1\src_r2$next[63:0]$14097
+ attribute \src "libresoc.v:201171.14-201171.43"
wire width 64 $1\src_r2[63:0]
- attribute \src "libresoc.v:201758.3-201767.6"
- wire width 64 $1\src_r3$next[63:0]$14308
- attribute \src "libresoc.v:201279.14-201279.43"
+ attribute \src "libresoc.v:201654.3-201663.6"
+ wire width 64 $1\src_r3$next[63:0]$14100
+ attribute \src "libresoc.v:201175.14-201175.43"
wire width 64 $1\src_r3[63:0]
- attribute \src "libresoc.v:201618.3-201639.6"
- wire width 64 $2\data_r0__o$next[63:0]$14262
- attribute \src "libresoc.v:201618.3-201639.6"
- wire $2\data_r0__o_ok$next[0:0]$14263
- attribute \src "libresoc.v:201640.3-201661.6"
- wire width 64 $2\data_r1__fast1$next[63:0]$14270
- attribute \src "libresoc.v:201640.3-201661.6"
- wire $2\data_r1__fast1_ok$next[0:0]$14271
- attribute \src "libresoc.v:201662.3-201683.6"
- wire width 64 $2\data_r2__fast2$next[63:0]$14278
- attribute \src "libresoc.v:201662.3-201683.6"
- wire $2\data_r2__fast2_ok$next[0:0]$14279
- attribute \src "libresoc.v:201684.3-201705.6"
- wire width 64 $2\data_r3__nia$next[63:0]$14286
- attribute \src "libresoc.v:201684.3-201705.6"
- wire $2\data_r3__nia_ok$next[0:0]$14287
- attribute \src "libresoc.v:201706.3-201727.6"
- wire width 64 $2\data_r4__msr$next[63:0]$14294
- attribute \src "libresoc.v:201706.3-201727.6"
- wire $2\data_r4__msr_ok$next[0:0]$14295
- attribute \src "libresoc.v:201618.3-201639.6"
- wire $3\data_r0__o_ok$next[0:0]$14264
- attribute \src "libresoc.v:201640.3-201661.6"
- wire $3\data_r1__fast1_ok$next[0:0]$14272
- attribute \src "libresoc.v:201662.3-201683.6"
- wire $3\data_r2__fast2_ok$next[0:0]$14280
- attribute \src "libresoc.v:201684.3-201705.6"
- wire $3\data_r3__nia_ok$next[0:0]$14288
- attribute \src "libresoc.v:201706.3-201727.6"
- wire $3\data_r4__msr_ok$next[0:0]$14296
- attribute \src "libresoc.v:201285.18-201285.112"
- wire width 4 $and$libresoc.v:201285$14109_Y
- attribute \src "libresoc.v:201286.19-201286.125"
- wire $and$libresoc.v:201286$14110_Y
- attribute \src "libresoc.v:201287.19-201287.125"
- wire $and$libresoc.v:201287$14111_Y
- attribute \src "libresoc.v:201288.19-201288.125"
- wire $and$libresoc.v:201288$14112_Y
- attribute \src "libresoc.v:201289.19-201289.125"
- wire $and$libresoc.v:201289$14113_Y
- attribute \src "libresoc.v:201290.19-201290.125"
- wire $and$libresoc.v:201290$14114_Y
- attribute \src "libresoc.v:201291.19-201291.157"
- wire width 5 $and$libresoc.v:201291$14115_Y
- attribute \src "libresoc.v:201292.19-201292.121"
- wire width 5 $and$libresoc.v:201292$14116_Y
- attribute \src "libresoc.v:201293.19-201293.127"
- wire $and$libresoc.v:201293$14117_Y
- attribute \src "libresoc.v:201294.19-201294.127"
- wire $and$libresoc.v:201294$14118_Y
- attribute \src "libresoc.v:201295.18-201295.110"
- wire $and$libresoc.v:201295$14119_Y
- attribute \src "libresoc.v:201296.19-201296.127"
- wire $and$libresoc.v:201296$14120_Y
- attribute \src "libresoc.v:201297.19-201297.127"
- wire $and$libresoc.v:201297$14121_Y
- attribute \src "libresoc.v:201298.19-201298.127"
- wire $and$libresoc.v:201298$14122_Y
- attribute \src "libresoc.v:201300.18-201300.98"
- wire $and$libresoc.v:201300$14124_Y
- attribute \src "libresoc.v:201302.18-201302.100"
- wire $and$libresoc.v:201302$14126_Y
- attribute \src "libresoc.v:201303.18-201303.171"
- wire width 5 $and$libresoc.v:201303$14127_Y
- attribute \src "libresoc.v:201305.18-201305.119"
- wire width 5 $and$libresoc.v:201305$14129_Y
- attribute \src "libresoc.v:201308.18-201308.116"
- wire $and$libresoc.v:201308$14132_Y
- attribute \src "libresoc.v:201312.17-201312.123"
- wire $and$libresoc.v:201312$14136_Y
- attribute \src "libresoc.v:201314.18-201314.113"
- wire $and$libresoc.v:201314$14138_Y
- attribute \src "libresoc.v:201315.18-201315.125"
- wire width 5 $and$libresoc.v:201315$14139_Y
- attribute \src "libresoc.v:201317.18-201317.112"
- wire $and$libresoc.v:201317$14141_Y
- attribute \src "libresoc.v:201319.18-201319.127"
- wire $and$libresoc.v:201319$14143_Y
- attribute \src "libresoc.v:201320.18-201320.127"
- wire $and$libresoc.v:201320$14144_Y
- attribute \src "libresoc.v:201321.18-201321.117"
- wire $and$libresoc.v:201321$14145_Y
- attribute \src "libresoc.v:201326.18-201326.131"
- wire $and$libresoc.v:201326$14150_Y
- attribute \src "libresoc.v:201327.18-201327.124"
- wire width 5 $and$libresoc.v:201327$14151_Y
- attribute \src "libresoc.v:201330.18-201330.116"
- wire $and$libresoc.v:201330$14154_Y
- attribute \src "libresoc.v:201331.18-201331.120"
- wire $and$libresoc.v:201331$14155_Y
- attribute \src "libresoc.v:201332.18-201332.120"
- wire $and$libresoc.v:201332$14156_Y
- attribute \src "libresoc.v:201333.18-201333.118"
- wire $and$libresoc.v:201333$14157_Y
- attribute \src "libresoc.v:201334.18-201334.118"
- wire $and$libresoc.v:201334$14158_Y
- attribute \src "libresoc.v:201340.18-201340.135"
- wire $and$libresoc.v:201340$14164_Y
- attribute \src "libresoc.v:201341.18-201341.133"
- wire $and$libresoc.v:201341$14165_Y
- attribute \src "libresoc.v:201342.18-201342.160"
- wire width 4 $and$libresoc.v:201342$14166_Y
- attribute \src "libresoc.v:201343.18-201343.112"
- wire width 4 $and$libresoc.v:201343$14167_Y
- attribute \src "libresoc.v:201316.18-201316.113"
- wire $eq$libresoc.v:201316$14140_Y
- attribute \src "libresoc.v:201318.18-201318.119"
- wire $eq$libresoc.v:201318$14142_Y
- attribute \src "libresoc.v:201299.18-201299.97"
- wire $not$libresoc.v:201299$14123_Y
- attribute \src "libresoc.v:201301.18-201301.99"
- wire $not$libresoc.v:201301$14125_Y
- attribute \src "libresoc.v:201304.18-201304.113"
- wire width 5 $not$libresoc.v:201304$14128_Y
- attribute \src "libresoc.v:201307.18-201307.106"
- wire $not$libresoc.v:201307$14131_Y
- attribute \src "libresoc.v:201313.18-201313.121"
- wire $not$libresoc.v:201313$14137_Y
- attribute \src "libresoc.v:201328.17-201328.113"
- wire width 4 $not$libresoc.v:201328$14152_Y
- attribute \src "libresoc.v:201344.18-201344.114"
- wire width 4 $not$libresoc.v:201344$14168_Y
- attribute \src "libresoc.v:201311.18-201311.112"
- wire $or$libresoc.v:201311$14135_Y
- attribute \src "libresoc.v:201322.18-201322.122"
- wire $or$libresoc.v:201322$14146_Y
- attribute \src "libresoc.v:201323.18-201323.124"
- wire $or$libresoc.v:201323$14147_Y
- attribute \src "libresoc.v:201324.18-201324.181"
- wire width 5 $or$libresoc.v:201324$14148_Y
- attribute \src "libresoc.v:201325.18-201325.168"
- wire width 4 $or$libresoc.v:201325$14149_Y
- attribute \src "libresoc.v:201329.18-201329.120"
- wire width 5 $or$libresoc.v:201329$14153_Y
- attribute \src "libresoc.v:201339.17-201339.117"
- wire width 4 $or$libresoc.v:201339$14163_Y
- attribute \src "libresoc.v:201284.17-201284.104"
- wire $reduce_and$libresoc.v:201284$14108_Y
- attribute \src "libresoc.v:201306.18-201306.106"
- wire $reduce_or$libresoc.v:201306$14130_Y
- attribute \src "libresoc.v:201309.18-201309.113"
- wire $reduce_or$libresoc.v:201309$14133_Y
- attribute \src "libresoc.v:201310.18-201310.112"
- wire $reduce_or$libresoc.v:201310$14134_Y
- attribute \src "libresoc.v:201335.18-201335.118"
- wire width 64 $ternary$libresoc.v:201335$14159_Y
- attribute \src "libresoc.v:201336.18-201336.118"
- wire width 64 $ternary$libresoc.v:201336$14160_Y
- attribute \src "libresoc.v:201337.18-201337.118"
- wire width 64 $ternary$libresoc.v:201337$14161_Y
- attribute \src "libresoc.v:201338.18-201338.118"
- wire width 64 $ternary$libresoc.v:201338$14162_Y
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire width 64 $2\data_r0__o$next[63:0]$14054
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire $2\data_r0__o_ok$next[0:0]$14055
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire width 64 $2\data_r1__fast1$next[63:0]$14062
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire $2\data_r1__fast1_ok$next[0:0]$14063
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire width 64 $2\data_r2__fast2$next[63:0]$14070
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire $2\data_r2__fast2_ok$next[0:0]$14071
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire width 64 $2\data_r3__nia$next[63:0]$14078
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire $2\data_r3__nia_ok$next[0:0]$14079
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire width 64 $2\data_r4__msr$next[63:0]$14086
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire $2\data_r4__msr_ok$next[0:0]$14087
+ attribute \src "libresoc.v:201514.3-201535.6"
+ wire $3\data_r0__o_ok$next[0:0]$14056
+ attribute \src "libresoc.v:201536.3-201557.6"
+ wire $3\data_r1__fast1_ok$next[0:0]$14064
+ attribute \src "libresoc.v:201558.3-201579.6"
+ wire $3\data_r2__fast2_ok$next[0:0]$14072
+ attribute \src "libresoc.v:201580.3-201601.6"
+ wire $3\data_r3__nia_ok$next[0:0]$14080
+ attribute \src "libresoc.v:201602.3-201623.6"
+ wire $3\data_r4__msr_ok$next[0:0]$14088
+ attribute \src "libresoc.v:201181.18-201181.112"
+ wire width 4 $and$libresoc.v:201181$13901_Y
+ attribute \src "libresoc.v:201182.19-201182.125"
+ wire $and$libresoc.v:201182$13902_Y
+ attribute \src "libresoc.v:201183.19-201183.125"
+ wire $and$libresoc.v:201183$13903_Y
+ attribute \src "libresoc.v:201184.19-201184.125"
+ wire $and$libresoc.v:201184$13904_Y
+ attribute \src "libresoc.v:201185.19-201185.125"
+ wire $and$libresoc.v:201185$13905_Y
+ attribute \src "libresoc.v:201186.19-201186.125"
+ wire $and$libresoc.v:201186$13906_Y
+ attribute \src "libresoc.v:201187.19-201187.157"
+ wire width 5 $and$libresoc.v:201187$13907_Y
+ attribute \src "libresoc.v:201188.19-201188.121"
+ wire width 5 $and$libresoc.v:201188$13908_Y
+ attribute \src "libresoc.v:201189.19-201189.127"
+ wire $and$libresoc.v:201189$13909_Y
+ attribute \src "libresoc.v:201190.19-201190.127"
+ wire $and$libresoc.v:201190$13910_Y
+ attribute \src "libresoc.v:201191.18-201191.110"
+ wire $and$libresoc.v:201191$13911_Y
+ attribute \src "libresoc.v:201192.19-201192.127"
+ wire $and$libresoc.v:201192$13912_Y
+ attribute \src "libresoc.v:201193.19-201193.127"
+ wire $and$libresoc.v:201193$13913_Y
+ attribute \src "libresoc.v:201194.19-201194.127"
+ wire $and$libresoc.v:201194$13914_Y
+ attribute \src "libresoc.v:201196.18-201196.98"
+ wire $and$libresoc.v:201196$13916_Y
+ attribute \src "libresoc.v:201198.18-201198.100"
+ wire $and$libresoc.v:201198$13918_Y
+ attribute \src "libresoc.v:201199.18-201199.171"
+ wire width 5 $and$libresoc.v:201199$13919_Y
+ attribute \src "libresoc.v:201201.18-201201.119"
+ wire width 5 $and$libresoc.v:201201$13921_Y
+ attribute \src "libresoc.v:201204.18-201204.116"
+ wire $and$libresoc.v:201204$13924_Y
+ attribute \src "libresoc.v:201208.17-201208.123"
+ wire $and$libresoc.v:201208$13928_Y
+ attribute \src "libresoc.v:201210.18-201210.113"
+ wire $and$libresoc.v:201210$13930_Y
+ attribute \src "libresoc.v:201211.18-201211.125"
+ wire width 5 $and$libresoc.v:201211$13931_Y
+ attribute \src "libresoc.v:201213.18-201213.112"
+ wire $and$libresoc.v:201213$13933_Y
+ attribute \src "libresoc.v:201215.18-201215.127"
+ wire $and$libresoc.v:201215$13935_Y
+ attribute \src "libresoc.v:201216.18-201216.127"
+ wire $and$libresoc.v:201216$13936_Y
+ attribute \src "libresoc.v:201217.18-201217.117"
+ wire $and$libresoc.v:201217$13937_Y
+ attribute \src "libresoc.v:201222.18-201222.131"
+ wire $and$libresoc.v:201222$13942_Y
+ attribute \src "libresoc.v:201223.18-201223.124"
+ wire width 5 $and$libresoc.v:201223$13943_Y
+ attribute \src "libresoc.v:201226.18-201226.116"
+ wire $and$libresoc.v:201226$13946_Y
+ attribute \src "libresoc.v:201227.18-201227.120"
+ wire $and$libresoc.v:201227$13947_Y
+ attribute \src "libresoc.v:201228.18-201228.120"
+ wire $and$libresoc.v:201228$13948_Y
+ attribute \src "libresoc.v:201229.18-201229.118"
+ wire $and$libresoc.v:201229$13949_Y
+ attribute \src "libresoc.v:201230.18-201230.118"
+ wire $and$libresoc.v:201230$13950_Y
+ attribute \src "libresoc.v:201236.18-201236.135"
+ wire $and$libresoc.v:201236$13956_Y
+ attribute \src "libresoc.v:201237.18-201237.133"
+ wire $and$libresoc.v:201237$13957_Y
+ attribute \src "libresoc.v:201238.18-201238.160"
+ wire width 4 $and$libresoc.v:201238$13958_Y
+ attribute \src "libresoc.v:201239.18-201239.112"
+ wire width 4 $and$libresoc.v:201239$13959_Y
+ attribute \src "libresoc.v:201212.18-201212.113"
+ wire $eq$libresoc.v:201212$13932_Y
+ attribute \src "libresoc.v:201214.18-201214.119"
+ wire $eq$libresoc.v:201214$13934_Y
+ attribute \src "libresoc.v:201195.18-201195.97"
+ wire $not$libresoc.v:201195$13915_Y
+ attribute \src "libresoc.v:201197.18-201197.99"
+ wire $not$libresoc.v:201197$13917_Y
+ attribute \src "libresoc.v:201200.18-201200.113"
+ wire width 5 $not$libresoc.v:201200$13920_Y
+ attribute \src "libresoc.v:201203.18-201203.106"
+ wire $not$libresoc.v:201203$13923_Y
+ attribute \src "libresoc.v:201209.18-201209.121"
+ wire $not$libresoc.v:201209$13929_Y
+ attribute \src "libresoc.v:201224.17-201224.113"
+ wire width 4 $not$libresoc.v:201224$13944_Y
+ attribute \src "libresoc.v:201240.18-201240.114"
+ wire width 4 $not$libresoc.v:201240$13960_Y
+ attribute \src "libresoc.v:201207.18-201207.112"
+ wire $or$libresoc.v:201207$13927_Y
+ attribute \src "libresoc.v:201218.18-201218.122"
+ wire $or$libresoc.v:201218$13938_Y
+ attribute \src "libresoc.v:201219.18-201219.124"
+ wire $or$libresoc.v:201219$13939_Y
+ attribute \src "libresoc.v:201220.18-201220.181"
+ wire width 5 $or$libresoc.v:201220$13940_Y
+ attribute \src "libresoc.v:201221.18-201221.168"
+ wire width 4 $or$libresoc.v:201221$13941_Y
+ attribute \src "libresoc.v:201225.18-201225.120"
+ wire width 5 $or$libresoc.v:201225$13945_Y
+ attribute \src "libresoc.v:201235.17-201235.117"
+ wire width 4 $or$libresoc.v:201235$13955_Y
+ attribute \src "libresoc.v:201180.17-201180.104"
+ wire $reduce_and$libresoc.v:201180$13900_Y
+ attribute \src "libresoc.v:201202.18-201202.106"
+ wire $reduce_or$libresoc.v:201202$13922_Y
+ attribute \src "libresoc.v:201205.18-201205.113"
+ wire $reduce_or$libresoc.v:201205$13925_Y
+ attribute \src "libresoc.v:201206.18-201206.112"
+ wire $reduce_or$libresoc.v:201206$13926_Y
+ attribute \src "libresoc.v:201231.18-201231.118"
+ wire width 64 $ternary$libresoc.v:201231$13951_Y
+ attribute \src "libresoc.v:201232.18-201232.118"
+ wire width 64 $ternary$libresoc.v:201232$13952_Y
+ attribute \src "libresoc.v:201233.18-201233.118"
+ wire width 64 $ternary$libresoc.v:201233$13953_Y
+ attribute \src "libresoc.v:201234.18-201234.118"
+ wire width 64 $ternary$libresoc.v:201234$13954_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
wire \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 5 \alu_pulsem
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_trap0_fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_trap0_fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_trap0_fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
wire width 64 \alu_trap0_fast2$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_trap0_msr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253"
wire \alu_trap0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252"
wire \alu_trap0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_trap0_nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire width 64 \alu_trap0_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160"
wire \alu_trap0_p_ready_o
wire \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire \alui_l_s_alui
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 32 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
wire output 12 \cu_busy_o
wire width 64 output 29 \dest4_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84"
wire width 64 output 31 \dest5_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 24 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 25 \fast2_ok
- attribute \src "libresoc.v:200684.7-200684.15"
+ attribute \src "libresoc.v:200580.7-200580.15"
wire \initial
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 30 \msr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 28 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19"
wire output 20 \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire \opc_l_q_opc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:201285$14109
+ cell $and $and$libresoc.v:201181$13901
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:201285$14109_Y
+ connect \Y $and$libresoc.v:201181$13901_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:201286$14110
+ cell $and $and$libresoc.v:201182$13902
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:201286$14110_Y
+ connect \Y $and$libresoc.v:201182$13902_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:201287$14111
+ cell $and $and$libresoc.v:201183$13903
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:201287$14111_Y
+ connect \Y $and$libresoc.v:201183$13903_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:201288$14112
+ cell $and $and$libresoc.v:201184$13904
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:201288$14112_Y
+ connect \Y $and$libresoc.v:201184$13904_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:201289$14113
+ cell $and $and$libresoc.v:201185$13905
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:201289$14113_Y
+ connect \Y $and$libresoc.v:201185$13905_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350"
- cell $and $and$libresoc.v:201290$14114
+ cell $and $and$libresoc.v:201186$13906
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \cu_shadown_i
- connect \Y $and$libresoc.v:201290$14114_Y
+ connect \Y $and$libresoc.v:201186$13906_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:201291$14115
+ cell $and $and$libresoc.v:201187$13907
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B { \$101 \$103 \$105 \$107 \$109 }
- connect \Y $and$libresoc.v:201291$14115_Y
+ connect \Y $and$libresoc.v:201187$13907_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351"
- cell $and $and$libresoc.v:201292$14116
+ cell $and $and$libresoc.v:201188$13908
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \$111
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:201292$14116_Y
+ connect \Y $and$libresoc.v:201188$13908_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:201293$14117
+ cell $and $and$libresoc.v:201189$13909
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [0]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201293$14117_Y
+ connect \Y $and$libresoc.v:201189$13909_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:201294$14118
+ cell $and $and$libresoc.v:201190$13910
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [1]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201294$14118_Y
+ connect \Y $and$libresoc.v:201190$13910_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $and $and$libresoc.v:201295$14119
+ cell $and $and$libresoc.v:201191$13911
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \$5
- connect \Y $and$libresoc.v:201295$14119_Y
+ connect \Y $and$libresoc.v:201191$13911_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:201296$14120
+ cell $and $and$libresoc.v:201192$13912
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [2]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201296$14120_Y
+ connect \Y $and$libresoc.v:201192$13912_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:201297$14121
+ cell $and $and$libresoc.v:201193$13913
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [3]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201297$14121_Y
+ connect \Y $and$libresoc.v:201193$13913_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355"
- cell $and $and$libresoc.v:201298$14122
+ cell $and $and$libresoc.v:201194$13914
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i [4]
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201298$14122_Y
+ connect \Y $and$libresoc.v:201194$13914_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:201300$14124
+ cell $and $and$libresoc.v:201196$13916
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \all_rd
connect \B \$13
- connect \Y $and$libresoc.v:201300$14124_Y
+ connect \Y $and$libresoc.v:201196$13916_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $and $and$libresoc.v:201302$14126
+ cell $and $and$libresoc.v:201198$13918
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_done
connect \B \$17
- connect \Y $and$libresoc.v:201302$14126_Y
+ connect \Y $and$libresoc.v:201198$13918_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
- cell $and $and$libresoc.v:201303$14127
+ cell $and $and$libresoc.v:201199$13919
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:201303$14127_Y
+ connect \Y $and$libresoc.v:201199$13919_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:201305$14129
+ cell $and $and$libresoc.v:201201$13921
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__rel_o
connect \B \$25
- connect \Y $and$libresoc.v:201305$14129_Y
+ connect \Y $and$libresoc.v:201201$13921_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $and $and$libresoc.v:201308$14132
+ cell $and $and$libresoc.v:201204$13924
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \$23
- connect \Y $and$libresoc.v:201308$14132_Y
+ connect \Y $and$libresoc.v:201204$13924_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
- cell $and $and$libresoc.v:201312$14136
+ cell $and $and$libresoc.v:201208$13928
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_busy_o
connect \B \rok_l_q_rdok
- connect \Y $and$libresoc.v:201312$14136_Y
+ connect \Y $and$libresoc.v:201208$13928_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $and $and$libresoc.v:201314$14138
+ cell $and $and$libresoc.v:201210$13930
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr_any
connect \B \$39
- connect \Y $and$libresoc.v:201314$14138_Y
+ connect \Y $and$libresoc.v:201210$13930_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:201315$14139
+ cell $and $and$libresoc.v:201211$13931
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:201315$14139_Y
+ connect \Y $and$libresoc.v:201211$13931_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $and$libresoc.v:201317$14141
+ cell $and $and$libresoc.v:201213$13933
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$41
connect \B \$45
- connect \Y $and$libresoc.v:201317$14141_Y
+ connect \Y $and$libresoc.v:201213$13933_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:201319$14143
+ cell $and $and$libresoc.v:201215$13935
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$49
connect \B \alu_trap0_n_ready_i
- connect \Y $and$libresoc.v:201319$14143_Y
+ connect \Y $and$libresoc.v:201215$13935_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:201320$14144
+ cell $and $and$libresoc.v:201216$13936
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$51
connect \B \alu_trap0_n_valid_o
- connect \Y $and$libresoc.v:201320$14144_Y
+ connect \Y $and$libresoc.v:201216$13936_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $and $and$libresoc.v:201321$14145
+ cell $and $and$libresoc.v:201217$13937
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$53
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201321$14145_Y
+ connect \Y $and$libresoc.v:201217$13937_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237"
- cell $and $and$libresoc.v:201326$14150
+ cell $and $and$libresoc.v:201222$13942
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201326$14150_Y
+ connect \Y $and$libresoc.v:201222$13942_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252"
- cell $and $and$libresoc.v:201327$14151
+ cell $and $and$libresoc.v:201223$13943
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \alu_pulsem
connect \B \cu_wrmask_o
- connect \Y $and$libresoc.v:201327$14151_Y
+ connect \Y $and$libresoc.v:201223$13943_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:201330$14154
+ cell $and $and$libresoc.v:201226$13946
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \o_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201330$14154_Y
+ connect \Y $and$libresoc.v:201226$13946_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:201331$14155
+ cell $and $and$libresoc.v:201227$13947
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast1_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201331$14155_Y
+ connect \Y $and$libresoc.v:201227$13947_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:201332$14156
+ cell $and $and$libresoc.v:201228$13948
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \fast2_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201332$14156_Y
+ connect \Y $and$libresoc.v:201228$13948_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:201333$14157
+ cell $and $and$libresoc.v:201229$13949
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \nia_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201333$14157_Y
+ connect \Y $and$libresoc.v:201229$13949_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276"
- cell $and $and$libresoc.v:201334$14158
+ cell $and $and$libresoc.v:201230$13950
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \msr_ok
connect \B \cu_busy_o
- connect \Y $and$libresoc.v:201334$14158_Y
+ connect \Y $and$libresoc.v:201230$13950_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
- cell $and $and$libresoc.v:201340$14164
+ cell $and $and$libresoc.v:201236$13956
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $and$libresoc.v:201340$14164_Y
+ connect \Y $and$libresoc.v:201236$13956_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334"
- cell $and $and$libresoc.v:201341$14165
+ cell $and $and$libresoc.v:201237$13957
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $and$libresoc.v:201341$14165_Y
+ connect \Y $and$libresoc.v:201237$13957_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:201342$14166
+ cell $and $and$libresoc.v:201238$13958
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \src_l_q_src
connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
- connect \Y $and$libresoc.v:201342$14166_Y
+ connect \Y $and$libresoc.v:201238$13958_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $and $and$libresoc.v:201343$14167
+ cell $and $and$libresoc.v:201239$13959
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$93
connect \B 4'1111
- connect \Y $and$libresoc.v:201343$14167_Y
+ connect \Y $and$libresoc.v:201239$13959_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $eq$libresoc.v:201316$14140
+ cell $eq $eq$libresoc.v:201212$13932
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$43
connect \B 1'0
- connect \Y $eq$libresoc.v:201316$14140_Y
+ connect \Y $eq$libresoc.v:201212$13932_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
- cell $eq $eq$libresoc.v:201318$14142
+ cell $eq $eq$libresoc.v:201214$13934
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_wrmask_o
connect \B 1'0
- connect \Y $eq$libresoc.v:201318$14142_Y
+ connect \Y $eq$libresoc.v:201214$13934_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:201299$14123
+ cell $not $not$libresoc.v:201195$13915
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $not$libresoc.v:201299$14123_Y
+ connect \Y $not$libresoc.v:201195$13915_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65"
- cell $not $not$libresoc.v:201301$14125
+ cell $not $not$libresoc.v:201197$13917
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $not$libresoc.v:201301$14125_Y
+ connect \Y $not$libresoc.v:201197$13917_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:201304$14128
+ cell $not $not$libresoc.v:201200$13920
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \cu_wrmask_o
- connect \Y $not$libresoc.v:201304$14128_Y
+ connect \Y $not$libresoc.v:201200$13920_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $not $not$libresoc.v:201307$14131
+ cell $not $not$libresoc.v:201203$13923
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:201307$14131_Y
+ connect \Y $not$libresoc.v:201203$13923_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
- cell $not $not$libresoc.v:201313$14137
+ cell $not $not$libresoc.v:201209$13929
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_ready_i
- connect \Y $not$libresoc.v:201313$14137_Y
+ connect \Y $not$libresoc.v:201209$13929_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $not $not$libresoc.v:201328$14152
+ cell $not $not$libresoc.v:201224$13944
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rd__rel_o
- connect \Y $not$libresoc.v:201328$14152_Y
+ connect \Y $not$libresoc.v:201224$13944_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347"
- cell $not $not$libresoc.v:201344$14168
+ cell $not $not$libresoc.v:201240$13960
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \cu_rdmaskn_i
- connect \Y $not$libresoc.v:201344$14168_Y
+ connect \Y $not$libresoc.v:201240$13960_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $or $or$libresoc.v:201311$14135
+ cell $or $or$libresoc.v:201207$13927
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$33
connect \B \$35
- connect \Y $or$libresoc.v:201311$14135_Y
+ connect \Y $or$libresoc.v:201207$13927_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
- cell $or $or$libresoc.v:201322$14146
+ cell $or $or$libresoc.v:201218$13938
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:201322$14146_Y
+ connect \Y $or$libresoc.v:201218$13938_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
- cell $or $or$libresoc.v:201323$14147
+ cell $or $or$libresoc.v:201219$13939
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_issue_i
connect \B \cu_go_die_i
- connect \Y $or$libresoc.v:201323$14147_Y
+ connect \Y $or$libresoc.v:201219$13939_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $or $or$libresoc.v:201324$14148
+ cell $or $or$libresoc.v:201220$13940
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \cu_wr__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:201324$14148_Y
+ connect \Y $or$libresoc.v:201220$13940_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
- cell $or $or$libresoc.v:201325$14149
+ cell $or $or$libresoc.v:201221$13941
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \cu_rd__go_i
connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
- connect \Y $or$libresoc.v:201325$14149_Y
+ connect \Y $or$libresoc.v:201221$13941_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253"
- cell $or $or$libresoc.v:201329$14153
+ cell $or $or$libresoc.v:201225$13945
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $or$libresoc.v:201329$14153_Y
+ connect \Y $or$libresoc.v:201225$13945_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $or $or$libresoc.v:201339$14163
+ cell $or $or$libresoc.v:201235$13955
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \$6
connect \B \cu_rd__go_i
- connect \Y $or$libresoc.v:201339$14163_Y
+ connect \Y $or$libresoc.v:201235$13955_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
- cell $reduce_and $reduce_and$libresoc.v:201284$14108
+ cell $reduce_and $reduce_and$libresoc.v:201180$13900
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $reduce_and$libresoc.v:201284$14108_Y
+ connect \Y $reduce_and$libresoc.v:201180$13900_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
- cell $reduce_or $reduce_or$libresoc.v:201306$14130
+ cell $reduce_or $reduce_or$libresoc.v:201202$13922
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \$27
- connect \Y $reduce_or$libresoc.v:201306$14130_Y
+ connect \Y $reduce_or$libresoc.v:201202$13922_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:201309$14133
+ cell $reduce_or $reduce_or$libresoc.v:201205$13925
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \cu_wr__go_i
- connect \Y $reduce_or$libresoc.v:201309$14133_Y
+ connect \Y $reduce_or$libresoc.v:201205$13925_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
- cell $reduce_or $reduce_or$libresoc.v:201310$14134
+ cell $reduce_or $reduce_or$libresoc.v:201206$13926
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $reduce_or$libresoc.v:201310$14134_Y
+ connect \Y $reduce_or$libresoc.v:201206$13926_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:201335$14159
+ cell $mux $ternary$libresoc.v:201231$13951
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $ternary$libresoc.v:201335$14159_Y
+ connect \Y $ternary$libresoc.v:201231$13951_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:201336$14160
+ cell $mux $ternary$libresoc.v:201232$13952
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $ternary$libresoc.v:201336$14160_Y
+ connect \Y $ternary$libresoc.v:201232$13952_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:201337$14161
+ cell $mux $ternary$libresoc.v:201233$13953
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $ternary$libresoc.v:201337$14161_Y
+ connect \Y $ternary$libresoc.v:201233$13953_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47"
- cell $mux $ternary$libresoc.v:201338$14162
+ cell $mux $ternary$libresoc.v:201234$13954
parameter \WIDTH 64
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $ternary$libresoc.v:201338$14162_Y
+ connect \Y $ternary$libresoc.v:201234$13954_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201421.14-201427.4"
+ attribute \src "libresoc.v:201317.14-201323.4"
cell \alu_l$45 \alu_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alu \alu_l_s_alu
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201428.13-201458.4"
+ attribute \src "libresoc.v:201324.13-201354.4"
cell \alu_trap0 \alu_trap0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \trap_op__traptype \alu_trap0_trap_op__traptype
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201459.15-201465.4"
+ attribute \src "libresoc.v:201355.15-201361.4"
cell \alui_l$44 \alui_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_alui \alui_l_s_alui
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201466.14-201472.4"
+ attribute \src "libresoc.v:201362.14-201368.4"
cell \opc_l$40 \opc_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_opc \opc_l_s_opc
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201473.14-201479.4"
+ attribute \src "libresoc.v:201369.14-201375.4"
cell \req_l$41 \req_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_req \req_l_s_req
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201480.14-201486.4"
+ attribute \src "libresoc.v:201376.14-201382.4"
cell \rok_l$43 \rok_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rdok \rok_l_s_rdok
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201487.14-201492.4"
+ attribute \src "libresoc.v:201383.14-201388.4"
cell \rst_l$42 \rst_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \s_rst \rst_l_s_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:201493.14-201499.4"
+ attribute \src "libresoc.v:201389.14-201395.4"
cell \src_l$39 \src_l
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \r_src \src_l_r_src
connect \s_src \src_l_s_src
end
- attribute \src "libresoc.v:200684.7-200684.20"
- process $proc$libresoc.v:200684$14323
+ attribute \src "libresoc.v:200580.7-200580.20"
+ process $proc$libresoc.v:200580$14115
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:200810.7-200810.24"
- process $proc$libresoc.v:200810$14324
+ attribute \src "libresoc.v:200706.7-200706.24"
+ process $proc$libresoc.v:200706$14116
assign { } { }
assign $1\all_rd_dly[0:0] 1'0
sync always
sync init
update \all_rd_dly $1\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:200820.7-200820.26"
- process $proc$libresoc.v:200820$14325
+ attribute \src "libresoc.v:200716.7-200716.26"
+ process $proc$libresoc.v:200716$14117
assign { } { }
assign $1\alu_done_dly[0:0] 1'0
sync always
sync init
update \alu_done_dly $1\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:200828.7-200828.25"
- process $proc$libresoc.v:200828$14326
+ attribute \src "libresoc.v:200724.7-200724.25"
+ process $proc$libresoc.v:200724$14118
assign { } { }
assign $1\alu_l_r_alu[0:0] 1'1
sync always
sync init
update \alu_l_r_alu $1\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:200864.14-200864.59"
- process $proc$libresoc.v:200864$14327
+ attribute \src "libresoc.v:200760.14-200760.59"
+ process $proc$libresoc.v:200760$14119
assign { } { }
assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:200883.14-200883.51"
- process $proc$libresoc.v:200883$14328
+ attribute \src "libresoc.v:200779.14-200779.51"
+ process $proc$libresoc.v:200779$14120
assign { } { }
assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000
sync always
sync init
update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:200887.14-200887.45"
- process $proc$libresoc.v:200887$14329
+ attribute \src "libresoc.v:200783.14-200783.45"
+ process $proc$libresoc.v:200783$14121
assign { } { }
assign $1\alu_trap0_trap_op__insn[31:0] 0
sync always
sync init
update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:200966.13-200966.49"
- process $proc$libresoc.v:200966$14330
+ attribute \src "libresoc.v:200862.13-200862.49"
+ process $proc$libresoc.v:200862$14122
assign { } { }
assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000
sync always
sync init
update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:200970.7-200970.41"
- process $proc$libresoc.v:200970$14331
+ attribute \src "libresoc.v:200866.7-200866.41"
+ process $proc$libresoc.v:200866$14123
assign { } { }
assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0
sync always
sync init
update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:200974.13-200974.48"
- process $proc$libresoc.v:200974$14332
+ attribute \src "libresoc.v:200870.13-200870.48"
+ process $proc$libresoc.v:200870$14124
assign { } { }
assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:200978.14-200978.59"
- process $proc$libresoc.v:200978$14333
+ attribute \src "libresoc.v:200874.14-200874.59"
+ process $proc$libresoc.v:200874$14125
assign { } { }
assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:200982.14-200982.52"
- process $proc$libresoc.v:200982$14334
+ attribute \src "libresoc.v:200878.14-200878.52"
+ process $proc$libresoc.v:200878$14126
assign { } { }
assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000
sync always
sync init
update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:200986.13-200986.48"
- process $proc$libresoc.v:200986$14335
+ attribute \src "libresoc.v:200882.13-200882.48"
+ process $proc$libresoc.v:200882$14127
assign { } { }
assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000
sync always
sync init
update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:200992.7-200992.27"
- process $proc$libresoc.v:200992$14336
+ attribute \src "libresoc.v:200888.7-200888.27"
+ process $proc$libresoc.v:200888$14128
assign { } { }
assign $1\alui_l_r_alui[0:0] 1'1
sync always
sync init
update \alui_l_r_alui $1\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:201024.14-201024.47"
- process $proc$libresoc.v:201024$14337
+ attribute \src "libresoc.v:200920.14-200920.47"
+ process $proc$libresoc.v:200920$14129
assign { } { }
assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r0__o $1\data_r0__o[63:0]
end
- attribute \src "libresoc.v:201028.7-201028.27"
- process $proc$libresoc.v:201028$14338
+ attribute \src "libresoc.v:200924.7-200924.27"
+ process $proc$libresoc.v:200924$14130
assign { } { }
assign $1\data_r0__o_ok[0:0] 1'0
sync always
sync init
update \data_r0__o_ok $1\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:201032.14-201032.51"
- process $proc$libresoc.v:201032$14339
+ attribute \src "libresoc.v:200928.14-200928.51"
+ process $proc$libresoc.v:200928$14131
assign { } { }
assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r1__fast1 $1\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:201036.7-201036.31"
- process $proc$libresoc.v:201036$14340
+ attribute \src "libresoc.v:200932.7-200932.31"
+ process $proc$libresoc.v:200932$14132
assign { } { }
assign $1\data_r1__fast1_ok[0:0] 1'0
sync always
sync init
update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:201040.14-201040.51"
- process $proc$libresoc.v:201040$14341
+ attribute \src "libresoc.v:200936.14-200936.51"
+ process $proc$libresoc.v:200936$14133
assign { } { }
assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r2__fast2 $1\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:201044.7-201044.31"
- process $proc$libresoc.v:201044$14342
+ attribute \src "libresoc.v:200940.7-200940.31"
+ process $proc$libresoc.v:200940$14134
assign { } { }
assign $1\data_r2__fast2_ok[0:0] 1'0
sync always
sync init
update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:201048.14-201048.49"
- process $proc$libresoc.v:201048$14343
+ attribute \src "libresoc.v:200944.14-200944.49"
+ process $proc$libresoc.v:200944$14135
assign { } { }
assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r3__nia $1\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:201052.7-201052.29"
- process $proc$libresoc.v:201052$14344
+ attribute \src "libresoc.v:200948.7-200948.29"
+ process $proc$libresoc.v:200948$14136
assign { } { }
assign $1\data_r3__nia_ok[0:0] 1'0
sync always
sync init
update \data_r3__nia_ok $1\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:201056.14-201056.49"
- process $proc$libresoc.v:201056$14345
+ attribute \src "libresoc.v:200952.14-200952.49"
+ process $proc$libresoc.v:200952$14137
assign { } { }
assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \data_r4__msr $1\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:201060.7-201060.29"
- process $proc$libresoc.v:201060$14346
+ attribute \src "libresoc.v:200956.7-200956.29"
+ process $proc$libresoc.v:200956$14138
assign { } { }
assign $1\data_r4__msr_ok[0:0] 1'0
sync always
sync init
update \data_r4__msr_ok $1\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:201091.7-201091.25"
- process $proc$libresoc.v:201091$14347
+ attribute \src "libresoc.v:200987.7-200987.25"
+ process $proc$libresoc.v:200987$14139
assign { } { }
assign $1\opc_l_r_opc[0:0] 1'1
sync always
sync init
update \opc_l_r_opc $1\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:201095.7-201095.25"
- process $proc$libresoc.v:201095$14348
+ attribute \src "libresoc.v:200991.7-200991.25"
+ process $proc$libresoc.v:200991$14140
assign { } { }
assign $1\opc_l_s_opc[0:0] 1'0
sync always
sync init
update \opc_l_s_opc $1\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:201207.13-201207.31"
- process $proc$libresoc.v:201207$14349
+ attribute \src "libresoc.v:201103.13-201103.31"
+ process $proc$libresoc.v:201103$14141
assign { } { }
assign $1\prev_wr_go[4:0] 5'00000
sync always
sync init
update \prev_wr_go $1\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:201215.13-201215.32"
- process $proc$libresoc.v:201215$14350
+ attribute \src "libresoc.v:201111.13-201111.32"
+ process $proc$libresoc.v:201111$14142
assign { } { }
assign $1\req_l_r_req[4:0] 5'11111
sync always
sync init
update \req_l_r_req $1\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:201219.13-201219.32"
- process $proc$libresoc.v:201219$14351
+ attribute \src "libresoc.v:201115.13-201115.32"
+ process $proc$libresoc.v:201115$14143
assign { } { }
assign $1\req_l_s_req[4:0] 5'00000
sync always
sync init
update \req_l_s_req $1\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:201231.7-201231.26"
- process $proc$libresoc.v:201231$14352
+ attribute \src "libresoc.v:201127.7-201127.26"
+ process $proc$libresoc.v:201127$14144
assign { } { }
assign $1\rok_l_r_rdok[0:0] 1'1
sync always
sync init
update \rok_l_r_rdok $1\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:201235.7-201235.26"
- process $proc$libresoc.v:201235$14353
+ attribute \src "libresoc.v:201131.7-201131.26"
+ process $proc$libresoc.v:201131$14145
assign { } { }
assign $1\rok_l_s_rdok[0:0] 1'0
sync always
sync init
update \rok_l_s_rdok $1\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:201239.7-201239.25"
- process $proc$libresoc.v:201239$14354
+ attribute \src "libresoc.v:201135.7-201135.25"
+ process $proc$libresoc.v:201135$14146
assign { } { }
assign $1\rst_l_r_rst[0:0] 1'1
sync always
sync init
update \rst_l_r_rst $1\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:201243.7-201243.25"
- process $proc$libresoc.v:201243$14355
+ attribute \src "libresoc.v:201139.7-201139.25"
+ process $proc$libresoc.v:201139$14147
assign { } { }
assign $1\rst_l_s_rst[0:0] 1'0
sync always
sync init
update \rst_l_s_rst $1\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:201259.13-201259.31"
- process $proc$libresoc.v:201259$14356
+ attribute \src "libresoc.v:201155.13-201155.31"
+ process $proc$libresoc.v:201155$14148
assign { } { }
assign $1\src_l_r_src[3:0] 4'1111
sync always
sync init
update \src_l_r_src $1\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:201263.13-201263.31"
- process $proc$libresoc.v:201263$14357
+ attribute \src "libresoc.v:201159.13-201159.31"
+ process $proc$libresoc.v:201159$14149
assign { } { }
assign $1\src_l_s_src[3:0] 4'0000
sync always
sync init
update \src_l_s_src $1\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:201267.14-201267.43"
- process $proc$libresoc.v:201267$14358
+ attribute \src "libresoc.v:201163.14-201163.43"
+ process $proc$libresoc.v:201163$14150
assign { } { }
assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r0 $1\src_r0[63:0]
end
- attribute \src "libresoc.v:201271.14-201271.43"
- process $proc$libresoc.v:201271$14359
+ attribute \src "libresoc.v:201167.14-201167.43"
+ process $proc$libresoc.v:201167$14151
assign { } { }
assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r1 $1\src_r1[63:0]
end
- attribute \src "libresoc.v:201275.14-201275.43"
- process $proc$libresoc.v:201275$14360
+ attribute \src "libresoc.v:201171.14-201171.43"
+ process $proc$libresoc.v:201171$14152
assign { } { }
assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r2 $1\src_r2[63:0]
end
- attribute \src "libresoc.v:201279.14-201279.43"
- process $proc$libresoc.v:201279$14361
+ attribute \src "libresoc.v:201175.14-201175.43"
+ process $proc$libresoc.v:201175$14153
assign { } { }
assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \src_r3 $1\src_r3[63:0]
end
- attribute \src "libresoc.v:201345.3-201346.39"
- process $proc$libresoc.v:201345$14169
+ attribute \src "libresoc.v:201241.3-201242.39"
+ process $proc$libresoc.v:201241$13961
assign { } { }
assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next
sync posedge \coresync_clk
update \alu_l_r_alu $0\alu_l_r_alu[0:0]
end
- attribute \src "libresoc.v:201347.3-201348.43"
- process $proc$libresoc.v:201347$14170
+ attribute \src "libresoc.v:201243.3-201244.43"
+ process $proc$libresoc.v:201243$13962
assign { } { }
assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next
sync posedge \coresync_clk
update \alui_l_r_alui $0\alui_l_r_alui[0:0]
end
- attribute \src "libresoc.v:201349.3-201350.29"
- process $proc$libresoc.v:201349$14171
+ attribute \src "libresoc.v:201245.3-201246.29"
+ process $proc$libresoc.v:201245$13963
assign { } { }
assign $0\src_r3[63:0] \src_r3$next
sync posedge \coresync_clk
update \src_r3 $0\src_r3[63:0]
end
- attribute \src "libresoc.v:201351.3-201352.29"
- process $proc$libresoc.v:201351$14172
+ attribute \src "libresoc.v:201247.3-201248.29"
+ process $proc$libresoc.v:201247$13964
assign { } { }
assign $0\src_r2[63:0] \src_r2$next
sync posedge \coresync_clk
update \src_r2 $0\src_r2[63:0]
end
- attribute \src "libresoc.v:201353.3-201354.29"
- process $proc$libresoc.v:201353$14173
+ attribute \src "libresoc.v:201249.3-201250.29"
+ process $proc$libresoc.v:201249$13965
assign { } { }
assign $0\src_r1[63:0] \src_r1$next
sync posedge \coresync_clk
update \src_r1 $0\src_r1[63:0]
end
- attribute \src "libresoc.v:201355.3-201356.29"
- process $proc$libresoc.v:201355$14174
+ attribute \src "libresoc.v:201251.3-201252.29"
+ process $proc$libresoc.v:201251$13966
assign { } { }
assign $0\src_r0[63:0] \src_r0$next
sync posedge \coresync_clk
update \src_r0 $0\src_r0[63:0]
end
- attribute \src "libresoc.v:201357.3-201358.41"
- process $proc$libresoc.v:201357$14175
+ attribute \src "libresoc.v:201253.3-201254.41"
+ process $proc$libresoc.v:201253$13967
assign { } { }
assign $0\data_r4__msr[63:0] \data_r4__msr$next
sync posedge \coresync_clk
update \data_r4__msr $0\data_r4__msr[63:0]
end
- attribute \src "libresoc.v:201359.3-201360.47"
- process $proc$libresoc.v:201359$14176
+ attribute \src "libresoc.v:201255.3-201256.47"
+ process $proc$libresoc.v:201255$13968
assign { } { }
assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next
sync posedge \coresync_clk
update \data_r4__msr_ok $0\data_r4__msr_ok[0:0]
end
- attribute \src "libresoc.v:201361.3-201362.41"
- process $proc$libresoc.v:201361$14177
+ attribute \src "libresoc.v:201257.3-201258.41"
+ process $proc$libresoc.v:201257$13969
assign { } { }
assign $0\data_r3__nia[63:0] \data_r3__nia$next
sync posedge \coresync_clk
update \data_r3__nia $0\data_r3__nia[63:0]
end
- attribute \src "libresoc.v:201363.3-201364.47"
- process $proc$libresoc.v:201363$14178
+ attribute \src "libresoc.v:201259.3-201260.47"
+ process $proc$libresoc.v:201259$13970
assign { } { }
assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next
sync posedge \coresync_clk
update \data_r3__nia_ok $0\data_r3__nia_ok[0:0]
end
- attribute \src "libresoc.v:201365.3-201366.45"
- process $proc$libresoc.v:201365$14179
+ attribute \src "libresoc.v:201261.3-201262.45"
+ process $proc$libresoc.v:201261$13971
assign { } { }
assign $0\data_r2__fast2[63:0] \data_r2__fast2$next
sync posedge \coresync_clk
update \data_r2__fast2 $0\data_r2__fast2[63:0]
end
- attribute \src "libresoc.v:201367.3-201368.51"
- process $proc$libresoc.v:201367$14180
+ attribute \src "libresoc.v:201263.3-201264.51"
+ process $proc$libresoc.v:201263$13972
assign { } { }
assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next
sync posedge \coresync_clk
update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0]
end
- attribute \src "libresoc.v:201369.3-201370.45"
- process $proc$libresoc.v:201369$14181
+ attribute \src "libresoc.v:201265.3-201266.45"
+ process $proc$libresoc.v:201265$13973
assign { } { }
assign $0\data_r1__fast1[63:0] \data_r1__fast1$next
sync posedge \coresync_clk
update \data_r1__fast1 $0\data_r1__fast1[63:0]
end
- attribute \src "libresoc.v:201371.3-201372.51"
- process $proc$libresoc.v:201371$14182
+ attribute \src "libresoc.v:201267.3-201268.51"
+ process $proc$libresoc.v:201267$13974
assign { } { }
assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next
sync posedge \coresync_clk
update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0]
end
- attribute \src "libresoc.v:201373.3-201374.37"
- process $proc$libresoc.v:201373$14183
+ attribute \src "libresoc.v:201269.3-201270.37"
+ process $proc$libresoc.v:201269$13975
assign { } { }
assign $0\data_r0__o[63:0] \data_r0__o$next
sync posedge \coresync_clk
update \data_r0__o $0\data_r0__o[63:0]
end
- attribute \src "libresoc.v:201375.3-201376.43"
- process $proc$libresoc.v:201375$14184
+ attribute \src "libresoc.v:201271.3-201272.43"
+ process $proc$libresoc.v:201271$13976
assign { } { }
assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next
sync posedge \coresync_clk
update \data_r0__o_ok $0\data_r0__o_ok[0:0]
end
- attribute \src "libresoc.v:201377.3-201378.73"
- process $proc$libresoc.v:201377$14185
+ attribute \src "libresoc.v:201273.3-201274.73"
+ process $proc$libresoc.v:201273$13977
assign { } { }
assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0]
end
- attribute \src "libresoc.v:201379.3-201380.69"
- process $proc$libresoc.v:201379$14186
+ attribute \src "libresoc.v:201275.3-201276.69"
+ process $proc$libresoc.v:201275$13978
assign { } { }
assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0]
end
- attribute \src "libresoc.v:201381.3-201382.63"
- process $proc$libresoc.v:201381$14187
+ attribute \src "libresoc.v:201277.3-201278.63"
+ process $proc$libresoc.v:201277$13979
assign { } { }
assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0]
end
- attribute \src "libresoc.v:201383.3-201384.61"
- process $proc$libresoc.v:201383$14188
+ attribute \src "libresoc.v:201279.3-201280.61"
+ process $proc$libresoc.v:201279$13980
assign { } { }
assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0]
end
- attribute \src "libresoc.v:201385.3-201386.61"
- process $proc$libresoc.v:201385$14189
+ attribute \src "libresoc.v:201281.3-201282.61"
+ process $proc$libresoc.v:201281$13981
assign { } { }
assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0]
end
- attribute \src "libresoc.v:201387.3-201388.71"
- process $proc$libresoc.v:201387$14190
+ attribute \src "libresoc.v:201283.3-201284.71"
+ process $proc$libresoc.v:201283$13982
assign { } { }
assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0]
end
- attribute \src "libresoc.v:201389.3-201390.71"
- process $proc$libresoc.v:201389$14191
+ attribute \src "libresoc.v:201285.3-201286.71"
+ process $proc$libresoc.v:201285$13983
assign { } { }
assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0]
end
- attribute \src "libresoc.v:201391.3-201392.71"
- process $proc$libresoc.v:201391$14192
+ attribute \src "libresoc.v:201287.3-201288.71"
+ process $proc$libresoc.v:201287$13984
assign { } { }
assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0]
end
- attribute \src "libresoc.v:201393.3-201394.71"
- process $proc$libresoc.v:201393$14193
+ attribute \src "libresoc.v:201289.3-201290.71"
+ process $proc$libresoc.v:201289$13985
assign { } { }
assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next
sync posedge \coresync_clk
update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0]
end
- attribute \src "libresoc.v:201395.3-201396.39"
- process $proc$libresoc.v:201395$14194
+ attribute \src "libresoc.v:201291.3-201292.39"
+ process $proc$libresoc.v:201291$13986
assign { } { }
assign $0\req_l_r_req[4:0] \req_l_r_req$next
sync posedge \coresync_clk
update \req_l_r_req $0\req_l_r_req[4:0]
end
- attribute \src "libresoc.v:201397.3-201398.39"
- process $proc$libresoc.v:201397$14195
+ attribute \src "libresoc.v:201293.3-201294.39"
+ process $proc$libresoc.v:201293$13987
assign { } { }
assign $0\req_l_s_req[4:0] \req_l_s_req$next
sync posedge \coresync_clk
update \req_l_s_req $0\req_l_s_req[4:0]
end
- attribute \src "libresoc.v:201399.3-201400.39"
- process $proc$libresoc.v:201399$14196
+ attribute \src "libresoc.v:201295.3-201296.39"
+ process $proc$libresoc.v:201295$13988
assign { } { }
assign $0\src_l_r_src[3:0] \src_l_r_src$next
sync posedge \coresync_clk
update \src_l_r_src $0\src_l_r_src[3:0]
end
- attribute \src "libresoc.v:201401.3-201402.39"
- process $proc$libresoc.v:201401$14197
+ attribute \src "libresoc.v:201297.3-201298.39"
+ process $proc$libresoc.v:201297$13989
assign { } { }
assign $0\src_l_s_src[3:0] \src_l_s_src$next
sync posedge \coresync_clk
update \src_l_s_src $0\src_l_s_src[3:0]
end
- attribute \src "libresoc.v:201403.3-201404.39"
- process $proc$libresoc.v:201403$14198
+ attribute \src "libresoc.v:201299.3-201300.39"
+ process $proc$libresoc.v:201299$13990
assign { } { }
assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next
sync posedge \coresync_clk
update \opc_l_r_opc $0\opc_l_r_opc[0:0]
end
- attribute \src "libresoc.v:201405.3-201406.39"
- process $proc$libresoc.v:201405$14199
+ attribute \src "libresoc.v:201301.3-201302.39"
+ process $proc$libresoc.v:201301$13991
assign { } { }
assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next
sync posedge \coresync_clk
update \opc_l_s_opc $0\opc_l_s_opc[0:0]
end
- attribute \src "libresoc.v:201407.3-201408.39"
- process $proc$libresoc.v:201407$14200
+ attribute \src "libresoc.v:201303.3-201304.39"
+ process $proc$libresoc.v:201303$13992
assign { } { }
assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next
sync posedge \coresync_clk
update \rst_l_r_rst $0\rst_l_r_rst[0:0]
end
- attribute \src "libresoc.v:201409.3-201410.39"
- process $proc$libresoc.v:201409$14201
+ attribute \src "libresoc.v:201305.3-201306.39"
+ process $proc$libresoc.v:201305$13993
assign { } { }
assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next
sync posedge \coresync_clk
update \rst_l_s_rst $0\rst_l_s_rst[0:0]
end
- attribute \src "libresoc.v:201411.3-201412.41"
- process $proc$libresoc.v:201411$14202
+ attribute \src "libresoc.v:201307.3-201308.41"
+ process $proc$libresoc.v:201307$13994
assign { } { }
assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next
sync posedge \coresync_clk
update \rok_l_r_rdok $0\rok_l_r_rdok[0:0]
end
- attribute \src "libresoc.v:201413.3-201414.41"
- process $proc$libresoc.v:201413$14203
+ attribute \src "libresoc.v:201309.3-201310.41"
+ process $proc$libresoc.v:201309$13995
assign { } { }
assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next
sync posedge \coresync_clk
update \rok_l_s_rdok $0\rok_l_s_rdok[0:0]
end
- attribute \src "libresoc.v:201415.3-201416.37"
- process $proc$libresoc.v:201415$14204
+ attribute \src "libresoc.v:201311.3-201312.37"
+ process $proc$libresoc.v:201311$13996
assign { } { }
assign $0\prev_wr_go[4:0] \prev_wr_go$next
sync posedge \coresync_clk
update \prev_wr_go $0\prev_wr_go[4:0]
end
- attribute \src "libresoc.v:201417.3-201418.41"
- process $proc$libresoc.v:201417$14205
+ attribute \src "libresoc.v:201313.3-201314.41"
+ process $proc$libresoc.v:201313$13997
assign { } { }
assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o
sync posedge \coresync_clk
update \alu_done_dly $0\alu_done_dly[0:0]
end
- attribute \src "libresoc.v:201419.3-201420.25"
- process $proc$libresoc.v:201419$14206
+ attribute \src "libresoc.v:201315.3-201316.25"
+ process $proc$libresoc.v:201315$13998
assign { } { }
assign $0\all_rd_dly[0:0] \$11
sync posedge \coresync_clk
update \all_rd_dly $0\all_rd_dly[0:0]
end
- attribute \src "libresoc.v:201500.3-201509.6"
- process $proc$libresoc.v:201500$14207
+ attribute \src "libresoc.v:201396.3-201405.6"
+ process $proc$libresoc.v:201396$13999
assign { } { }
assign { } { }
assign $0\req_done[0:0] $1\req_done[0:0]
- attribute \src "libresoc.v:201501.5-201501.29"
+ attribute \src "libresoc.v:201397.5-201397.29"
switch \initial
- attribute \src "libresoc.v:201501.9-201501.17"
+ attribute \src "libresoc.v:201397.9-201397.17"
case 1'1
case
end
sync always
update \req_done $0\req_done[0:0]
end
- attribute \src "libresoc.v:201510.3-201518.6"
- process $proc$libresoc.v:201510$14208
+ attribute \src "libresoc.v:201406.3-201414.6"
+ process $proc$libresoc.v:201406$14000
assign { } { }
assign { } { }
- assign $0\rok_l_s_rdok$next[0:0]$14209 $1\rok_l_s_rdok$next[0:0]$14210
- attribute \src "libresoc.v:201511.5-201511.29"
+ assign $0\rok_l_s_rdok$next[0:0]$14001 $1\rok_l_s_rdok$next[0:0]$14002
+ attribute \src "libresoc.v:201407.5-201407.29"
switch \initial
- attribute \src "libresoc.v:201511.9-201511.17"
+ attribute \src "libresoc.v:201407.9-201407.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_s_rdok$next[0:0]$14210 1'0
+ assign $1\rok_l_s_rdok$next[0:0]$14002 1'0
case
- assign $1\rok_l_s_rdok$next[0:0]$14210 \cu_issue_i
+ assign $1\rok_l_s_rdok$next[0:0]$14002 \cu_issue_i
end
sync always
- update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14209
+ update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14001
end
- attribute \src "libresoc.v:201519.3-201527.6"
- process $proc$libresoc.v:201519$14211
+ attribute \src "libresoc.v:201415.3-201423.6"
+ process $proc$libresoc.v:201415$14003
assign { } { }
assign { } { }
- assign $0\rok_l_r_rdok$next[0:0]$14212 $1\rok_l_r_rdok$next[0:0]$14213
- attribute \src "libresoc.v:201520.5-201520.29"
+ assign $0\rok_l_r_rdok$next[0:0]$14004 $1\rok_l_r_rdok$next[0:0]$14005
+ attribute \src "libresoc.v:201416.5-201416.29"
switch \initial
- attribute \src "libresoc.v:201520.9-201520.17"
+ attribute \src "libresoc.v:201416.9-201416.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rok_l_r_rdok$next[0:0]$14213 1'1
+ assign $1\rok_l_r_rdok$next[0:0]$14005 1'1
case
- assign $1\rok_l_r_rdok$next[0:0]$14213 \$65
+ assign $1\rok_l_r_rdok$next[0:0]$14005 \$65
end
sync always
- update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14212
+ update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14004
end
- attribute \src "libresoc.v:201528.3-201536.6"
- process $proc$libresoc.v:201528$14214
+ attribute \src "libresoc.v:201424.3-201432.6"
+ process $proc$libresoc.v:201424$14006
assign { } { }
assign { } { }
- assign $0\rst_l_s_rst$next[0:0]$14215 $1\rst_l_s_rst$next[0:0]$14216
- attribute \src "libresoc.v:201529.5-201529.29"
+ assign $0\rst_l_s_rst$next[0:0]$14007 $1\rst_l_s_rst$next[0:0]$14008
+ attribute \src "libresoc.v:201425.5-201425.29"
switch \initial
- attribute \src "libresoc.v:201529.9-201529.17"
+ attribute \src "libresoc.v:201425.9-201425.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_s_rst$next[0:0]$14216 1'0
+ assign $1\rst_l_s_rst$next[0:0]$14008 1'0
case
- assign $1\rst_l_s_rst$next[0:0]$14216 \all_rd
+ assign $1\rst_l_s_rst$next[0:0]$14008 \all_rd
end
sync always
- update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14215
+ update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14007
end
- attribute \src "libresoc.v:201537.3-201545.6"
- process $proc$libresoc.v:201537$14217
+ attribute \src "libresoc.v:201433.3-201441.6"
+ process $proc$libresoc.v:201433$14009
assign { } { }
assign { } { }
- assign $0\rst_l_r_rst$next[0:0]$14218 $1\rst_l_r_rst$next[0:0]$14219
- attribute \src "libresoc.v:201538.5-201538.29"
+ assign $0\rst_l_r_rst$next[0:0]$14010 $1\rst_l_r_rst$next[0:0]$14011
+ attribute \src "libresoc.v:201434.5-201434.29"
switch \initial
- attribute \src "libresoc.v:201538.9-201538.17"
+ attribute \src "libresoc.v:201434.9-201434.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\rst_l_r_rst$next[0:0]$14219 1'1
+ assign $1\rst_l_r_rst$next[0:0]$14011 1'1
case
- assign $1\rst_l_r_rst$next[0:0]$14219 \rst_r
+ assign $1\rst_l_r_rst$next[0:0]$14011 \rst_r
end
sync always
- update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14218
+ update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14010
end
- attribute \src "libresoc.v:201546.3-201554.6"
- process $proc$libresoc.v:201546$14220
+ attribute \src "libresoc.v:201442.3-201450.6"
+ process $proc$libresoc.v:201442$14012
assign { } { }
assign { } { }
- assign $0\opc_l_s_opc$next[0:0]$14221 $1\opc_l_s_opc$next[0:0]$14222
- attribute \src "libresoc.v:201547.5-201547.29"
+ assign $0\opc_l_s_opc$next[0:0]$14013 $1\opc_l_s_opc$next[0:0]$14014
+ attribute \src "libresoc.v:201443.5-201443.29"
switch \initial
- attribute \src "libresoc.v:201547.9-201547.17"
+ attribute \src "libresoc.v:201443.9-201443.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_s_opc$next[0:0]$14222 1'0
+ assign $1\opc_l_s_opc$next[0:0]$14014 1'0
case
- assign $1\opc_l_s_opc$next[0:0]$14222 \cu_issue_i
+ assign $1\opc_l_s_opc$next[0:0]$14014 \cu_issue_i
end
sync always
- update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14221
+ update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14013
end
- attribute \src "libresoc.v:201555.3-201563.6"
- process $proc$libresoc.v:201555$14223
+ attribute \src "libresoc.v:201451.3-201459.6"
+ process $proc$libresoc.v:201451$14015
assign { } { }
assign { } { }
- assign $0\opc_l_r_opc$next[0:0]$14224 $1\opc_l_r_opc$next[0:0]$14225
- attribute \src "libresoc.v:201556.5-201556.29"
+ assign $0\opc_l_r_opc$next[0:0]$14016 $1\opc_l_r_opc$next[0:0]$14017
+ attribute \src "libresoc.v:201452.5-201452.29"
switch \initial
- attribute \src "libresoc.v:201556.9-201556.17"
+ attribute \src "libresoc.v:201452.9-201452.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\opc_l_r_opc$next[0:0]$14225 1'1
+ assign $1\opc_l_r_opc$next[0:0]$14017 1'1
case
- assign $1\opc_l_r_opc$next[0:0]$14225 \req_done
+ assign $1\opc_l_r_opc$next[0:0]$14017 \req_done
end
sync always
- update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14224
+ update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14016
end
- attribute \src "libresoc.v:201564.3-201572.6"
- process $proc$libresoc.v:201564$14226
+ attribute \src "libresoc.v:201460.3-201468.6"
+ process $proc$libresoc.v:201460$14018
assign { } { }
assign { } { }
- assign $0\src_l_s_src$next[3:0]$14227 $1\src_l_s_src$next[3:0]$14228
- attribute \src "libresoc.v:201565.5-201565.29"
+ assign $0\src_l_s_src$next[3:0]$14019 $1\src_l_s_src$next[3:0]$14020
+ attribute \src "libresoc.v:201461.5-201461.29"
switch \initial
- attribute \src "libresoc.v:201565.9-201565.17"
+ attribute \src "libresoc.v:201461.9-201461.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_s_src$next[3:0]$14228 4'0000
+ assign $1\src_l_s_src$next[3:0]$14020 4'0000
case
- assign $1\src_l_s_src$next[3:0]$14228 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+ assign $1\src_l_s_src$next[3:0]$14020 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
end
sync always
- update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14227
+ update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14019
end
- attribute \src "libresoc.v:201573.3-201581.6"
- process $proc$libresoc.v:201573$14229
+ attribute \src "libresoc.v:201469.3-201477.6"
+ process $proc$libresoc.v:201469$14021
assign { } { }
assign { } { }
- assign $0\src_l_r_src$next[3:0]$14230 $1\src_l_r_src$next[3:0]$14231
- attribute \src "libresoc.v:201574.5-201574.29"
+ assign $0\src_l_r_src$next[3:0]$14022 $1\src_l_r_src$next[3:0]$14023
+ attribute \src "libresoc.v:201470.5-201470.29"
switch \initial
- attribute \src "libresoc.v:201574.9-201574.17"
+ attribute \src "libresoc.v:201470.9-201470.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_l_r_src$next[3:0]$14231 4'1111
+ assign $1\src_l_r_src$next[3:0]$14023 4'1111
case
- assign $1\src_l_r_src$next[3:0]$14231 \reset_r
+ assign $1\src_l_r_src$next[3:0]$14023 \reset_r
end
sync always
- update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14230
+ update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14022
end
- attribute \src "libresoc.v:201582.3-201590.6"
- process $proc$libresoc.v:201582$14232
+ attribute \src "libresoc.v:201478.3-201486.6"
+ process $proc$libresoc.v:201478$14024
assign { } { }
assign { } { }
- assign $0\req_l_s_req$next[4:0]$14233 $1\req_l_s_req$next[4:0]$14234
- attribute \src "libresoc.v:201583.5-201583.29"
+ assign $0\req_l_s_req$next[4:0]$14025 $1\req_l_s_req$next[4:0]$14026
+ attribute \src "libresoc.v:201479.5-201479.29"
switch \initial
- attribute \src "libresoc.v:201583.9-201583.17"
+ attribute \src "libresoc.v:201479.9-201479.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_s_req$next[4:0]$14234 5'00000
+ assign $1\req_l_s_req$next[4:0]$14026 5'00000
case
- assign $1\req_l_s_req$next[4:0]$14234 \$67
+ assign $1\req_l_s_req$next[4:0]$14026 \$67
end
sync always
- update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14233
+ update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14025
end
- attribute \src "libresoc.v:201591.3-201599.6"
- process $proc$libresoc.v:201591$14235
+ attribute \src "libresoc.v:201487.3-201495.6"
+ process $proc$libresoc.v:201487$14027
assign { } { }
assign { } { }
- assign $0\req_l_r_req$next[4:0]$14236 $1\req_l_r_req$next[4:0]$14237
- attribute \src "libresoc.v:201592.5-201592.29"
+ assign $0\req_l_r_req$next[4:0]$14028 $1\req_l_r_req$next[4:0]$14029
+ attribute \src "libresoc.v:201488.5-201488.29"
switch \initial
- attribute \src "libresoc.v:201592.9-201592.17"
+ attribute \src "libresoc.v:201488.9-201488.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\req_l_r_req$next[4:0]$14237 5'11111
+ assign $1\req_l_r_req$next[4:0]$14029 5'11111
case
- assign $1\req_l_r_req$next[4:0]$14237 \$69
+ assign $1\req_l_r_req$next[4:0]$14029 \$69
end
sync always
- update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14236
+ update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14028
end
- attribute \src "libresoc.v:201600.3-201617.6"
- process $proc$libresoc.v:201600$14238
+ attribute \src "libresoc.v:201496.3-201513.6"
+ process $proc$libresoc.v:201496$14030
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\alu_trap0_trap_op__cia$next[63:0]$14239 $1\alu_trap0_trap_op__cia$next[63:0]$14248
- assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249
- assign $0\alu_trap0_trap_op__insn$next[31:0]$14241 $1\alu_trap0_trap_op__insn$next[31:0]$14250
- assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14242 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251
- assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252
- assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253
- assign $0\alu_trap0_trap_op__msr$next[63:0]$14245 $1\alu_trap0_trap_op__msr$next[63:0]$14254
- assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255
- assign $0\alu_trap0_trap_op__traptype$next[7:0]$14247 $1\alu_trap0_trap_op__traptype$next[7:0]$14256
- attribute \src "libresoc.v:201601.5-201601.29"
+ assign $0\alu_trap0_trap_op__cia$next[63:0]$14031 $1\alu_trap0_trap_op__cia$next[63:0]$14040
+ assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041
+ assign $0\alu_trap0_trap_op__insn$next[31:0]$14033 $1\alu_trap0_trap_op__insn$next[31:0]$14042
+ assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14034 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043
+ assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044
+ assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045
+ assign $0\alu_trap0_trap_op__msr$next[63:0]$14037 $1\alu_trap0_trap_op__msr$next[63:0]$14046
+ assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047
+ assign $0\alu_trap0_trap_op__traptype$next[7:0]$14039 $1\alu_trap0_trap_op__traptype$next[7:0]$14048
+ attribute \src "libresoc.v:201497.5-201497.29"
switch \initial
- attribute \src "libresoc.v:201601.9-201601.17"
+ attribute \src "libresoc.v:201497.9-201497.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255 $1\alu_trap0_trap_op__traptype$next[7:0]$14256 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252 $1\alu_trap0_trap_op__cia$next[63:0]$14248 $1\alu_trap0_trap_op__msr$next[63:0]$14254 $1\alu_trap0_trap_op__insn$next[31:0]$14250 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249 $1\alu_trap0_trap_op__insn_type$next[6:0]$14251 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
+ assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 $1\alu_trap0_trap_op__traptype$next[7:0]$14048 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 $1\alu_trap0_trap_op__cia$next[63:0]$14040 $1\alu_trap0_trap_op__msr$next[63:0]$14046 $1\alu_trap0_trap_op__insn$next[31:0]$14042 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
case
- assign $1\alu_trap0_trap_op__cia$next[63:0]$14248 \alu_trap0_trap_op__cia
- assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14249 \alu_trap0_trap_op__fn_unit
- assign $1\alu_trap0_trap_op__insn$next[31:0]$14250 \alu_trap0_trap_op__insn
- assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14251 \alu_trap0_trap_op__insn_type
- assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14252 \alu_trap0_trap_op__is_32bit
- assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14253 \alu_trap0_trap_op__ldst_exc
- assign $1\alu_trap0_trap_op__msr$next[63:0]$14254 \alu_trap0_trap_op__msr
- assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14255 \alu_trap0_trap_op__trapaddr
- assign $1\alu_trap0_trap_op__traptype$next[7:0]$14256 \alu_trap0_trap_op__traptype
+ assign $1\alu_trap0_trap_op__cia$next[63:0]$14040 \alu_trap0_trap_op__cia
+ assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14041 \alu_trap0_trap_op__fn_unit
+ assign $1\alu_trap0_trap_op__insn$next[31:0]$14042 \alu_trap0_trap_op__insn
+ assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14043 \alu_trap0_trap_op__insn_type
+ assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14044 \alu_trap0_trap_op__is_32bit
+ assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14045 \alu_trap0_trap_op__ldst_exc
+ assign $1\alu_trap0_trap_op__msr$next[63:0]$14046 \alu_trap0_trap_op__msr
+ assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14047 \alu_trap0_trap_op__trapaddr
+ assign $1\alu_trap0_trap_op__traptype$next[7:0]$14048 \alu_trap0_trap_op__traptype
end
sync always
- update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14239
- update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14240
- update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14241
- update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14242
- update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14243
- update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14244
- update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14245
- update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14246
- update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14247
+ update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14031
+ update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14032
+ update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14033
+ update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14034
+ update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14035
+ update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14036
+ update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14037
+ update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14038
+ update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14039
end
- attribute \src "libresoc.v:201618.3-201639.6"
- process $proc$libresoc.v:201618$14257
+ attribute \src "libresoc.v:201514.3-201535.6"
+ process $proc$libresoc.v:201514$14049
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r0__o$next[63:0]$14258 $2\data_r0__o$next[63:0]$14262
+ assign $0\data_r0__o$next[63:0]$14050 $2\data_r0__o$next[63:0]$14054
assign { } { }
- assign $0\data_r0__o_ok$next[0:0]$14259 $3\data_r0__o_ok$next[0:0]$14264
- attribute \src "libresoc.v:201619.5-201619.29"
+ assign $0\data_r0__o_ok$next[0:0]$14051 $3\data_r0__o_ok$next[0:0]$14056
+ attribute \src "libresoc.v:201515.5-201515.29"
switch \initial
- attribute \src "libresoc.v:201619.9-201619.17"
+ attribute \src "libresoc.v:201515.9-201515.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r0__o_ok$next[0:0]$14261 $1\data_r0__o$next[63:0]$14260 } { \o_ok \alu_trap0_o }
+ assign { $1\data_r0__o_ok$next[0:0]$14053 $1\data_r0__o$next[63:0]$14052 } { \o_ok \alu_trap0_o }
case
- assign $1\data_r0__o$next[63:0]$14260 \data_r0__o
- assign $1\data_r0__o_ok$next[0:0]$14261 \data_r0__o_ok
+ assign $1\data_r0__o$next[63:0]$14052 \data_r0__o
+ assign $1\data_r0__o_ok$next[0:0]$14053 \data_r0__o_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r0__o_ok$next[0:0]$14263 $2\data_r0__o$next[63:0]$14262 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r0__o_ok$next[0:0]$14055 $2\data_r0__o$next[63:0]$14054 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r0__o$next[63:0]$14262 $1\data_r0__o$next[63:0]$14260
- assign $2\data_r0__o_ok$next[0:0]$14263 $1\data_r0__o_ok$next[0:0]$14261
+ assign $2\data_r0__o$next[63:0]$14054 $1\data_r0__o$next[63:0]$14052
+ assign $2\data_r0__o_ok$next[0:0]$14055 $1\data_r0__o_ok$next[0:0]$14053
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r0__o_ok$next[0:0]$14264 1'0
+ assign $3\data_r0__o_ok$next[0:0]$14056 1'0
case
- assign $3\data_r0__o_ok$next[0:0]$14264 $2\data_r0__o_ok$next[0:0]$14263
+ assign $3\data_r0__o_ok$next[0:0]$14056 $2\data_r0__o_ok$next[0:0]$14055
end
sync always
- update \data_r0__o$next $0\data_r0__o$next[63:0]$14258
- update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14259
+ update \data_r0__o$next $0\data_r0__o$next[63:0]$14050
+ update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14051
end
- attribute \src "libresoc.v:201640.3-201661.6"
- process $proc$libresoc.v:201640$14265
+ attribute \src "libresoc.v:201536.3-201557.6"
+ process $proc$libresoc.v:201536$14057
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r1__fast1$next[63:0]$14266 $2\data_r1__fast1$next[63:0]$14270
+ assign $0\data_r1__fast1$next[63:0]$14058 $2\data_r1__fast1$next[63:0]$14062
assign { } { }
- assign $0\data_r1__fast1_ok$next[0:0]$14267 $3\data_r1__fast1_ok$next[0:0]$14272
- attribute \src "libresoc.v:201641.5-201641.29"
+ assign $0\data_r1__fast1_ok$next[0:0]$14059 $3\data_r1__fast1_ok$next[0:0]$14064
+ attribute \src "libresoc.v:201537.5-201537.29"
switch \initial
- attribute \src "libresoc.v:201641.9-201641.17"
+ attribute \src "libresoc.v:201537.9-201537.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r1__fast1_ok$next[0:0]$14269 $1\data_r1__fast1$next[63:0]$14268 } { \fast1_ok \alu_trap0_fast1 }
+ assign { $1\data_r1__fast1_ok$next[0:0]$14061 $1\data_r1__fast1$next[63:0]$14060 } { \fast1_ok \alu_trap0_fast1 }
case
- assign $1\data_r1__fast1$next[63:0]$14268 \data_r1__fast1
- assign $1\data_r1__fast1_ok$next[0:0]$14269 \data_r1__fast1_ok
+ assign $1\data_r1__fast1$next[63:0]$14060 \data_r1__fast1
+ assign $1\data_r1__fast1_ok$next[0:0]$14061 \data_r1__fast1_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r1__fast1_ok$next[0:0]$14271 $2\data_r1__fast1$next[63:0]$14270 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r1__fast1_ok$next[0:0]$14063 $2\data_r1__fast1$next[63:0]$14062 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r1__fast1$next[63:0]$14270 $1\data_r1__fast1$next[63:0]$14268
- assign $2\data_r1__fast1_ok$next[0:0]$14271 $1\data_r1__fast1_ok$next[0:0]$14269
+ assign $2\data_r1__fast1$next[63:0]$14062 $1\data_r1__fast1$next[63:0]$14060
+ assign $2\data_r1__fast1_ok$next[0:0]$14063 $1\data_r1__fast1_ok$next[0:0]$14061
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r1__fast1_ok$next[0:0]$14272 1'0
+ assign $3\data_r1__fast1_ok$next[0:0]$14064 1'0
case
- assign $3\data_r1__fast1_ok$next[0:0]$14272 $2\data_r1__fast1_ok$next[0:0]$14271
+ assign $3\data_r1__fast1_ok$next[0:0]$14064 $2\data_r1__fast1_ok$next[0:0]$14063
end
sync always
- update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14266
- update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14267
+ update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14058
+ update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14059
end
- attribute \src "libresoc.v:201662.3-201683.6"
- process $proc$libresoc.v:201662$14273
+ attribute \src "libresoc.v:201558.3-201579.6"
+ process $proc$libresoc.v:201558$14065
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r2__fast2$next[63:0]$14274 $2\data_r2__fast2$next[63:0]$14278
+ assign $0\data_r2__fast2$next[63:0]$14066 $2\data_r2__fast2$next[63:0]$14070
assign { } { }
- assign $0\data_r2__fast2_ok$next[0:0]$14275 $3\data_r2__fast2_ok$next[0:0]$14280
- attribute \src "libresoc.v:201663.5-201663.29"
+ assign $0\data_r2__fast2_ok$next[0:0]$14067 $3\data_r2__fast2_ok$next[0:0]$14072
+ attribute \src "libresoc.v:201559.5-201559.29"
switch \initial
- attribute \src "libresoc.v:201663.9-201663.17"
+ attribute \src "libresoc.v:201559.9-201559.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r2__fast2_ok$next[0:0]$14277 $1\data_r2__fast2$next[63:0]$14276 } { \fast2_ok \alu_trap0_fast2 }
+ assign { $1\data_r2__fast2_ok$next[0:0]$14069 $1\data_r2__fast2$next[63:0]$14068 } { \fast2_ok \alu_trap0_fast2 }
case
- assign $1\data_r2__fast2$next[63:0]$14276 \data_r2__fast2
- assign $1\data_r2__fast2_ok$next[0:0]$14277 \data_r2__fast2_ok
+ assign $1\data_r2__fast2$next[63:0]$14068 \data_r2__fast2
+ assign $1\data_r2__fast2_ok$next[0:0]$14069 \data_r2__fast2_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r2__fast2_ok$next[0:0]$14279 $2\data_r2__fast2$next[63:0]$14278 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r2__fast2_ok$next[0:0]$14071 $2\data_r2__fast2$next[63:0]$14070 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r2__fast2$next[63:0]$14278 $1\data_r2__fast2$next[63:0]$14276
- assign $2\data_r2__fast2_ok$next[0:0]$14279 $1\data_r2__fast2_ok$next[0:0]$14277
+ assign $2\data_r2__fast2$next[63:0]$14070 $1\data_r2__fast2$next[63:0]$14068
+ assign $2\data_r2__fast2_ok$next[0:0]$14071 $1\data_r2__fast2_ok$next[0:0]$14069
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r2__fast2_ok$next[0:0]$14280 1'0
+ assign $3\data_r2__fast2_ok$next[0:0]$14072 1'0
case
- assign $3\data_r2__fast2_ok$next[0:0]$14280 $2\data_r2__fast2_ok$next[0:0]$14279
+ assign $3\data_r2__fast2_ok$next[0:0]$14072 $2\data_r2__fast2_ok$next[0:0]$14071
end
sync always
- update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14274
- update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14275
+ update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14066
+ update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14067
end
- attribute \src "libresoc.v:201684.3-201705.6"
- process $proc$libresoc.v:201684$14281
+ attribute \src "libresoc.v:201580.3-201601.6"
+ process $proc$libresoc.v:201580$14073
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r3__nia$next[63:0]$14282 $2\data_r3__nia$next[63:0]$14286
+ assign $0\data_r3__nia$next[63:0]$14074 $2\data_r3__nia$next[63:0]$14078
assign { } { }
- assign $0\data_r3__nia_ok$next[0:0]$14283 $3\data_r3__nia_ok$next[0:0]$14288
- attribute \src "libresoc.v:201685.5-201685.29"
+ assign $0\data_r3__nia_ok$next[0:0]$14075 $3\data_r3__nia_ok$next[0:0]$14080
+ attribute \src "libresoc.v:201581.5-201581.29"
switch \initial
- attribute \src "libresoc.v:201685.9-201685.17"
+ attribute \src "libresoc.v:201581.9-201581.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r3__nia_ok$next[0:0]$14285 $1\data_r3__nia$next[63:0]$14284 } { \nia_ok \alu_trap0_nia }
+ assign { $1\data_r3__nia_ok$next[0:0]$14077 $1\data_r3__nia$next[63:0]$14076 } { \nia_ok \alu_trap0_nia }
case
- assign $1\data_r3__nia$next[63:0]$14284 \data_r3__nia
- assign $1\data_r3__nia_ok$next[0:0]$14285 \data_r3__nia_ok
+ assign $1\data_r3__nia$next[63:0]$14076 \data_r3__nia
+ assign $1\data_r3__nia_ok$next[0:0]$14077 \data_r3__nia_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r3__nia_ok$next[0:0]$14287 $2\data_r3__nia$next[63:0]$14286 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r3__nia_ok$next[0:0]$14079 $2\data_r3__nia$next[63:0]$14078 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r3__nia$next[63:0]$14286 $1\data_r3__nia$next[63:0]$14284
- assign $2\data_r3__nia_ok$next[0:0]$14287 $1\data_r3__nia_ok$next[0:0]$14285
+ assign $2\data_r3__nia$next[63:0]$14078 $1\data_r3__nia$next[63:0]$14076
+ assign $2\data_r3__nia_ok$next[0:0]$14079 $1\data_r3__nia_ok$next[0:0]$14077
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r3__nia_ok$next[0:0]$14288 1'0
+ assign $3\data_r3__nia_ok$next[0:0]$14080 1'0
case
- assign $3\data_r3__nia_ok$next[0:0]$14288 $2\data_r3__nia_ok$next[0:0]$14287
+ assign $3\data_r3__nia_ok$next[0:0]$14080 $2\data_r3__nia_ok$next[0:0]$14079
end
sync always
- update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14282
- update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14283
+ update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14074
+ update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14075
end
- attribute \src "libresoc.v:201706.3-201727.6"
- process $proc$libresoc.v:201706$14289
+ attribute \src "libresoc.v:201602.3-201623.6"
+ process $proc$libresoc.v:201602$14081
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\data_r4__msr$next[63:0]$14290 $2\data_r4__msr$next[63:0]$14294
+ assign $0\data_r4__msr$next[63:0]$14082 $2\data_r4__msr$next[63:0]$14086
assign { } { }
- assign $0\data_r4__msr_ok$next[0:0]$14291 $3\data_r4__msr_ok$next[0:0]$14296
- attribute \src "libresoc.v:201707.5-201707.29"
+ assign $0\data_r4__msr_ok$next[0:0]$14083 $3\data_r4__msr_ok$next[0:0]$14088
+ attribute \src "libresoc.v:201603.5-201603.29"
switch \initial
- attribute \src "libresoc.v:201707.9-201707.17"
+ attribute \src "libresoc.v:201603.9-201603.17"
case 1'1
case
end
case 1'1
assign { } { }
assign { } { }
- assign { $1\data_r4__msr_ok$next[0:0]$14293 $1\data_r4__msr$next[63:0]$14292 } { \msr_ok \alu_trap0_msr }
+ assign { $1\data_r4__msr_ok$next[0:0]$14085 $1\data_r4__msr$next[63:0]$14084 } { \msr_ok \alu_trap0_msr }
case
- assign $1\data_r4__msr$next[63:0]$14292 \data_r4__msr
- assign $1\data_r4__msr_ok$next[0:0]$14293 \data_r4__msr_ok
+ assign $1\data_r4__msr$next[63:0]$14084 \data_r4__msr
+ assign $1\data_r4__msr_ok$next[0:0]$14085 \data_r4__msr_ok
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279"
switch \cu_issue_i
case 1'1
assign { } { }
assign { } { }
- assign { $2\data_r4__msr_ok$next[0:0]$14295 $2\data_r4__msr$next[63:0]$14294 } 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign { $2\data_r4__msr_ok$next[0:0]$14087 $2\data_r4__msr$next[63:0]$14086 } 65'00000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\data_r4__msr$next[63:0]$14294 $1\data_r4__msr$next[63:0]$14292
- assign $2\data_r4__msr_ok$next[0:0]$14295 $1\data_r4__msr_ok$next[0:0]$14293
+ assign $2\data_r4__msr$next[63:0]$14086 $1\data_r4__msr$next[63:0]$14084
+ assign $2\data_r4__msr_ok$next[0:0]$14087 $1\data_r4__msr_ok$next[0:0]$14085
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \coresync_rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\data_r4__msr_ok$next[0:0]$14296 1'0
+ assign $3\data_r4__msr_ok$next[0:0]$14088 1'0
case
- assign $3\data_r4__msr_ok$next[0:0]$14296 $2\data_r4__msr_ok$next[0:0]$14295
+ assign $3\data_r4__msr_ok$next[0:0]$14088 $2\data_r4__msr_ok$next[0:0]$14087
end
sync always
- update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14290
- update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14291
+ update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14082
+ update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14083
end
- attribute \src "libresoc.v:201728.3-201737.6"
- process $proc$libresoc.v:201728$14297
+ attribute \src "libresoc.v:201624.3-201633.6"
+ process $proc$libresoc.v:201624$14089
assign { } { }
assign { } { }
- assign $0\src_r0$next[63:0]$14298 $1\src_r0$next[63:0]$14299
- attribute \src "libresoc.v:201729.5-201729.29"
+ assign $0\src_r0$next[63:0]$14090 $1\src_r0$next[63:0]$14091
+ attribute \src "libresoc.v:201625.5-201625.29"
switch \initial
- attribute \src "libresoc.v:201729.9-201729.17"
+ attribute \src "libresoc.v:201625.9-201625.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r0$next[63:0]$14299 \src1_i
+ assign $1\src_r0$next[63:0]$14091 \src1_i
case
- assign $1\src_r0$next[63:0]$14299 \src_r0
+ assign $1\src_r0$next[63:0]$14091 \src_r0
end
sync always
- update \src_r0$next $0\src_r0$next[63:0]$14298
+ update \src_r0$next $0\src_r0$next[63:0]$14090
end
- attribute \src "libresoc.v:201738.3-201747.6"
- process $proc$libresoc.v:201738$14300
+ attribute \src "libresoc.v:201634.3-201643.6"
+ process $proc$libresoc.v:201634$14092
assign { } { }
assign { } { }
- assign $0\src_r1$next[63:0]$14301 $1\src_r1$next[63:0]$14302
- attribute \src "libresoc.v:201739.5-201739.29"
+ assign $0\src_r1$next[63:0]$14093 $1\src_r1$next[63:0]$14094
+ attribute \src "libresoc.v:201635.5-201635.29"
switch \initial
- attribute \src "libresoc.v:201739.9-201739.17"
+ attribute \src "libresoc.v:201635.9-201635.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r1$next[63:0]$14302 \src2_i
+ assign $1\src_r1$next[63:0]$14094 \src2_i
case
- assign $1\src_r1$next[63:0]$14302 \src_r1
+ assign $1\src_r1$next[63:0]$14094 \src_r1
end
sync always
- update \src_r1$next $0\src_r1$next[63:0]$14301
+ update \src_r1$next $0\src_r1$next[63:0]$14093
end
- attribute \src "libresoc.v:201748.3-201757.6"
- process $proc$libresoc.v:201748$14303
+ attribute \src "libresoc.v:201644.3-201653.6"
+ process $proc$libresoc.v:201644$14095
assign { } { }
assign { } { }
- assign $0\src_r2$next[63:0]$14304 $1\src_r2$next[63:0]$14305
- attribute \src "libresoc.v:201749.5-201749.29"
+ assign $0\src_r2$next[63:0]$14096 $1\src_r2$next[63:0]$14097
+ attribute \src "libresoc.v:201645.5-201645.29"
switch \initial
- attribute \src "libresoc.v:201749.9-201749.17"
+ attribute \src "libresoc.v:201645.9-201645.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r2$next[63:0]$14305 \src3_i
+ assign $1\src_r2$next[63:0]$14097 \src3_i
case
- assign $1\src_r2$next[63:0]$14305 \src_r2
+ assign $1\src_r2$next[63:0]$14097 \src_r2
end
sync always
- update \src_r2$next $0\src_r2$next[63:0]$14304
+ update \src_r2$next $0\src_r2$next[63:0]$14096
end
- attribute \src "libresoc.v:201758.3-201767.6"
- process $proc$libresoc.v:201758$14306
+ attribute \src "libresoc.v:201654.3-201663.6"
+ process $proc$libresoc.v:201654$14098
assign { } { }
assign { } { }
- assign $0\src_r3$next[63:0]$14307 $1\src_r3$next[63:0]$14308
- attribute \src "libresoc.v:201759.5-201759.29"
+ assign $0\src_r3$next[63:0]$14099 $1\src_r3$next[63:0]$14100
+ attribute \src "libresoc.v:201655.5-201655.29"
switch \initial
- attribute \src "libresoc.v:201759.9-201759.17"
+ attribute \src "libresoc.v:201655.9-201655.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\src_r3$next[63:0]$14308 \src4_i
+ assign $1\src_r3$next[63:0]$14100 \src4_i
case
- assign $1\src_r3$next[63:0]$14308 \src_r3
+ assign $1\src_r3$next[63:0]$14100 \src_r3
end
sync always
- update \src_r3$next $0\src_r3$next[63:0]$14307
+ update \src_r3$next $0\src_r3$next[63:0]$14099
end
- attribute \src "libresoc.v:201768.3-201776.6"
- process $proc$libresoc.v:201768$14309
+ attribute \src "libresoc.v:201664.3-201672.6"
+ process $proc$libresoc.v:201664$14101
assign { } { }
assign { } { }
- assign $0\alui_l_r_alui$next[0:0]$14310 $1\alui_l_r_alui$next[0:0]$14311
- attribute \src "libresoc.v:201769.5-201769.29"
+ assign $0\alui_l_r_alui$next[0:0]$14102 $1\alui_l_r_alui$next[0:0]$14103
+ attribute \src "libresoc.v:201665.5-201665.29"
switch \initial
- attribute \src "libresoc.v:201769.9-201769.17"
+ attribute \src "libresoc.v:201665.9-201665.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alui_l_r_alui$next[0:0]$14311 1'1
+ assign $1\alui_l_r_alui$next[0:0]$14103 1'1
case
- assign $1\alui_l_r_alui$next[0:0]$14311 \$89
+ assign $1\alui_l_r_alui$next[0:0]$14103 \$89
end
sync always
- update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14310
+ update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14102
end
- attribute \src "libresoc.v:201777.3-201785.6"
- process $proc$libresoc.v:201777$14312
+ attribute \src "libresoc.v:201673.3-201681.6"
+ process $proc$libresoc.v:201673$14104
assign { } { }
assign { } { }
- assign $0\alu_l_r_alu$next[0:0]$14313 $1\alu_l_r_alu$next[0:0]$14314
- attribute \src "libresoc.v:201778.5-201778.29"
+ assign $0\alu_l_r_alu$next[0:0]$14105 $1\alu_l_r_alu$next[0:0]$14106
+ attribute \src "libresoc.v:201674.5-201674.29"
switch \initial
- attribute \src "libresoc.v:201778.9-201778.17"
+ attribute \src "libresoc.v:201674.9-201674.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\alu_l_r_alu$next[0:0]$14314 1'1
+ assign $1\alu_l_r_alu$next[0:0]$14106 1'1
case
- assign $1\alu_l_r_alu$next[0:0]$14314 \$91
+ assign $1\alu_l_r_alu$next[0:0]$14106 \$91
end
sync always
- update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14313
+ update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14105
end
- attribute \src "libresoc.v:201786.3-201795.6"
- process $proc$libresoc.v:201786$14315
+ attribute \src "libresoc.v:201682.3-201691.6"
+ process $proc$libresoc.v:201682$14107
assign { } { }
assign { } { }
assign $0\dest1_o[63:0] $1\dest1_o[63:0]
- attribute \src "libresoc.v:201787.5-201787.29"
+ attribute \src "libresoc.v:201683.5-201683.29"
switch \initial
- attribute \src "libresoc.v:201787.9-201787.17"
+ attribute \src "libresoc.v:201683.9-201683.17"
case 1'1
case
end
sync always
update \dest1_o $0\dest1_o[63:0]
end
- attribute \src "libresoc.v:201796.3-201805.6"
- process $proc$libresoc.v:201796$14316
+ attribute \src "libresoc.v:201692.3-201701.6"
+ process $proc$libresoc.v:201692$14108
assign { } { }
assign { } { }
assign $0\dest2_o[63:0] $1\dest2_o[63:0]
- attribute \src "libresoc.v:201797.5-201797.29"
+ attribute \src "libresoc.v:201693.5-201693.29"
switch \initial
- attribute \src "libresoc.v:201797.9-201797.17"
+ attribute \src "libresoc.v:201693.9-201693.17"
case 1'1
case
end
sync always
update \dest2_o $0\dest2_o[63:0]
end
- attribute \src "libresoc.v:201806.3-201815.6"
- process $proc$libresoc.v:201806$14317
+ attribute \src "libresoc.v:201702.3-201711.6"
+ process $proc$libresoc.v:201702$14109
assign { } { }
assign { } { }
assign $0\dest3_o[63:0] $1\dest3_o[63:0]
- attribute \src "libresoc.v:201807.5-201807.29"
+ attribute \src "libresoc.v:201703.5-201703.29"
switch \initial
- attribute \src "libresoc.v:201807.9-201807.17"
+ attribute \src "libresoc.v:201703.9-201703.17"
case 1'1
case
end
sync always
update \dest3_o $0\dest3_o[63:0]
end
- attribute \src "libresoc.v:201816.3-201825.6"
- process $proc$libresoc.v:201816$14318
+ attribute \src "libresoc.v:201712.3-201721.6"
+ process $proc$libresoc.v:201712$14110
assign { } { }
assign { } { }
assign $0\dest4_o[63:0] $1\dest4_o[63:0]
- attribute \src "libresoc.v:201817.5-201817.29"
+ attribute \src "libresoc.v:201713.5-201713.29"
switch \initial
- attribute \src "libresoc.v:201817.9-201817.17"
+ attribute \src "libresoc.v:201713.9-201713.17"
case 1'1
case
end
sync always
update \dest4_o $0\dest4_o[63:0]
end
- attribute \src "libresoc.v:201826.3-201835.6"
- process $proc$libresoc.v:201826$14319
+ attribute \src "libresoc.v:201722.3-201731.6"
+ process $proc$libresoc.v:201722$14111
assign { } { }
assign { } { }
assign $0\dest5_o[63:0] $1\dest5_o[63:0]
- attribute \src "libresoc.v:201827.5-201827.29"
+ attribute \src "libresoc.v:201723.5-201723.29"
switch \initial
- attribute \src "libresoc.v:201827.9-201827.17"
+ attribute \src "libresoc.v:201723.9-201723.17"
case 1'1
case
end
sync always
update \dest5_o $0\dest5_o[63:0]
end
- attribute \src "libresoc.v:201836.3-201844.6"
- process $proc$libresoc.v:201836$14320
+ attribute \src "libresoc.v:201732.3-201740.6"
+ process $proc$libresoc.v:201732$14112
assign { } { }
assign { } { }
- assign $0\prev_wr_go$next[4:0]$14321 $1\prev_wr_go$next[4:0]$14322
- attribute \src "libresoc.v:201837.5-201837.29"
+ assign $0\prev_wr_go$next[4:0]$14113 $1\prev_wr_go$next[4:0]$14114
+ attribute \src "libresoc.v:201733.5-201733.29"
switch \initial
- attribute \src "libresoc.v:201837.9-201837.17"
+ attribute \src "libresoc.v:201733.9-201733.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\prev_wr_go$next[4:0]$14322 5'00000
- case
- assign $1\prev_wr_go$next[4:0]$14322 \$21
- end
- sync always
- update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14321
- end
- connect \$5 $reduce_and$libresoc.v:201284$14108_Y
- connect \$99 $and$libresoc.v:201285$14109_Y
- connect \$101 $and$libresoc.v:201286$14110_Y
- connect \$103 $and$libresoc.v:201287$14111_Y
- connect \$105 $and$libresoc.v:201288$14112_Y
- connect \$107 $and$libresoc.v:201289$14113_Y
- connect \$109 $and$libresoc.v:201290$14114_Y
- connect \$111 $and$libresoc.v:201291$14115_Y
- connect \$113 $and$libresoc.v:201292$14116_Y
- connect \$115 $and$libresoc.v:201293$14117_Y
- connect \$117 $and$libresoc.v:201294$14118_Y
- connect \$11 $and$libresoc.v:201295$14119_Y
- connect \$119 $and$libresoc.v:201296$14120_Y
- connect \$121 $and$libresoc.v:201297$14121_Y
- connect \$123 $and$libresoc.v:201298$14122_Y
- connect \$13 $not$libresoc.v:201299$14123_Y
- connect \$15 $and$libresoc.v:201300$14124_Y
- connect \$17 $not$libresoc.v:201301$14125_Y
- connect \$19 $and$libresoc.v:201302$14126_Y
- connect \$21 $and$libresoc.v:201303$14127_Y
- connect \$25 $not$libresoc.v:201304$14128_Y
- connect \$27 $and$libresoc.v:201305$14129_Y
- connect \$24 $reduce_or$libresoc.v:201306$14130_Y
- connect \$23 $not$libresoc.v:201307$14131_Y
- connect \$31 $and$libresoc.v:201308$14132_Y
- connect \$33 $reduce_or$libresoc.v:201309$14133_Y
- connect \$35 $reduce_or$libresoc.v:201310$14134_Y
- connect \$37 $or$libresoc.v:201311$14135_Y
- connect \$3 $and$libresoc.v:201312$14136_Y
- connect \$39 $not$libresoc.v:201313$14137_Y
- connect \$41 $and$libresoc.v:201314$14138_Y
- connect \$43 $and$libresoc.v:201315$14139_Y
- connect \$45 $eq$libresoc.v:201316$14140_Y
- connect \$47 $and$libresoc.v:201317$14141_Y
- connect \$49 $eq$libresoc.v:201318$14142_Y
- connect \$51 $and$libresoc.v:201319$14143_Y
- connect \$53 $and$libresoc.v:201320$14144_Y
- connect \$55 $and$libresoc.v:201321$14145_Y
- connect \$57 $or$libresoc.v:201322$14146_Y
- connect \$59 $or$libresoc.v:201323$14147_Y
- connect \$61 $or$libresoc.v:201324$14148_Y
- connect \$63 $or$libresoc.v:201325$14149_Y
- connect \$65 $and$libresoc.v:201326$14150_Y
- connect \$67 $and$libresoc.v:201327$14151_Y
- connect \$6 $not$libresoc.v:201328$14152_Y
- connect \$69 $or$libresoc.v:201329$14153_Y
- connect \$71 $and$libresoc.v:201330$14154_Y
- connect \$73 $and$libresoc.v:201331$14155_Y
- connect \$75 $and$libresoc.v:201332$14156_Y
- connect \$77 $and$libresoc.v:201333$14157_Y
- connect \$79 $and$libresoc.v:201334$14158_Y
- connect \$81 $ternary$libresoc.v:201335$14159_Y
- connect \$83 $ternary$libresoc.v:201336$14160_Y
- connect \$85 $ternary$libresoc.v:201337$14161_Y
- connect \$87 $ternary$libresoc.v:201338$14162_Y
- connect \$8 $or$libresoc.v:201339$14163_Y
- connect \$89 $and$libresoc.v:201340$14164_Y
- connect \$91 $and$libresoc.v:201341$14165_Y
- connect \$93 $and$libresoc.v:201342$14166_Y
- connect \$95 $and$libresoc.v:201343$14167_Y
- connect \$97 $not$libresoc.v:201344$14168_Y
+ assign $1\prev_wr_go$next[4:0]$14114 5'00000
+ case
+ assign $1\prev_wr_go$next[4:0]$14114 \$21
+ end
+ sync always
+ update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14113
+ end
+ connect \$5 $reduce_and$libresoc.v:201180$13900_Y
+ connect \$99 $and$libresoc.v:201181$13901_Y
+ connect \$101 $and$libresoc.v:201182$13902_Y
+ connect \$103 $and$libresoc.v:201183$13903_Y
+ connect \$105 $and$libresoc.v:201184$13904_Y
+ connect \$107 $and$libresoc.v:201185$13905_Y
+ connect \$109 $and$libresoc.v:201186$13906_Y
+ connect \$111 $and$libresoc.v:201187$13907_Y
+ connect \$113 $and$libresoc.v:201188$13908_Y
+ connect \$115 $and$libresoc.v:201189$13909_Y
+ connect \$117 $and$libresoc.v:201190$13910_Y
+ connect \$11 $and$libresoc.v:201191$13911_Y
+ connect \$119 $and$libresoc.v:201192$13912_Y
+ connect \$121 $and$libresoc.v:201193$13913_Y
+ connect \$123 $and$libresoc.v:201194$13914_Y
+ connect \$13 $not$libresoc.v:201195$13915_Y
+ connect \$15 $and$libresoc.v:201196$13916_Y
+ connect \$17 $not$libresoc.v:201197$13917_Y
+ connect \$19 $and$libresoc.v:201198$13918_Y
+ connect \$21 $and$libresoc.v:201199$13919_Y
+ connect \$25 $not$libresoc.v:201200$13920_Y
+ connect \$27 $and$libresoc.v:201201$13921_Y
+ connect \$24 $reduce_or$libresoc.v:201202$13922_Y
+ connect \$23 $not$libresoc.v:201203$13923_Y
+ connect \$31 $and$libresoc.v:201204$13924_Y
+ connect \$33 $reduce_or$libresoc.v:201205$13925_Y
+ connect \$35 $reduce_or$libresoc.v:201206$13926_Y
+ connect \$37 $or$libresoc.v:201207$13927_Y
+ connect \$3 $and$libresoc.v:201208$13928_Y
+ connect \$39 $not$libresoc.v:201209$13929_Y
+ connect \$41 $and$libresoc.v:201210$13930_Y
+ connect \$43 $and$libresoc.v:201211$13931_Y
+ connect \$45 $eq$libresoc.v:201212$13932_Y
+ connect \$47 $and$libresoc.v:201213$13933_Y
+ connect \$49 $eq$libresoc.v:201214$13934_Y
+ connect \$51 $and$libresoc.v:201215$13935_Y
+ connect \$53 $and$libresoc.v:201216$13936_Y
+ connect \$55 $and$libresoc.v:201217$13937_Y
+ connect \$57 $or$libresoc.v:201218$13938_Y
+ connect \$59 $or$libresoc.v:201219$13939_Y
+ connect \$61 $or$libresoc.v:201220$13940_Y
+ connect \$63 $or$libresoc.v:201221$13941_Y
+ connect \$65 $and$libresoc.v:201222$13942_Y
+ connect \$67 $and$libresoc.v:201223$13943_Y
+ connect \$6 $not$libresoc.v:201224$13944_Y
+ connect \$69 $or$libresoc.v:201225$13945_Y
+ connect \$71 $and$libresoc.v:201226$13946_Y
+ connect \$73 $and$libresoc.v:201227$13947_Y
+ connect \$75 $and$libresoc.v:201228$13948_Y
+ connect \$77 $and$libresoc.v:201229$13949_Y
+ connect \$79 $and$libresoc.v:201230$13950_Y
+ connect \$81 $ternary$libresoc.v:201231$13951_Y
+ connect \$83 $ternary$libresoc.v:201232$13952_Y
+ connect \$85 $ternary$libresoc.v:201233$13953_Y
+ connect \$87 $ternary$libresoc.v:201234$13954_Y
+ connect \$8 $or$libresoc.v:201235$13955_Y
+ connect \$89 $and$libresoc.v:201236$13956_Y
+ connect \$91 $and$libresoc.v:201237$13957_Y
+ connect \$93 $and$libresoc.v:201238$13958_Y
+ connect \$95 $and$libresoc.v:201239$13959_Y
+ connect \$97 $not$libresoc.v:201240$13960_Y
connect \cu_go_die_i 1'0
connect \cu_shadown_i 1'1
connect \cu_wr__rel_o \$113
connect \all_rd_dly$next \all_rd
connect \all_rd \$11
end
-attribute \src "libresoc.v:201878.1-201936.10"
+attribute \src "libresoc.v:201774.1-201832.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l"
attribute \generator "nMigen"
module \upd_l
- attribute \src "libresoc.v:201879.7-201879.20"
+ attribute \src "libresoc.v:201775.7-201775.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:201924.3-201932.6"
- wire $0\q_int$next[0:0]$14372
- attribute \src "libresoc.v:201922.3-201923.27"
+ attribute \src "libresoc.v:201820.3-201828.6"
+ wire $0\q_int$next[0:0]$14164
+ attribute \src "libresoc.v:201818.3-201819.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:201924.3-201932.6"
- wire $1\q_int$next[0:0]$14373
- attribute \src "libresoc.v:201901.7-201901.19"
+ attribute \src "libresoc.v:201820.3-201828.6"
+ wire $1\q_int$next[0:0]$14165
+ attribute \src "libresoc.v:201797.7-201797.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:201914.17-201914.96"
- wire $and$libresoc.v:201914$14362_Y
- attribute \src "libresoc.v:201919.17-201919.96"
- wire $and$libresoc.v:201919$14367_Y
- attribute \src "libresoc.v:201916.18-201916.93"
- wire $not$libresoc.v:201916$14364_Y
- attribute \src "libresoc.v:201918.17-201918.92"
- wire $not$libresoc.v:201918$14366_Y
- attribute \src "libresoc.v:201921.17-201921.92"
- wire $not$libresoc.v:201921$14369_Y
- attribute \src "libresoc.v:201915.18-201915.98"
- wire $or$libresoc.v:201915$14363_Y
- attribute \src "libresoc.v:201917.18-201917.99"
- wire $or$libresoc.v:201917$14365_Y
- attribute \src "libresoc.v:201920.17-201920.97"
- wire $or$libresoc.v:201920$14368_Y
+ attribute \src "libresoc.v:201810.17-201810.96"
+ wire $and$libresoc.v:201810$14154_Y
+ attribute \src "libresoc.v:201815.17-201815.96"
+ wire $and$libresoc.v:201815$14159_Y
+ attribute \src "libresoc.v:201812.18-201812.93"
+ wire $not$libresoc.v:201812$14156_Y
+ attribute \src "libresoc.v:201814.17-201814.92"
+ wire $not$libresoc.v:201814$14158_Y
+ attribute \src "libresoc.v:201817.17-201817.92"
+ wire $not$libresoc.v:201817$14161_Y
+ attribute \src "libresoc.v:201811.18-201811.98"
+ wire $or$libresoc.v:201811$14155_Y
+ attribute \src "libresoc.v:201813.18-201813.99"
+ wire $or$libresoc.v:201813$14157_Y
+ attribute \src "libresoc.v:201816.17-201816.97"
+ wire $or$libresoc.v:201816$14160_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:201879.7-201879.15"
+ attribute \src "libresoc.v:201775.7-201775.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_upd
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:201914$14362
+ cell $and $and$libresoc.v:201810$14154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:201914$14362_Y
+ connect \Y $and$libresoc.v:201810$14154_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:201919$14367
+ cell $and $and$libresoc.v:201815$14159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:201919$14367_Y
+ connect \Y $and$libresoc.v:201815$14159_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:201916$14364
+ cell $not $not$libresoc.v:201812$14156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_upd
- connect \Y $not$libresoc.v:201916$14364_Y
+ connect \Y $not$libresoc.v:201812$14156_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:201918$14366
+ cell $not $not$libresoc.v:201814$14158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:201918$14366_Y
+ connect \Y $not$libresoc.v:201814$14158_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:201921$14369
+ cell $not $not$libresoc.v:201817$14161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_upd
- connect \Y $not$libresoc.v:201921$14369_Y
+ connect \Y $not$libresoc.v:201817$14161_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:201915$14363
+ cell $or $or$libresoc.v:201811$14155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_upd
- connect \Y $or$libresoc.v:201915$14363_Y
+ connect \Y $or$libresoc.v:201811$14155_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:201917$14365
+ cell $or $or$libresoc.v:201813$14157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_upd
connect \B \q_int
- connect \Y $or$libresoc.v:201917$14365_Y
+ connect \Y $or$libresoc.v:201813$14157_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:201920$14368
+ cell $or $or$libresoc.v:201816$14160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_upd
- connect \Y $or$libresoc.v:201920$14368_Y
+ connect \Y $or$libresoc.v:201816$14160_Y
end
- attribute \src "libresoc.v:201879.7-201879.20"
- process $proc$libresoc.v:201879$14374
+ attribute \src "libresoc.v:201775.7-201775.20"
+ process $proc$libresoc.v:201775$14166
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:201901.7-201901.19"
- process $proc$libresoc.v:201901$14375
+ attribute \src "libresoc.v:201797.7-201797.19"
+ process $proc$libresoc.v:201797$14167
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:201922.3-201923.27"
- process $proc$libresoc.v:201922$14370
+ attribute \src "libresoc.v:201818.3-201819.27"
+ process $proc$libresoc.v:201818$14162
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:201924.3-201932.6"
- process $proc$libresoc.v:201924$14371
+ attribute \src "libresoc.v:201820.3-201828.6"
+ process $proc$libresoc.v:201820$14163
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14372 $1\q_int$next[0:0]$14373
- attribute \src "libresoc.v:201925.5-201925.29"
+ assign $0\q_int$next[0:0]$14164 $1\q_int$next[0:0]$14165
+ attribute \src "libresoc.v:201821.5-201821.29"
switch \initial
- attribute \src "libresoc.v:201925.9-201925.17"
+ attribute \src "libresoc.v:201821.9-201821.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14373 1'0
+ assign $1\q_int$next[0:0]$14165 1'0
case
- assign $1\q_int$next[0:0]$14373 \$5
+ assign $1\q_int$next[0:0]$14165 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14372
+ update \q_int$next $0\q_int$next[0:0]$14164
end
- connect \$9 $and$libresoc.v:201914$14362_Y
- connect \$11 $or$libresoc.v:201915$14363_Y
- connect \$13 $not$libresoc.v:201916$14364_Y
- connect \$15 $or$libresoc.v:201917$14365_Y
- connect \$1 $not$libresoc.v:201918$14366_Y
- connect \$3 $and$libresoc.v:201919$14367_Y
- connect \$5 $or$libresoc.v:201920$14368_Y
- connect \$7 $not$libresoc.v:201921$14369_Y
+ connect \$9 $and$libresoc.v:201810$14154_Y
+ connect \$11 $or$libresoc.v:201811$14155_Y
+ connect \$13 $not$libresoc.v:201812$14156_Y
+ connect \$15 $or$libresoc.v:201813$14157_Y
+ connect \$1 $not$libresoc.v:201814$14158_Y
+ connect \$3 $and$libresoc.v:201815$14159_Y
+ connect \$5 $or$libresoc.v:201816$14160_Y
+ connect \$7 $not$libresoc.v:201817$14161_Y
connect \qlq_upd \$15
connect \qn_upd \$13
connect \q_upd \$11
end
-attribute \src "libresoc.v:201940.1-201998.10"
+attribute \src "libresoc.v:201836.1-201894.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l"
attribute \generator "nMigen"
module \valid_l
- attribute \src "libresoc.v:201941.7-201941.20"
+ attribute \src "libresoc.v:201837.7-201837.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:201986.3-201994.6"
- wire $0\q_int$next[0:0]$14386
- attribute \src "libresoc.v:201984.3-201985.27"
+ attribute \src "libresoc.v:201882.3-201890.6"
+ wire $0\q_int$next[0:0]$14178
+ attribute \src "libresoc.v:201880.3-201881.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:201986.3-201994.6"
- wire $1\q_int$next[0:0]$14387
- attribute \src "libresoc.v:201963.7-201963.19"
+ attribute \src "libresoc.v:201882.3-201890.6"
+ wire $1\q_int$next[0:0]$14179
+ attribute \src "libresoc.v:201859.7-201859.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:201976.17-201976.96"
- wire $and$libresoc.v:201976$14376_Y
- attribute \src "libresoc.v:201981.17-201981.96"
- wire $and$libresoc.v:201981$14381_Y
- attribute \src "libresoc.v:201978.18-201978.95"
- wire $not$libresoc.v:201978$14378_Y
- attribute \src "libresoc.v:201980.17-201980.94"
- wire $not$libresoc.v:201980$14380_Y
- attribute \src "libresoc.v:201983.17-201983.94"
- wire $not$libresoc.v:201983$14383_Y
- attribute \src "libresoc.v:201977.18-201977.100"
- wire $or$libresoc.v:201977$14377_Y
- attribute \src "libresoc.v:201979.18-201979.101"
- wire $or$libresoc.v:201979$14379_Y
- attribute \src "libresoc.v:201982.17-201982.99"
- wire $or$libresoc.v:201982$14382_Y
+ attribute \src "libresoc.v:201872.17-201872.96"
+ wire $and$libresoc.v:201872$14168_Y
+ attribute \src "libresoc.v:201877.17-201877.96"
+ wire $and$libresoc.v:201877$14173_Y
+ attribute \src "libresoc.v:201874.18-201874.95"
+ wire $not$libresoc.v:201874$14170_Y
+ attribute \src "libresoc.v:201876.17-201876.94"
+ wire $not$libresoc.v:201876$14172_Y
+ attribute \src "libresoc.v:201879.17-201879.94"
+ wire $not$libresoc.v:201879$14175_Y
+ attribute \src "libresoc.v:201873.18-201873.100"
+ wire $or$libresoc.v:201873$14169_Y
+ attribute \src "libresoc.v:201875.18-201875.101"
+ wire $or$libresoc.v:201875$14171_Y
+ attribute \src "libresoc.v:201878.17-201878.99"
+ wire $or$libresoc.v:201878$14174_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:201941.7-201941.15"
+ attribute \src "libresoc.v:201837.7-201837.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_valid
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:201976$14376
+ cell $and $and$libresoc.v:201872$14168
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:201976$14376_Y
+ connect \Y $and$libresoc.v:201872$14168_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:201981$14381
+ cell $and $and$libresoc.v:201877$14173
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:201981$14381_Y
+ connect \Y $and$libresoc.v:201877$14173_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:201978$14378
+ cell $not $not$libresoc.v:201874$14170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_valid
- connect \Y $not$libresoc.v:201978$14378_Y
+ connect \Y $not$libresoc.v:201874$14170_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:201980$14380
+ cell $not $not$libresoc.v:201876$14172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:201980$14380_Y
+ connect \Y $not$libresoc.v:201876$14172_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:201983$14383
+ cell $not $not$libresoc.v:201879$14175
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_valid
- connect \Y $not$libresoc.v:201983$14383_Y
+ connect \Y $not$libresoc.v:201879$14175_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:201977$14377
+ cell $or $or$libresoc.v:201873$14169
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_valid
- connect \Y $or$libresoc.v:201977$14377_Y
+ connect \Y $or$libresoc.v:201873$14169_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:201979$14379
+ cell $or $or$libresoc.v:201875$14171
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_valid
connect \B \q_int
- connect \Y $or$libresoc.v:201979$14379_Y
+ connect \Y $or$libresoc.v:201875$14171_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:201982$14382
+ cell $or $or$libresoc.v:201878$14174
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_valid
- connect \Y $or$libresoc.v:201982$14382_Y
+ connect \Y $or$libresoc.v:201878$14174_Y
end
- attribute \src "libresoc.v:201941.7-201941.20"
- process $proc$libresoc.v:201941$14388
+ attribute \src "libresoc.v:201837.7-201837.20"
+ process $proc$libresoc.v:201837$14180
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:201963.7-201963.19"
- process $proc$libresoc.v:201963$14389
+ attribute \src "libresoc.v:201859.7-201859.19"
+ process $proc$libresoc.v:201859$14181
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:201984.3-201985.27"
- process $proc$libresoc.v:201984$14384
+ attribute \src "libresoc.v:201880.3-201881.27"
+ process $proc$libresoc.v:201880$14176
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:201986.3-201994.6"
- process $proc$libresoc.v:201986$14385
+ attribute \src "libresoc.v:201882.3-201890.6"
+ process $proc$libresoc.v:201882$14177
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14386 $1\q_int$next[0:0]$14387
- attribute \src "libresoc.v:201987.5-201987.29"
+ assign $0\q_int$next[0:0]$14178 $1\q_int$next[0:0]$14179
+ attribute \src "libresoc.v:201883.5-201883.29"
switch \initial
- attribute \src "libresoc.v:201987.9-201987.17"
+ attribute \src "libresoc.v:201883.9-201883.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14387 1'0
+ assign $1\q_int$next[0:0]$14179 1'0
case
- assign $1\q_int$next[0:0]$14387 \$5
+ assign $1\q_int$next[0:0]$14179 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14386
+ update \q_int$next $0\q_int$next[0:0]$14178
end
- connect \$9 $and$libresoc.v:201976$14376_Y
- connect \$11 $or$libresoc.v:201977$14377_Y
- connect \$13 $not$libresoc.v:201978$14378_Y
- connect \$15 $or$libresoc.v:201979$14379_Y
- connect \$1 $not$libresoc.v:201980$14380_Y
- connect \$3 $and$libresoc.v:201981$14381_Y
- connect \$5 $or$libresoc.v:201982$14382_Y
- connect \$7 $not$libresoc.v:201983$14383_Y
+ connect \$9 $and$libresoc.v:201872$14168_Y
+ connect \$11 $or$libresoc.v:201873$14169_Y
+ connect \$13 $not$libresoc.v:201874$14170_Y
+ connect \$15 $or$libresoc.v:201875$14171_Y
+ connect \$1 $not$libresoc.v:201876$14172_Y
+ connect \$3 $and$libresoc.v:201877$14173_Y
+ connect \$5 $or$libresoc.v:201878$14174_Y
+ connect \$7 $not$libresoc.v:201879$14175_Y
connect \qlq_valid \$15
connect \qn_valid \$13
connect \q_valid \$11
end
-attribute \src "libresoc.v:202002.1-202060.10"
+attribute \src "libresoc.v:201898.1-201956.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l"
attribute \generator "nMigen"
module \wri_l
- attribute \src "libresoc.v:202003.7-202003.20"
+ attribute \src "libresoc.v:201899.7-201899.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:202048.3-202056.6"
- wire $0\q_int$next[0:0]$14400
- attribute \src "libresoc.v:202046.3-202047.27"
+ attribute \src "libresoc.v:201944.3-201952.6"
+ wire $0\q_int$next[0:0]$14192
+ attribute \src "libresoc.v:201942.3-201943.27"
wire $0\q_int[0:0]
- attribute \src "libresoc.v:202048.3-202056.6"
- wire $1\q_int$next[0:0]$14401
- attribute \src "libresoc.v:202025.7-202025.19"
+ attribute \src "libresoc.v:201944.3-201952.6"
+ wire $1\q_int$next[0:0]$14193
+ attribute \src "libresoc.v:201921.7-201921.19"
wire $1\q_int[0:0]
- attribute \src "libresoc.v:202038.17-202038.96"
- wire $and$libresoc.v:202038$14390_Y
- attribute \src "libresoc.v:202043.17-202043.96"
- wire $and$libresoc.v:202043$14395_Y
- attribute \src "libresoc.v:202040.18-202040.93"
- wire $not$libresoc.v:202040$14392_Y
- attribute \src "libresoc.v:202042.17-202042.92"
- wire $not$libresoc.v:202042$14394_Y
- attribute \src "libresoc.v:202045.17-202045.92"
- wire $not$libresoc.v:202045$14397_Y
- attribute \src "libresoc.v:202039.18-202039.98"
- wire $or$libresoc.v:202039$14391_Y
- attribute \src "libresoc.v:202041.18-202041.99"
- wire $or$libresoc.v:202041$14393_Y
- attribute \src "libresoc.v:202044.17-202044.97"
- wire $or$libresoc.v:202044$14396_Y
+ attribute \src "libresoc.v:201934.17-201934.96"
+ wire $and$libresoc.v:201934$14182_Y
+ attribute \src "libresoc.v:201939.17-201939.96"
+ wire $and$libresoc.v:201939$14187_Y
+ attribute \src "libresoc.v:201936.18-201936.93"
+ wire $not$libresoc.v:201936$14184_Y
+ attribute \src "libresoc.v:201938.17-201938.92"
+ wire $not$libresoc.v:201938$14186_Y
+ attribute \src "libresoc.v:201941.17-201941.92"
+ wire $not$libresoc.v:201941$14189_Y
+ attribute \src "libresoc.v:201935.18-201935.98"
+ wire $or$libresoc.v:201935$14183_Y
+ attribute \src "libresoc.v:201937.18-201937.99"
+ wire $or$libresoc.v:201937$14185_Y
+ attribute \src "libresoc.v:201940.17-201940.97"
+ wire $or$libresoc.v:201940$14188_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
wire \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 5 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
- attribute \src "libresoc.v:202003.7-202003.15"
+ attribute \src "libresoc.v:201899.7-201899.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire input 2 \s_wri
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $and $and$libresoc.v:202038$14390
+ cell $and $and$libresoc.v:201934$14182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$7
- connect \Y $and$libresoc.v:202038$14390_Y
+ connect \Y $and$libresoc.v:201934$14182_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $and $and$libresoc.v:202043$14395
+ cell $and $and$libresoc.v:201939$14187
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_int
connect \B \$1
- connect \Y $and$libresoc.v:202043$14395_Y
+ connect \Y $and$libresoc.v:201939$14187_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80"
- cell $not $not$libresoc.v:202040$14392
+ cell $not $not$libresoc.v:201936$14184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \q_wri
- connect \Y $not$libresoc.v:202040$14392_Y
+ connect \Y $not$libresoc.v:201936$14184_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $not $not$libresoc.v:202042$14394
+ cell $not $not$libresoc.v:201938$14186
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:202042$14394_Y
+ connect \Y $not$libresoc.v:201938$14186_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $not $not$libresoc.v:202045$14397
+ cell $not $not$libresoc.v:201941$14189
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \r_wri
- connect \Y $not$libresoc.v:202045$14397_Y
+ connect \Y $not$libresoc.v:201941$14189_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79"
- cell $or $or$libresoc.v:202039$14391
+ cell $or $or$libresoc.v:201935$14183
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$9
connect \B \s_wri
- connect \Y $or$libresoc.v:202039$14391_Y
+ connect \Y $or$libresoc.v:201935$14183_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81"
- cell $or $or$libresoc.v:202041$14393
+ cell $or $or$libresoc.v:201937$14185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \q_wri
connect \B \q_int
- connect \Y $or$libresoc.v:202041$14393_Y
+ connect \Y $or$libresoc.v:201937$14185_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75"
- cell $or $or$libresoc.v:202044$14396
+ cell $or $or$libresoc.v:201940$14188
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$3
connect \B \s_wri
- connect \Y $or$libresoc.v:202044$14396_Y
+ connect \Y $or$libresoc.v:201940$14188_Y
end
- attribute \src "libresoc.v:202003.7-202003.20"
- process $proc$libresoc.v:202003$14402
+ attribute \src "libresoc.v:201899.7-201899.20"
+ process $proc$libresoc.v:201899$14194
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:202025.7-202025.19"
- process $proc$libresoc.v:202025$14403
+ attribute \src "libresoc.v:201921.7-201921.19"
+ process $proc$libresoc.v:201921$14195
assign { } { }
assign $1\q_int[0:0] 1'0
sync always
sync init
update \q_int $1\q_int[0:0]
end
- attribute \src "libresoc.v:202046.3-202047.27"
- process $proc$libresoc.v:202046$14398
+ attribute \src "libresoc.v:201942.3-201943.27"
+ process $proc$libresoc.v:201942$14190
assign { } { }
assign $0\q_int[0:0] \q_int$next
sync posedge \coresync_clk
update \q_int $0\q_int[0:0]
end
- attribute \src "libresoc.v:202048.3-202056.6"
- process $proc$libresoc.v:202048$14399
+ attribute \src "libresoc.v:201944.3-201952.6"
+ process $proc$libresoc.v:201944$14191
assign { } { }
assign { } { }
- assign $0\q_int$next[0:0]$14400 $1\q_int$next[0:0]$14401
- attribute \src "libresoc.v:202049.5-202049.29"
+ assign $0\q_int$next[0:0]$14192 $1\q_int$next[0:0]$14193
+ attribute \src "libresoc.v:201945.5-201945.29"
switch \initial
- attribute \src "libresoc.v:202049.9-202049.17"
+ attribute \src "libresoc.v:201945.9-201945.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\q_int$next[0:0]$14401 1'0
+ assign $1\q_int$next[0:0]$14193 1'0
case
- assign $1\q_int$next[0:0]$14401 \$5
+ assign $1\q_int$next[0:0]$14193 \$5
end
sync always
- update \q_int$next $0\q_int$next[0:0]$14400
+ update \q_int$next $0\q_int$next[0:0]$14192
end
- connect \$9 $and$libresoc.v:202038$14390_Y
- connect \$11 $or$libresoc.v:202039$14391_Y
- connect \$13 $not$libresoc.v:202040$14392_Y
- connect \$15 $or$libresoc.v:202041$14393_Y
- connect \$1 $not$libresoc.v:202042$14394_Y
- connect \$3 $and$libresoc.v:202043$14395_Y
- connect \$5 $or$libresoc.v:202044$14396_Y
- connect \$7 $not$libresoc.v:202045$14397_Y
+ connect \$9 $and$libresoc.v:201934$14182_Y
+ connect \$11 $or$libresoc.v:201935$14183_Y
+ connect \$13 $not$libresoc.v:201936$14184_Y
+ connect \$15 $or$libresoc.v:201937$14185_Y
+ connect \$1 $not$libresoc.v:201938$14186_Y
+ connect \$3 $and$libresoc.v:201939$14187_Y
+ connect \$5 $or$libresoc.v:201940$14188_Y
+ connect \$7 $not$libresoc.v:201941$14189_Y
connect \qlq_wri \$15
connect \qn_wri \$13
connect \q_wri \$11
end
-attribute \src "libresoc.v:202064.1-202130.10"
+attribute \src "libresoc.v:201960.1-202026.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a"
attribute \generator "nMigen"
module \wrpick_CR_cr_a
- attribute \src "libresoc.v:202109.17-202109.91"
- wire $not$libresoc.v:202109$14404_Y
- attribute \src "libresoc.v:202111.18-202111.93"
- wire $not$libresoc.v:202111$14406_Y
- attribute \src "libresoc.v:202113.18-202113.93"
- wire $not$libresoc.v:202113$14408_Y
- attribute \src "libresoc.v:202114.17-202114.89"
- wire width 6 $not$libresoc.v:202114$14409_Y
- attribute \src "libresoc.v:202116.18-202116.93"
- wire $not$libresoc.v:202116$14411_Y
- attribute \src "libresoc.v:202119.17-202119.91"
- wire $not$libresoc.v:202119$14414_Y
- attribute \src "libresoc.v:202110.18-202110.106"
- wire $reduce_or$libresoc.v:202110$14405_Y
- attribute \src "libresoc.v:202112.18-202112.106"
- wire $reduce_or$libresoc.v:202112$14407_Y
- attribute \src "libresoc.v:202115.18-202115.106"
- wire $reduce_or$libresoc.v:202115$14410_Y
- attribute \src "libresoc.v:202117.18-202117.90"
- wire $reduce_or$libresoc.v:202117$14412_Y
- attribute \src "libresoc.v:202118.17-202118.103"
- wire $reduce_or$libresoc.v:202118$14413_Y
- attribute \src "libresoc.v:202120.17-202120.105"
- wire $reduce_or$libresoc.v:202120$14415_Y
+ attribute \src "libresoc.v:202005.17-202005.91"
+ wire $not$libresoc.v:202005$14196_Y
+ attribute \src "libresoc.v:202007.18-202007.93"
+ wire $not$libresoc.v:202007$14198_Y
+ attribute \src "libresoc.v:202009.18-202009.93"
+ wire $not$libresoc.v:202009$14200_Y
+ attribute \src "libresoc.v:202010.17-202010.89"
+ wire width 6 $not$libresoc.v:202010$14201_Y
+ attribute \src "libresoc.v:202012.18-202012.93"
+ wire $not$libresoc.v:202012$14203_Y
+ attribute \src "libresoc.v:202015.17-202015.91"
+ wire $not$libresoc.v:202015$14206_Y
+ attribute \src "libresoc.v:202006.18-202006.106"
+ wire $reduce_or$libresoc.v:202006$14197_Y
+ attribute \src "libresoc.v:202008.18-202008.106"
+ wire $reduce_or$libresoc.v:202008$14199_Y
+ attribute \src "libresoc.v:202011.18-202011.106"
+ wire $reduce_or$libresoc.v:202011$14202_Y
+ attribute \src "libresoc.v:202013.18-202013.90"
+ wire $reduce_or$libresoc.v:202013$14204_Y
+ attribute \src "libresoc.v:202014.17-202014.103"
+ wire $reduce_or$libresoc.v:202014$14205_Y
+ attribute \src "libresoc.v:202016.17-202016.105"
+ wire $reduce_or$libresoc.v:202016$14207_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 6 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202109$14404
+ cell $not $not$libresoc.v:202005$14196
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202109$14404_Y
+ connect \Y $not$libresoc.v:202005$14196_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202111$14406
+ cell $not $not$libresoc.v:202007$14198
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:202111$14406_Y
+ connect \Y $not$libresoc.v:202007$14198_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202113$14408
+ cell $not $not$libresoc.v:202009$14200
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:202113$14408_Y
+ connect \Y $not$libresoc.v:202009$14200_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202114$14409
+ cell $not $not$libresoc.v:202010$14201
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \i
- connect \Y $not$libresoc.v:202114$14409_Y
+ connect \Y $not$libresoc.v:202010$14201_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202116$14411
+ cell $not $not$libresoc.v:202012$14203
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:202116$14411_Y
+ connect \Y $not$libresoc.v:202012$14203_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202119$14414
+ cell $not $not$libresoc.v:202015$14206
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202119$14414_Y
+ connect \Y $not$libresoc.v:202015$14206_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202110$14405
+ cell $reduce_or $reduce_or$libresoc.v:202006$14197
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:202110$14405_Y
+ connect \Y $reduce_or$libresoc.v:202006$14197_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202112$14407
+ cell $reduce_or $reduce_or$libresoc.v:202008$14199
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:202112$14407_Y
+ connect \Y $reduce_or$libresoc.v:202008$14199_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202115$14410
+ cell $reduce_or $reduce_or$libresoc.v:202011$14202
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:202115$14410_Y
+ connect \Y $reduce_or$libresoc.v:202011$14202_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202117$14412
+ cell $reduce_or $reduce_or$libresoc.v:202013$14204
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202117$14412_Y
+ connect \Y $reduce_or$libresoc.v:202013$14204_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202118$14413
+ cell $reduce_or $reduce_or$libresoc.v:202014$14205
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202118$14413_Y
+ connect \Y $reduce_or$libresoc.v:202014$14205_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202120$14415
+ cell $reduce_or $reduce_or$libresoc.v:202016$14207
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202120$14415_Y
- end
- connect \$7 $not$libresoc.v:202109$14404_Y
- connect \$12 $reduce_or$libresoc.v:202110$14405_Y
- connect \$11 $not$libresoc.v:202111$14406_Y
- connect \$16 $reduce_or$libresoc.v:202112$14407_Y
- connect \$15 $not$libresoc.v:202113$14408_Y
- connect \$1 $not$libresoc.v:202114$14409_Y
- connect \$20 $reduce_or$libresoc.v:202115$14410_Y
- connect \$19 $not$libresoc.v:202116$14411_Y
- connect \$23 $reduce_or$libresoc.v:202117$14412_Y
- connect \$4 $reduce_or$libresoc.v:202118$14413_Y
- connect \$3 $not$libresoc.v:202119$14414_Y
- connect \$8 $reduce_or$libresoc.v:202120$14415_Y
+ connect \Y $reduce_or$libresoc.v:202016$14207_Y
+ end
+ connect \$7 $not$libresoc.v:202005$14196_Y
+ connect \$12 $reduce_or$libresoc.v:202006$14197_Y
+ connect \$11 $not$libresoc.v:202007$14198_Y
+ connect \$16 $reduce_or$libresoc.v:202008$14199_Y
+ connect \$15 $not$libresoc.v:202009$14200_Y
+ connect \$1 $not$libresoc.v:202010$14201_Y
+ connect \$20 $reduce_or$libresoc.v:202011$14202_Y
+ connect \$19 $not$libresoc.v:202012$14203_Y
+ connect \$23 $reduce_or$libresoc.v:202013$14204_Y
+ connect \$4 $reduce_or$libresoc.v:202014$14205_Y
+ connect \$3 $not$libresoc.v:202015$14206_Y
+ connect \$8 $reduce_or$libresoc.v:202016$14207_Y
connect \en_o \$23
connect \o { \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t5 \$19
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202134.1-202155.10"
+attribute \src "libresoc.v:202030.1-202051.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr"
attribute \generator "nMigen"
module \wrpick_CR_full_cr
- attribute \src "libresoc.v:202149.17-202149.89"
- wire $not$libresoc.v:202149$14416_Y
- attribute \src "libresoc.v:202150.17-202150.89"
- wire $reduce_or$libresoc.v:202150$14417_Y
+ attribute \src "libresoc.v:202045.17-202045.89"
+ wire $not$libresoc.v:202045$14208_Y
+ attribute \src "libresoc.v:202046.17-202046.89"
+ wire $reduce_or$libresoc.v:202046$14209_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202149$14416
+ cell $not $not$libresoc.v:202045$14208
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:202149$14416_Y
+ connect \Y $not$libresoc.v:202045$14208_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202150$14417
+ cell $reduce_or $reduce_or$libresoc.v:202046$14209
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202150$14417_Y
+ connect \Y $reduce_or$libresoc.v:202046$14209_Y
end
- connect \$1 $not$libresoc.v:202149$14416_Y
- connect \$3 $reduce_or$libresoc.v:202150$14417_Y
+ connect \$1 $not$libresoc.v:202045$14208_Y
+ connect \$3 $reduce_or$libresoc.v:202046$14209_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:202159.1-202216.10"
+attribute \src "libresoc.v:202055.1-202112.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1"
attribute \generator "nMigen"
module \wrpick_FAST_fast1
- attribute \src "libresoc.v:202198.17-202198.91"
- wire $not$libresoc.v:202198$14418_Y
- attribute \src "libresoc.v:202200.18-202200.93"
- wire $not$libresoc.v:202200$14420_Y
- attribute \src "libresoc.v:202202.18-202202.93"
- wire $not$libresoc.v:202202$14422_Y
- attribute \src "libresoc.v:202203.17-202203.89"
- wire width 5 $not$libresoc.v:202203$14423_Y
- attribute \src "libresoc.v:202206.17-202206.91"
- wire $not$libresoc.v:202206$14426_Y
- attribute \src "libresoc.v:202199.18-202199.106"
- wire $reduce_or$libresoc.v:202199$14419_Y
- attribute \src "libresoc.v:202201.18-202201.106"
- wire $reduce_or$libresoc.v:202201$14421_Y
- attribute \src "libresoc.v:202204.18-202204.90"
- wire $reduce_or$libresoc.v:202204$14424_Y
- attribute \src "libresoc.v:202205.17-202205.103"
- wire $reduce_or$libresoc.v:202205$14425_Y
- attribute \src "libresoc.v:202207.17-202207.105"
- wire $reduce_or$libresoc.v:202207$14427_Y
+ attribute \src "libresoc.v:202094.17-202094.91"
+ wire $not$libresoc.v:202094$14210_Y
+ attribute \src "libresoc.v:202096.18-202096.93"
+ wire $not$libresoc.v:202096$14212_Y
+ attribute \src "libresoc.v:202098.18-202098.93"
+ wire $not$libresoc.v:202098$14214_Y
+ attribute \src "libresoc.v:202099.17-202099.89"
+ wire width 5 $not$libresoc.v:202099$14215_Y
+ attribute \src "libresoc.v:202102.17-202102.91"
+ wire $not$libresoc.v:202102$14218_Y
+ attribute \src "libresoc.v:202095.18-202095.106"
+ wire $reduce_or$libresoc.v:202095$14211_Y
+ attribute \src "libresoc.v:202097.18-202097.106"
+ wire $reduce_or$libresoc.v:202097$14213_Y
+ attribute \src "libresoc.v:202100.18-202100.90"
+ wire $reduce_or$libresoc.v:202100$14216_Y
+ attribute \src "libresoc.v:202101.17-202101.103"
+ wire $reduce_or$libresoc.v:202101$14217_Y
+ attribute \src "libresoc.v:202103.17-202103.105"
+ wire $reduce_or$libresoc.v:202103$14219_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 5 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202198$14418
+ cell $not $not$libresoc.v:202094$14210
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202198$14418_Y
+ connect \Y $not$libresoc.v:202094$14210_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202200$14420
+ cell $not $not$libresoc.v:202096$14212
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:202200$14420_Y
+ connect \Y $not$libresoc.v:202096$14212_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202202$14422
+ cell $not $not$libresoc.v:202098$14214
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:202202$14422_Y
+ connect \Y $not$libresoc.v:202098$14214_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202203$14423
+ cell $not $not$libresoc.v:202099$14215
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \i
- connect \Y $not$libresoc.v:202203$14423_Y
+ connect \Y $not$libresoc.v:202099$14215_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202206$14426
+ cell $not $not$libresoc.v:202102$14218
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202206$14426_Y
+ connect \Y $not$libresoc.v:202102$14218_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202199$14419
+ cell $reduce_or $reduce_or$libresoc.v:202095$14211
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:202199$14419_Y
+ connect \Y $reduce_or$libresoc.v:202095$14211_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202201$14421
+ cell $reduce_or $reduce_or$libresoc.v:202097$14213
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:202201$14421_Y
+ connect \Y $reduce_or$libresoc.v:202097$14213_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202204$14424
+ cell $reduce_or $reduce_or$libresoc.v:202100$14216
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202204$14424_Y
+ connect \Y $reduce_or$libresoc.v:202100$14216_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202205$14425
+ cell $reduce_or $reduce_or$libresoc.v:202101$14217
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202205$14425_Y
+ connect \Y $reduce_or$libresoc.v:202101$14217_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202207$14427
+ cell $reduce_or $reduce_or$libresoc.v:202103$14219
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202207$14427_Y
- end
- connect \$7 $not$libresoc.v:202198$14418_Y
- connect \$12 $reduce_or$libresoc.v:202199$14419_Y
- connect \$11 $not$libresoc.v:202200$14420_Y
- connect \$16 $reduce_or$libresoc.v:202201$14421_Y
- connect \$15 $not$libresoc.v:202202$14422_Y
- connect \$1 $not$libresoc.v:202203$14423_Y
- connect \$19 $reduce_or$libresoc.v:202204$14424_Y
- connect \$4 $reduce_or$libresoc.v:202205$14425_Y
- connect \$3 $not$libresoc.v:202206$14426_Y
- connect \$8 $reduce_or$libresoc.v:202207$14427_Y
+ connect \Y $reduce_or$libresoc.v:202103$14219_Y
+ end
+ connect \$7 $not$libresoc.v:202094$14210_Y
+ connect \$12 $reduce_or$libresoc.v:202095$14211_Y
+ connect \$11 $not$libresoc.v:202096$14212_Y
+ connect \$16 $reduce_or$libresoc.v:202097$14213_Y
+ connect \$15 $not$libresoc.v:202098$14214_Y
+ connect \$1 $not$libresoc.v:202099$14215_Y
+ connect \$19 $reduce_or$libresoc.v:202100$14216_Y
+ connect \$4 $reduce_or$libresoc.v:202101$14217_Y
+ connect \$3 $not$libresoc.v:202102$14218_Y
+ connect \$8 $reduce_or$libresoc.v:202103$14219_Y
connect \en_o \$19
connect \o { \t4 \t3 \t2 \t1 \t0 }
connect \t4 \$15
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202220.1-202322.10"
+attribute \src "libresoc.v:202116.1-202218.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o"
attribute \generator "nMigen"
module \wrpick_INT_o
- attribute \src "libresoc.v:202289.17-202289.91"
- wire $not$libresoc.v:202289$14428_Y
- attribute \src "libresoc.v:202291.18-202291.93"
- wire $not$libresoc.v:202291$14430_Y
- attribute \src "libresoc.v:202293.18-202293.93"
- wire $not$libresoc.v:202293$14432_Y
- attribute \src "libresoc.v:202294.17-202294.89"
- wire width 10 $not$libresoc.v:202294$14433_Y
- attribute \src "libresoc.v:202296.18-202296.93"
- wire $not$libresoc.v:202296$14435_Y
- attribute \src "libresoc.v:202298.18-202298.93"
- wire $not$libresoc.v:202298$14437_Y
- attribute \src "libresoc.v:202300.18-202300.93"
- wire $not$libresoc.v:202300$14439_Y
- attribute \src "libresoc.v:202302.18-202302.93"
- wire $not$libresoc.v:202302$14441_Y
- attribute \src "libresoc.v:202304.18-202304.93"
- wire $not$libresoc.v:202304$14443_Y
- attribute \src "libresoc.v:202307.17-202307.91"
- wire $not$libresoc.v:202307$14446_Y
- attribute \src "libresoc.v:202290.18-202290.106"
- wire $reduce_or$libresoc.v:202290$14429_Y
- attribute \src "libresoc.v:202292.18-202292.106"
- wire $reduce_or$libresoc.v:202292$14431_Y
- attribute \src "libresoc.v:202295.18-202295.106"
- wire $reduce_or$libresoc.v:202295$14434_Y
- attribute \src "libresoc.v:202297.18-202297.106"
- wire $reduce_or$libresoc.v:202297$14436_Y
- attribute \src "libresoc.v:202299.18-202299.106"
- wire $reduce_or$libresoc.v:202299$14438_Y
- attribute \src "libresoc.v:202301.18-202301.106"
- wire $reduce_or$libresoc.v:202301$14440_Y
- attribute \src "libresoc.v:202303.18-202303.106"
- wire $reduce_or$libresoc.v:202303$14442_Y
- attribute \src "libresoc.v:202305.18-202305.90"
- wire $reduce_or$libresoc.v:202305$14444_Y
- attribute \src "libresoc.v:202306.17-202306.103"
- wire $reduce_or$libresoc.v:202306$14445_Y
- attribute \src "libresoc.v:202308.17-202308.105"
- wire $reduce_or$libresoc.v:202308$14447_Y
+ attribute \src "libresoc.v:202185.17-202185.91"
+ wire $not$libresoc.v:202185$14220_Y
+ attribute \src "libresoc.v:202187.18-202187.93"
+ wire $not$libresoc.v:202187$14222_Y
+ attribute \src "libresoc.v:202189.18-202189.93"
+ wire $not$libresoc.v:202189$14224_Y
+ attribute \src "libresoc.v:202190.17-202190.89"
+ wire width 10 $not$libresoc.v:202190$14225_Y
+ attribute \src "libresoc.v:202192.18-202192.93"
+ wire $not$libresoc.v:202192$14227_Y
+ attribute \src "libresoc.v:202194.18-202194.93"
+ wire $not$libresoc.v:202194$14229_Y
+ attribute \src "libresoc.v:202196.18-202196.93"
+ wire $not$libresoc.v:202196$14231_Y
+ attribute \src "libresoc.v:202198.18-202198.93"
+ wire $not$libresoc.v:202198$14233_Y
+ attribute \src "libresoc.v:202200.18-202200.93"
+ wire $not$libresoc.v:202200$14235_Y
+ attribute \src "libresoc.v:202203.17-202203.91"
+ wire $not$libresoc.v:202203$14238_Y
+ attribute \src "libresoc.v:202186.18-202186.106"
+ wire $reduce_or$libresoc.v:202186$14221_Y
+ attribute \src "libresoc.v:202188.18-202188.106"
+ wire $reduce_or$libresoc.v:202188$14223_Y
+ attribute \src "libresoc.v:202191.18-202191.106"
+ wire $reduce_or$libresoc.v:202191$14226_Y
+ attribute \src "libresoc.v:202193.18-202193.106"
+ wire $reduce_or$libresoc.v:202193$14228_Y
+ attribute \src "libresoc.v:202195.18-202195.106"
+ wire $reduce_or$libresoc.v:202195$14230_Y
+ attribute \src "libresoc.v:202197.18-202197.106"
+ wire $reduce_or$libresoc.v:202197$14232_Y
+ attribute \src "libresoc.v:202199.18-202199.106"
+ wire $reduce_or$libresoc.v:202199$14234_Y
+ attribute \src "libresoc.v:202201.18-202201.90"
+ wire $reduce_or$libresoc.v:202201$14236_Y
+ attribute \src "libresoc.v:202202.17-202202.103"
+ wire $reduce_or$libresoc.v:202202$14237_Y
+ attribute \src "libresoc.v:202204.17-202204.105"
+ wire $reduce_or$libresoc.v:202204$14239_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 10 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202289$14428
+ cell $not $not$libresoc.v:202185$14220
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202289$14428_Y
+ connect \Y $not$libresoc.v:202185$14220_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202291$14430
+ cell $not $not$libresoc.v:202187$14222
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:202291$14430_Y
+ connect \Y $not$libresoc.v:202187$14222_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202293$14432
+ cell $not $not$libresoc.v:202189$14224
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:202293$14432_Y
+ connect \Y $not$libresoc.v:202189$14224_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202294$14433
+ cell $not $not$libresoc.v:202190$14225
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 10
connect \A \i
- connect \Y $not$libresoc.v:202294$14433_Y
+ connect \Y $not$libresoc.v:202190$14225_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202296$14435
+ cell $not $not$libresoc.v:202192$14227
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:202296$14435_Y
+ connect \Y $not$libresoc.v:202192$14227_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202298$14437
+ cell $not $not$libresoc.v:202194$14229
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:202298$14437_Y
+ connect \Y $not$libresoc.v:202194$14229_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202300$14439
+ cell $not $not$libresoc.v:202196$14231
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:202300$14439_Y
+ connect \Y $not$libresoc.v:202196$14231_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202302$14441
+ cell $not $not$libresoc.v:202198$14233
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$32
- connect \Y $not$libresoc.v:202302$14441_Y
+ connect \Y $not$libresoc.v:202198$14233_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202304$14443
+ cell $not $not$libresoc.v:202200$14235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$36
- connect \Y $not$libresoc.v:202304$14443_Y
+ connect \Y $not$libresoc.v:202200$14235_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202307$14446
+ cell $not $not$libresoc.v:202203$14238
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202307$14446_Y
+ connect \Y $not$libresoc.v:202203$14238_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202290$14429
+ cell $reduce_or $reduce_or$libresoc.v:202186$14221
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:202290$14429_Y
+ connect \Y $reduce_or$libresoc.v:202186$14221_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202292$14431
+ cell $reduce_or $reduce_or$libresoc.v:202188$14223
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [3:0] \ni [4] }
- connect \Y $reduce_or$libresoc.v:202292$14431_Y
+ connect \Y $reduce_or$libresoc.v:202188$14223_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202295$14434
+ cell $reduce_or $reduce_or$libresoc.v:202191$14226
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [4:0] \ni [5] }
- connect \Y $reduce_or$libresoc.v:202295$14434_Y
+ connect \Y $reduce_or$libresoc.v:202191$14226_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202297$14436
+ cell $reduce_or $reduce_or$libresoc.v:202193$14228
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [5:0] \ni [6] }
- connect \Y $reduce_or$libresoc.v:202297$14436_Y
+ connect \Y $reduce_or$libresoc.v:202193$14228_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202299$14438
+ cell $reduce_or $reduce_or$libresoc.v:202195$14230
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [6:0] \ni [7] }
- connect \Y $reduce_or$libresoc.v:202299$14438_Y
+ connect \Y $reduce_or$libresoc.v:202195$14230_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202301$14440
+ cell $reduce_or $reduce_or$libresoc.v:202197$14232
parameter \A_SIGNED 0
parameter \A_WIDTH 9
parameter \Y_WIDTH 1
connect \A { \i [7:0] \ni [8] }
- connect \Y $reduce_or$libresoc.v:202301$14440_Y
+ connect \Y $reduce_or$libresoc.v:202197$14232_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202303$14442
+ cell $reduce_or $reduce_or$libresoc.v:202199$14234
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A { \i [8:0] \ni [9] }
- connect \Y $reduce_or$libresoc.v:202303$14442_Y
+ connect \Y $reduce_or$libresoc.v:202199$14234_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202305$14444
+ cell $reduce_or $reduce_or$libresoc.v:202201$14236
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202305$14444_Y
+ connect \Y $reduce_or$libresoc.v:202201$14236_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202306$14445
+ cell $reduce_or $reduce_or$libresoc.v:202202$14237
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202306$14445_Y
+ connect \Y $reduce_or$libresoc.v:202202$14237_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202308$14447
+ cell $reduce_or $reduce_or$libresoc.v:202204$14239
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202308$14447_Y
- end
- connect \$7 $not$libresoc.v:202289$14428_Y
- connect \$12 $reduce_or$libresoc.v:202290$14429_Y
- connect \$11 $not$libresoc.v:202291$14430_Y
- connect \$16 $reduce_or$libresoc.v:202292$14431_Y
- connect \$15 $not$libresoc.v:202293$14432_Y
- connect \$1 $not$libresoc.v:202294$14433_Y
- connect \$20 $reduce_or$libresoc.v:202295$14434_Y
- connect \$19 $not$libresoc.v:202296$14435_Y
- connect \$24 $reduce_or$libresoc.v:202297$14436_Y
- connect \$23 $not$libresoc.v:202298$14437_Y
- connect \$28 $reduce_or$libresoc.v:202299$14438_Y
- connect \$27 $not$libresoc.v:202300$14439_Y
- connect \$32 $reduce_or$libresoc.v:202301$14440_Y
- connect \$31 $not$libresoc.v:202302$14441_Y
- connect \$36 $reduce_or$libresoc.v:202303$14442_Y
- connect \$35 $not$libresoc.v:202304$14443_Y
- connect \$39 $reduce_or$libresoc.v:202305$14444_Y
- connect \$4 $reduce_or$libresoc.v:202306$14445_Y
- connect \$3 $not$libresoc.v:202307$14446_Y
- connect \$8 $reduce_or$libresoc.v:202308$14447_Y
+ connect \Y $reduce_or$libresoc.v:202204$14239_Y
+ end
+ connect \$7 $not$libresoc.v:202185$14220_Y
+ connect \$12 $reduce_or$libresoc.v:202186$14221_Y
+ connect \$11 $not$libresoc.v:202187$14222_Y
+ connect \$16 $reduce_or$libresoc.v:202188$14223_Y
+ connect \$15 $not$libresoc.v:202189$14224_Y
+ connect \$1 $not$libresoc.v:202190$14225_Y
+ connect \$20 $reduce_or$libresoc.v:202191$14226_Y
+ connect \$19 $not$libresoc.v:202192$14227_Y
+ connect \$24 $reduce_or$libresoc.v:202193$14228_Y
+ connect \$23 $not$libresoc.v:202194$14229_Y
+ connect \$28 $reduce_or$libresoc.v:202195$14230_Y
+ connect \$27 $not$libresoc.v:202196$14231_Y
+ connect \$32 $reduce_or$libresoc.v:202197$14232_Y
+ connect \$31 $not$libresoc.v:202198$14233_Y
+ connect \$36 $reduce_or$libresoc.v:202199$14234_Y
+ connect \$35 $not$libresoc.v:202200$14235_Y
+ connect \$39 $reduce_or$libresoc.v:202201$14236_Y
+ connect \$4 $reduce_or$libresoc.v:202202$14237_Y
+ connect \$3 $not$libresoc.v:202203$14238_Y
+ connect \$8 $reduce_or$libresoc.v:202204$14239_Y
connect \en_o \$39
connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
connect \t9 \$35
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202326.1-202347.10"
+attribute \src "libresoc.v:202222.1-202243.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1"
attribute \generator "nMigen"
module \wrpick_SPR_spr1
- attribute \src "libresoc.v:202341.17-202341.89"
- wire $not$libresoc.v:202341$14448_Y
- attribute \src "libresoc.v:202342.17-202342.89"
- wire $reduce_or$libresoc.v:202342$14449_Y
+ attribute \src "libresoc.v:202237.17-202237.89"
+ wire $not$libresoc.v:202237$14240_Y
+ attribute \src "libresoc.v:202238.17-202238.89"
+ wire $reduce_or$libresoc.v:202238$14241_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202341$14448
+ cell $not $not$libresoc.v:202237$14240
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:202341$14448_Y
+ connect \Y $not$libresoc.v:202237$14240_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202342$14449
+ cell $reduce_or $reduce_or$libresoc.v:202238$14241
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202342$14449_Y
+ connect \Y $reduce_or$libresoc.v:202238$14241_Y
end
- connect \$1 $not$libresoc.v:202341$14448_Y
- connect \$3 $reduce_or$libresoc.v:202342$14449_Y
+ connect \$1 $not$libresoc.v:202237$14240_Y
+ connect \$3 $reduce_or$libresoc.v:202238$14241_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:202351.1-202372.10"
+attribute \src "libresoc.v:202247.1-202268.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr"
attribute \generator "nMigen"
module \wrpick_STATE_msr
- attribute \src "libresoc.v:202366.17-202366.89"
- wire $not$libresoc.v:202366$14450_Y
- attribute \src "libresoc.v:202367.17-202367.89"
- wire $reduce_or$libresoc.v:202367$14451_Y
+ attribute \src "libresoc.v:202262.17-202262.89"
+ wire $not$libresoc.v:202262$14242_Y
+ attribute \src "libresoc.v:202263.17-202263.89"
+ wire $reduce_or$libresoc.v:202263$14243_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202366$14450
+ cell $not $not$libresoc.v:202262$14242
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i
- connect \Y $not$libresoc.v:202366$14450_Y
+ connect \Y $not$libresoc.v:202262$14242_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202367$14451
+ cell $reduce_or $reduce_or$libresoc.v:202263$14243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202367$14451_Y
+ connect \Y $reduce_or$libresoc.v:202263$14243_Y
end
- connect \$1 $not$libresoc.v:202366$14450_Y
- connect \$3 $reduce_or$libresoc.v:202367$14451_Y
+ connect \$1 $not$libresoc.v:202262$14242_Y
+ connect \$3 $reduce_or$libresoc.v:202263$14243_Y
connect \en_o \$3
connect \o \t0
connect \t0 \i
connect \ni \$1
end
-attribute \src "libresoc.v:202376.1-202406.10"
+attribute \src "libresoc.v:202272.1-202302.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia"
attribute \generator "nMigen"
module \wrpick_STATE_nia
- attribute \src "libresoc.v:202397.17-202397.89"
- wire width 2 $not$libresoc.v:202397$14452_Y
- attribute \src "libresoc.v:202399.17-202399.91"
- wire $not$libresoc.v:202399$14454_Y
- attribute \src "libresoc.v:202398.17-202398.103"
- wire $reduce_or$libresoc.v:202398$14453_Y
- attribute \src "libresoc.v:202400.17-202400.89"
- wire $reduce_or$libresoc.v:202400$14455_Y
+ attribute \src "libresoc.v:202293.17-202293.89"
+ wire width 2 $not$libresoc.v:202293$14244_Y
+ attribute \src "libresoc.v:202295.17-202295.91"
+ wire $not$libresoc.v:202295$14246_Y
+ attribute \src "libresoc.v:202294.17-202294.103"
+ wire $reduce_or$libresoc.v:202294$14245_Y
+ attribute \src "libresoc.v:202296.17-202296.89"
+ wire $reduce_or$libresoc.v:202296$14247_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 2 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202397$14452
+ cell $not $not$libresoc.v:202293$14244
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \i
- connect \Y $not$libresoc.v:202397$14452_Y
+ connect \Y $not$libresoc.v:202293$14244_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202399$14454
+ cell $not $not$libresoc.v:202295$14246
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202399$14454_Y
+ connect \Y $not$libresoc.v:202295$14246_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202398$14453
+ cell $reduce_or $reduce_or$libresoc.v:202294$14245
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202398$14453_Y
+ connect \Y $reduce_or$libresoc.v:202294$14245_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202400$14455
+ cell $reduce_or $reduce_or$libresoc.v:202296$14247
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202400$14455_Y
+ connect \Y $reduce_or$libresoc.v:202296$14247_Y
end
- connect \$1 $not$libresoc.v:202397$14452_Y
- connect \$4 $reduce_or$libresoc.v:202398$14453_Y
- connect \$3 $not$libresoc.v:202399$14454_Y
- connect \$7 $reduce_or$libresoc.v:202400$14455_Y
+ connect \$1 $not$libresoc.v:202293$14244_Y
+ connect \$4 $reduce_or$libresoc.v:202294$14245_Y
+ connect \$3 $not$libresoc.v:202295$14246_Y
+ connect \$7 $reduce_or$libresoc.v:202296$14247_Y
connect \en_o \$7
connect \o { \t1 \t0 }
connect \t1 \$3
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202410.1-202449.10"
+attribute \src "libresoc.v:202306.1-202345.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca"
attribute \generator "nMigen"
module \wrpick_XER_xer_ca
- attribute \src "libresoc.v:202437.17-202437.91"
- wire $not$libresoc.v:202437$14456_Y
- attribute \src "libresoc.v:202439.17-202439.89"
- wire width 3 $not$libresoc.v:202439$14458_Y
- attribute \src "libresoc.v:202441.17-202441.91"
- wire $not$libresoc.v:202441$14460_Y
- attribute \src "libresoc.v:202438.18-202438.90"
- wire $reduce_or$libresoc.v:202438$14457_Y
- attribute \src "libresoc.v:202440.17-202440.103"
- wire $reduce_or$libresoc.v:202440$14459_Y
- attribute \src "libresoc.v:202442.17-202442.105"
- wire $reduce_or$libresoc.v:202442$14461_Y
+ attribute \src "libresoc.v:202333.17-202333.91"
+ wire $not$libresoc.v:202333$14248_Y
+ attribute \src "libresoc.v:202335.17-202335.89"
+ wire width 3 $not$libresoc.v:202335$14250_Y
+ attribute \src "libresoc.v:202337.17-202337.91"
+ wire $not$libresoc.v:202337$14252_Y
+ attribute \src "libresoc.v:202334.18-202334.90"
+ wire $reduce_or$libresoc.v:202334$14249_Y
+ attribute \src "libresoc.v:202336.17-202336.103"
+ wire $reduce_or$libresoc.v:202336$14251_Y
+ attribute \src "libresoc.v:202338.17-202338.105"
+ wire $reduce_or$libresoc.v:202338$14253_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 3 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202437$14456
+ cell $not $not$libresoc.v:202333$14248
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202437$14456_Y
+ connect \Y $not$libresoc.v:202333$14248_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202439$14458
+ cell $not $not$libresoc.v:202335$14250
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \i
- connect \Y $not$libresoc.v:202439$14458_Y
+ connect \Y $not$libresoc.v:202335$14250_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202441$14460
+ cell $not $not$libresoc.v:202337$14252
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202441$14460_Y
+ connect \Y $not$libresoc.v:202337$14252_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202438$14457
+ cell $reduce_or $reduce_or$libresoc.v:202334$14249
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202438$14457_Y
+ connect \Y $reduce_or$libresoc.v:202334$14249_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202440$14459
+ cell $reduce_or $reduce_or$libresoc.v:202336$14251
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202440$14459_Y
+ connect \Y $reduce_or$libresoc.v:202336$14251_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202442$14461
+ cell $reduce_or $reduce_or$libresoc.v:202338$14253
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202442$14461_Y
- end
- connect \$7 $not$libresoc.v:202437$14456_Y
- connect \$11 $reduce_or$libresoc.v:202438$14457_Y
- connect \$1 $not$libresoc.v:202439$14458_Y
- connect \$4 $reduce_or$libresoc.v:202440$14459_Y
- connect \$3 $not$libresoc.v:202441$14460_Y
- connect \$8 $reduce_or$libresoc.v:202442$14461_Y
+ connect \Y $reduce_or$libresoc.v:202338$14253_Y
+ end
+ connect \$7 $not$libresoc.v:202333$14248_Y
+ connect \$11 $reduce_or$libresoc.v:202334$14249_Y
+ connect \$1 $not$libresoc.v:202335$14250_Y
+ connect \$4 $reduce_or$libresoc.v:202336$14251_Y
+ connect \$3 $not$libresoc.v:202337$14252_Y
+ connect \$8 $reduce_or$libresoc.v:202338$14253_Y
connect \en_o \$11
connect \o { \t2 \t1 \t0 }
connect \t2 \$7
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202453.1-202501.10"
+attribute \src "libresoc.v:202349.1-202397.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov"
attribute \generator "nMigen"
module \wrpick_XER_xer_ov
- attribute \src "libresoc.v:202486.17-202486.91"
- wire $not$libresoc.v:202486$14462_Y
- attribute \src "libresoc.v:202488.18-202488.93"
- wire $not$libresoc.v:202488$14464_Y
- attribute \src "libresoc.v:202490.17-202490.89"
- wire width 4 $not$libresoc.v:202490$14466_Y
- attribute \src "libresoc.v:202492.17-202492.91"
- wire $not$libresoc.v:202492$14468_Y
- attribute \src "libresoc.v:202487.18-202487.106"
- wire $reduce_or$libresoc.v:202487$14463_Y
- attribute \src "libresoc.v:202489.18-202489.90"
- wire $reduce_or$libresoc.v:202489$14465_Y
- attribute \src "libresoc.v:202491.17-202491.103"
- wire $reduce_or$libresoc.v:202491$14467_Y
- attribute \src "libresoc.v:202493.17-202493.105"
- wire $reduce_or$libresoc.v:202493$14469_Y
+ attribute \src "libresoc.v:202382.17-202382.91"
+ wire $not$libresoc.v:202382$14254_Y
+ attribute \src "libresoc.v:202384.18-202384.93"
+ wire $not$libresoc.v:202384$14256_Y
+ attribute \src "libresoc.v:202386.17-202386.89"
+ wire width 4 $not$libresoc.v:202386$14258_Y
+ attribute \src "libresoc.v:202388.17-202388.91"
+ wire $not$libresoc.v:202388$14260_Y
+ attribute \src "libresoc.v:202383.18-202383.106"
+ wire $reduce_or$libresoc.v:202383$14255_Y
+ attribute \src "libresoc.v:202385.18-202385.90"
+ wire $reduce_or$libresoc.v:202385$14257_Y
+ attribute \src "libresoc.v:202387.17-202387.103"
+ wire $reduce_or$libresoc.v:202387$14259_Y
+ attribute \src "libresoc.v:202389.17-202389.105"
+ wire $reduce_or$libresoc.v:202389$14261_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202486$14462
+ cell $not $not$libresoc.v:202382$14254
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202486$14462_Y
+ connect \Y $not$libresoc.v:202382$14254_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202488$14464
+ cell $not $not$libresoc.v:202384$14256
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:202488$14464_Y
+ connect \Y $not$libresoc.v:202384$14256_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202490$14466
+ cell $not $not$libresoc.v:202386$14258
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:202490$14466_Y
+ connect \Y $not$libresoc.v:202386$14258_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202492$14468
+ cell $not $not$libresoc.v:202388$14260
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202492$14468_Y
+ connect \Y $not$libresoc.v:202388$14260_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202487$14463
+ cell $reduce_or $reduce_or$libresoc.v:202383$14255
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:202487$14463_Y
+ connect \Y $reduce_or$libresoc.v:202383$14255_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202489$14465
+ cell $reduce_or $reduce_or$libresoc.v:202385$14257
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202489$14465_Y
+ connect \Y $reduce_or$libresoc.v:202385$14257_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202491$14467
+ cell $reduce_or $reduce_or$libresoc.v:202387$14259
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202491$14467_Y
+ connect \Y $reduce_or$libresoc.v:202387$14259_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202493$14469
+ cell $reduce_or $reduce_or$libresoc.v:202389$14261
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202493$14469_Y
- end
- connect \$7 $not$libresoc.v:202486$14462_Y
- connect \$12 $reduce_or$libresoc.v:202487$14463_Y
- connect \$11 $not$libresoc.v:202488$14464_Y
- connect \$15 $reduce_or$libresoc.v:202489$14465_Y
- connect \$1 $not$libresoc.v:202490$14466_Y
- connect \$4 $reduce_or$libresoc.v:202491$14467_Y
- connect \$3 $not$libresoc.v:202492$14468_Y
- connect \$8 $reduce_or$libresoc.v:202493$14469_Y
+ connect \Y $reduce_or$libresoc.v:202389$14261_Y
+ end
+ connect \$7 $not$libresoc.v:202382$14254_Y
+ connect \$12 $reduce_or$libresoc.v:202383$14255_Y
+ connect \$11 $not$libresoc.v:202384$14256_Y
+ connect \$15 $reduce_or$libresoc.v:202385$14257_Y
+ connect \$1 $not$libresoc.v:202386$14258_Y
+ connect \$4 $reduce_or$libresoc.v:202387$14259_Y
+ connect \$3 $not$libresoc.v:202388$14260_Y
+ connect \$8 $reduce_or$libresoc.v:202389$14261_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202505.1-202553.10"
+attribute \src "libresoc.v:202401.1-202449.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so"
attribute \generator "nMigen"
module \wrpick_XER_xer_so
- attribute \src "libresoc.v:202538.17-202538.91"
- wire $not$libresoc.v:202538$14470_Y
- attribute \src "libresoc.v:202540.18-202540.93"
- wire $not$libresoc.v:202540$14472_Y
- attribute \src "libresoc.v:202542.17-202542.89"
- wire width 4 $not$libresoc.v:202542$14474_Y
- attribute \src "libresoc.v:202544.17-202544.91"
- wire $not$libresoc.v:202544$14476_Y
- attribute \src "libresoc.v:202539.18-202539.106"
- wire $reduce_or$libresoc.v:202539$14471_Y
- attribute \src "libresoc.v:202541.18-202541.90"
- wire $reduce_or$libresoc.v:202541$14473_Y
- attribute \src "libresoc.v:202543.17-202543.103"
- wire $reduce_or$libresoc.v:202543$14475_Y
- attribute \src "libresoc.v:202545.17-202545.105"
- wire $reduce_or$libresoc.v:202545$14477_Y
+ attribute \src "libresoc.v:202434.17-202434.91"
+ wire $not$libresoc.v:202434$14262_Y
+ attribute \src "libresoc.v:202436.18-202436.93"
+ wire $not$libresoc.v:202436$14264_Y
+ attribute \src "libresoc.v:202438.17-202438.89"
+ wire width 4 $not$libresoc.v:202438$14266_Y
+ attribute \src "libresoc.v:202440.17-202440.91"
+ wire $not$libresoc.v:202440$14268_Y
+ attribute \src "libresoc.v:202435.18-202435.106"
+ wire $reduce_or$libresoc.v:202435$14263_Y
+ attribute \src "libresoc.v:202437.18-202437.90"
+ wire $reduce_or$libresoc.v:202437$14265_Y
+ attribute \src "libresoc.v:202439.17-202439.103"
+ wire $reduce_or$libresoc.v:202439$14267_Y
+ attribute \src "libresoc.v:202441.17-202441.105"
+ wire $reduce_or$libresoc.v:202441$14269_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire width 4 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
wire \t3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202538$14470
+ cell $not $not$libresoc.v:202434$14262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:202538$14470_Y
+ connect \Y $not$libresoc.v:202434$14262_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202540$14472
+ cell $not $not$libresoc.v:202436$14264
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:202540$14472_Y
+ connect \Y $not$libresoc.v:202436$14264_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
- cell $not $not$libresoc.v:202542$14474
+ cell $not $not$libresoc.v:202438$14266
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \i
- connect \Y $not$libresoc.v:202542$14474_Y
+ connect \Y $not$libresoc.v:202438$14266_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $not $not$libresoc.v:202544$14476
+ cell $not $not$libresoc.v:202440$14268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:202544$14476_Y
+ connect \Y $not$libresoc.v:202440$14268_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202539$14471
+ cell $reduce_or $reduce_or$libresoc.v:202435$14263
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [2:0] \ni [3] }
- connect \Y $reduce_or$libresoc.v:202539$14471_Y
+ connect \Y $reduce_or$libresoc.v:202435$14263_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74"
- cell $reduce_or $reduce_or$libresoc.v:202541$14473
+ cell $reduce_or $reduce_or$libresoc.v:202437$14265
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:202541$14473_Y
+ connect \Y $reduce_or$libresoc.v:202437$14265_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202543$14475
+ cell $reduce_or $reduce_or$libresoc.v:202439$14267
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [0] \ni [1] }
- connect \Y $reduce_or$libresoc.v:202543$14475_Y
+ connect \Y $reduce_or$libresoc.v:202439$14267_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68"
- cell $reduce_or $reduce_or$libresoc.v:202545$14477
+ cell $reduce_or $reduce_or$libresoc.v:202441$14269
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [1:0] \ni [2] }
- connect \Y $reduce_or$libresoc.v:202545$14477_Y
- end
- connect \$7 $not$libresoc.v:202538$14470_Y
- connect \$12 $reduce_or$libresoc.v:202539$14471_Y
- connect \$11 $not$libresoc.v:202540$14472_Y
- connect \$15 $reduce_or$libresoc.v:202541$14473_Y
- connect \$1 $not$libresoc.v:202542$14474_Y
- connect \$4 $reduce_or$libresoc.v:202543$14475_Y
- connect \$3 $not$libresoc.v:202544$14476_Y
- connect \$8 $reduce_or$libresoc.v:202545$14477_Y
+ connect \Y $reduce_or$libresoc.v:202441$14269_Y
+ end
+ connect \$7 $not$libresoc.v:202434$14262_Y
+ connect \$12 $reduce_or$libresoc.v:202435$14263_Y
+ connect \$11 $not$libresoc.v:202436$14264_Y
+ connect \$15 $reduce_or$libresoc.v:202437$14265_Y
+ connect \$1 $not$libresoc.v:202438$14266_Y
+ connect \$4 $reduce_or$libresoc.v:202439$14267_Y
+ connect \$3 $not$libresoc.v:202440$14268_Y
+ connect \$8 $reduce_or$libresoc.v:202441$14269_Y
connect \en_o \$15
connect \o { \t3 \t2 \t1 \t0 }
connect \t3 \$11
connect \t0 \i [0]
connect \ni \$1
end
-attribute \src "libresoc.v:202557.1-202877.10"
+attribute \src "libresoc.v:202453.1-202773.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.core.xer"
attribute \generator "nMigen"
module \xer
- attribute \src "libresoc.v:202558.7-202558.20"
+ attribute \src "libresoc.v:202454.7-202454.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:202837.3-202845.6"
- wire width 3 $0\ren_delay$11$next[2:0]$14501
- attribute \src "libresoc.v:202735.3-202736.43"
- wire width 3 $0\ren_delay$11[2:0]$14490
- attribute \src "libresoc.v:202694.13-202694.34"
- wire width 3 $0\ren_delay$11[2:0]$14507
- attribute \src "libresoc.v:202799.3-202807.6"
- wire width 3 $0\ren_delay$18$next[2:0]$14493
- attribute \src "libresoc.v:202733.3-202734.43"
- wire width 3 $0\ren_delay$18[2:0]$14488
- attribute \src "libresoc.v:202698.13-202698.34"
- wire width 3 $0\ren_delay$18[2:0]$14509
- attribute \src "libresoc.v:202818.3-202826.6"
- wire width 3 $0\ren_delay$next[2:0]$14497
- attribute \src "libresoc.v:202737.3-202738.35"
+ attribute \src "libresoc.v:202733.3-202741.6"
+ wire width 3 $0\ren_delay$11$next[2:0]$14293
+ attribute \src "libresoc.v:202631.3-202632.43"
+ wire width 3 $0\ren_delay$11[2:0]$14282
+ attribute \src "libresoc.v:202590.13-202590.34"
+ wire width 3 $0\ren_delay$11[2:0]$14299
+ attribute \src "libresoc.v:202695.3-202703.6"
+ wire width 3 $0\ren_delay$18$next[2:0]$14285
+ attribute \src "libresoc.v:202629.3-202630.43"
+ wire width 3 $0\ren_delay$18[2:0]$14280
+ attribute \src "libresoc.v:202594.13-202594.34"
+ wire width 3 $0\ren_delay$18[2:0]$14301
+ attribute \src "libresoc.v:202714.3-202722.6"
+ wire width 3 $0\ren_delay$next[2:0]$14289
+ attribute \src "libresoc.v:202633.3-202634.35"
wire width 3 $0\ren_delay[2:0]
- attribute \src "libresoc.v:202827.3-202836.6"
+ attribute \src "libresoc.v:202723.3-202732.6"
wire width 2 $0\src1__data_o[1:0]
- attribute \src "libresoc.v:202846.3-202855.6"
+ attribute \src "libresoc.v:202742.3-202751.6"
wire width 2 $0\src2__data_o[1:0]
- attribute \src "libresoc.v:202808.3-202817.6"
+ attribute \src "libresoc.v:202704.3-202713.6"
wire width 2 $0\src3__data_o[1:0]
- attribute \src "libresoc.v:202837.3-202845.6"
- wire width 3 $1\ren_delay$11$next[2:0]$14502
- attribute \src "libresoc.v:202799.3-202807.6"
- wire width 3 $1\ren_delay$18$next[2:0]$14494
- attribute \src "libresoc.v:202818.3-202826.6"
- wire width 3 $1\ren_delay$next[2:0]$14498
- attribute \src "libresoc.v:202692.13-202692.29"
+ attribute \src "libresoc.v:202733.3-202741.6"
+ wire width 3 $1\ren_delay$11$next[2:0]$14294
+ attribute \src "libresoc.v:202695.3-202703.6"
+ wire width 3 $1\ren_delay$18$next[2:0]$14286
+ attribute \src "libresoc.v:202714.3-202722.6"
+ wire width 3 $1\ren_delay$next[2:0]$14290
+ attribute \src "libresoc.v:202588.13-202588.29"
wire width 3 $1\ren_delay[2:0]
- attribute \src "libresoc.v:202827.3-202836.6"
+ attribute \src "libresoc.v:202723.3-202732.6"
wire width 2 $1\src1__data_o[1:0]
- attribute \src "libresoc.v:202846.3-202855.6"
+ attribute \src "libresoc.v:202742.3-202751.6"
wire width 2 $1\src2__data_o[1:0]
- attribute \src "libresoc.v:202808.3-202817.6"
+ attribute \src "libresoc.v:202704.3-202713.6"
wire width 2 $1\src3__data_o[1:0]
- attribute \src "libresoc.v:202724.17-202724.109"
- wire width 2 $or$libresoc.v:202724$14478_Y
- attribute \src "libresoc.v:202726.18-202726.126"
- wire width 2 $or$libresoc.v:202726$14480_Y
- attribute \src "libresoc.v:202727.18-202727.111"
- wire width 2 $or$libresoc.v:202727$14481_Y
- attribute \src "libresoc.v:202729.18-202729.126"
- wire width 2 $or$libresoc.v:202729$14483_Y
- attribute \src "libresoc.v:202730.18-202730.111"
- wire width 2 $or$libresoc.v:202730$14484_Y
- attribute \src "libresoc.v:202732.17-202732.125"
- wire width 2 $or$libresoc.v:202732$14486_Y
- attribute \src "libresoc.v:202725.18-202725.100"
- wire $reduce_or$libresoc.v:202725$14479_Y
- attribute \src "libresoc.v:202728.18-202728.100"
- wire $reduce_or$libresoc.v:202728$14482_Y
- attribute \src "libresoc.v:202731.17-202731.95"
- wire $reduce_or$libresoc.v:202731$14485_Y
+ attribute \src "libresoc.v:202620.17-202620.109"
+ wire width 2 $or$libresoc.v:202620$14270_Y
+ attribute \src "libresoc.v:202622.18-202622.126"
+ wire width 2 $or$libresoc.v:202622$14272_Y
+ attribute \src "libresoc.v:202623.18-202623.111"
+ wire width 2 $or$libresoc.v:202623$14273_Y
+ attribute \src "libresoc.v:202625.18-202625.126"
+ wire width 2 $or$libresoc.v:202625$14275_Y
+ attribute \src "libresoc.v:202626.18-202626.111"
+ wire width 2 $or$libresoc.v:202626$14276_Y
+ attribute \src "libresoc.v:202628.17-202628.125"
+ wire width 2 $or$libresoc.v:202628$14278_Y
+ attribute \src "libresoc.v:202621.18-202621.100"
+ wire $reduce_or$libresoc.v:202621$14271_Y
+ attribute \src "libresoc.v:202624.18-202624.100"
+ wire $reduce_or$libresoc.v:202624$14274_Y
+ attribute \src "libresoc.v:202627.17-202627.95"
+ wire $reduce_or$libresoc.v:202627$14277_Y
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire \$12
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
wire width 2 \$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
wire width 2 \$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 16 \coresync_clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:795"
wire input 1 \coresync_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 input 10 \data_i
wire width 6 \full_wr__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 \full_wr__wen
- attribute \src "libresoc.v:202558.7-202558.15"
+ attribute \src "libresoc.v:202454.7-202454.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 2 \reg_0_dest10__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97"
wire width 3 input 15 \wen$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:202724$14478
+ cell $or $or$libresoc.v:202620$14270
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src10__data_o
connect \B \$7
- connect \Y $or$libresoc.v:202724$14478_Y
+ connect \Y $or$libresoc.v:202620$14270_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:202726$14480
+ cell $or $or$libresoc.v:202622$14272
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src21__data_o
connect \B \reg_2_src22__data_o
- connect \Y $or$libresoc.v:202726$14480_Y
+ connect \Y $or$libresoc.v:202622$14272_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:202727$14481
+ cell $or $or$libresoc.v:202623$14273
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src20__data_o
connect \B \$14
- connect \Y $or$libresoc.v:202727$14481_Y
+ connect \Y $or$libresoc.v:202623$14273_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:202729$14483
+ cell $or $or$libresoc.v:202625$14275
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src31__data_o
connect \B \reg_2_src32__data_o
- connect \Y $or$libresoc.v:202729$14483_Y
+ connect \Y $or$libresoc.v:202625$14275_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36"
- cell $or $or$libresoc.v:202730$14484
+ cell $or $or$libresoc.v:202626$14276
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_0_src30__data_o
connect \B \$21
- connect \Y $or$libresoc.v:202730$14484_Y
+ connect \Y $or$libresoc.v:202626$14276_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33"
- cell $or $or$libresoc.v:202732$14486
+ cell $or $or$libresoc.v:202628$14278
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \reg_1_src11__data_o
connect \B \reg_2_src12__data_o
- connect \Y $or$libresoc.v:202732$14486_Y
+ connect \Y $or$libresoc.v:202628$14278_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:202725$14479
+ cell $reduce_or $reduce_or$libresoc.v:202621$14271
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$11
- connect \Y $reduce_or$libresoc.v:202725$14479_Y
+ connect \Y $reduce_or$libresoc.v:202621$14271_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:202728$14482
+ cell $reduce_or $reduce_or$libresoc.v:202624$14274
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay$18
- connect \Y $reduce_or$libresoc.v:202728$14482_Y
+ connect \Y $reduce_or$libresoc.v:202624$14274_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:202731$14485
+ cell $reduce_or $reduce_or$libresoc.v:202627$14277
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \ren_delay
- connect \Y $reduce_or$libresoc.v:202731$14485_Y
+ connect \Y $reduce_or$libresoc.v:202627$14277_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202739.15-202758.4"
+ attribute \src "libresoc.v:202635.15-202654.4"
cell \reg_0$132 \reg_0
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w0__wen \reg_0_w0__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202759.15-202778.4"
+ attribute \src "libresoc.v:202655.15-202674.4"
cell \reg_1$133 \reg_1
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w1__wen \reg_1_w1__wen
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:202779.15-202798.4"
+ attribute \src "libresoc.v:202675.15-202694.4"
cell \reg_2$134 \reg_2
connect \coresync_clk \coresync_clk
connect \coresync_rst \coresync_rst
connect \w2__data_i \reg_2_w2__data_i
connect \w2__wen \reg_2_w2__wen
end
- attribute \src "libresoc.v:202558.7-202558.20"
- process $proc$libresoc.v:202558$14504
+ attribute \src "libresoc.v:202454.7-202454.20"
+ process $proc$libresoc.v:202454$14296
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:202692.13-202692.29"
- process $proc$libresoc.v:202692$14505
+ attribute \src "libresoc.v:202588.13-202588.29"
+ process $proc$libresoc.v:202588$14297
assign { } { }
assign $1\ren_delay[2:0] 3'000
sync always
sync init
update \ren_delay $1\ren_delay[2:0]
end
- attribute \src "libresoc.v:202694.13-202694.34"
- process $proc$libresoc.v:202694$14506
+ attribute \src "libresoc.v:202590.13-202590.34"
+ process $proc$libresoc.v:202590$14298
assign { } { }
- assign $0\ren_delay$11[2:0]$14507 3'000
+ assign $0\ren_delay$11[2:0]$14299 3'000
sync always
sync init
- update \ren_delay$11 $0\ren_delay$11[2:0]$14507
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14299
end
- attribute \src "libresoc.v:202698.13-202698.34"
- process $proc$libresoc.v:202698$14508
+ attribute \src "libresoc.v:202594.13-202594.34"
+ process $proc$libresoc.v:202594$14300
assign { } { }
- assign $0\ren_delay$18[2:0]$14509 3'000
+ assign $0\ren_delay$18[2:0]$14301 3'000
sync always
sync init
- update \ren_delay$18 $0\ren_delay$18[2:0]$14509
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14301
end
- attribute \src "libresoc.v:202733.3-202734.43"
- process $proc$libresoc.v:202733$14487
+ attribute \src "libresoc.v:202629.3-202630.43"
+ process $proc$libresoc.v:202629$14279
assign { } { }
- assign $0\ren_delay$18[2:0]$14488 \ren_delay$18$next
+ assign $0\ren_delay$18[2:0]$14280 \ren_delay$18$next
sync posedge \coresync_clk
- update \ren_delay$18 $0\ren_delay$18[2:0]$14488
+ update \ren_delay$18 $0\ren_delay$18[2:0]$14280
end
- attribute \src "libresoc.v:202735.3-202736.43"
- process $proc$libresoc.v:202735$14489
+ attribute \src "libresoc.v:202631.3-202632.43"
+ process $proc$libresoc.v:202631$14281
assign { } { }
- assign $0\ren_delay$11[2:0]$14490 \ren_delay$11$next
+ assign $0\ren_delay$11[2:0]$14282 \ren_delay$11$next
sync posedge \coresync_clk
- update \ren_delay$11 $0\ren_delay$11[2:0]$14490
+ update \ren_delay$11 $0\ren_delay$11[2:0]$14282
end
- attribute \src "libresoc.v:202737.3-202738.35"
- process $proc$libresoc.v:202737$14491
+ attribute \src "libresoc.v:202633.3-202634.35"
+ process $proc$libresoc.v:202633$14283
assign { } { }
assign $0\ren_delay[2:0] \ren_delay$next
sync posedge \coresync_clk
update \ren_delay $0\ren_delay[2:0]
end
- attribute \src "libresoc.v:202799.3-202807.6"
- process $proc$libresoc.v:202799$14492
+ attribute \src "libresoc.v:202695.3-202703.6"
+ process $proc$libresoc.v:202695$14284
assign { } { }
assign { } { }
- assign $0\ren_delay$18$next[2:0]$14493 $1\ren_delay$18$next[2:0]$14494
- attribute \src "libresoc.v:202800.5-202800.29"
+ assign $0\ren_delay$18$next[2:0]$14285 $1\ren_delay$18$next[2:0]$14286
+ attribute \src "libresoc.v:202696.5-202696.29"
switch \initial
- attribute \src "libresoc.v:202800.9-202800.17"
+ attribute \src "libresoc.v:202696.9-202696.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$18$next[2:0]$14494 3'000
+ assign $1\ren_delay$18$next[2:0]$14286 3'000
case
- assign $1\ren_delay$18$next[2:0]$14494 \src3__ren
+ assign $1\ren_delay$18$next[2:0]$14286 \src3__ren
end
sync always
- update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14493
+ update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14285
end
- attribute \src "libresoc.v:202808.3-202817.6"
- process $proc$libresoc.v:202808$14495
+ attribute \src "libresoc.v:202704.3-202713.6"
+ process $proc$libresoc.v:202704$14287
assign { } { }
assign { } { }
assign $0\src3__data_o[1:0] $1\src3__data_o[1:0]
- attribute \src "libresoc.v:202809.5-202809.29"
+ attribute \src "libresoc.v:202705.5-202705.29"
switch \initial
- attribute \src "libresoc.v:202809.9-202809.17"
+ attribute \src "libresoc.v:202705.9-202705.17"
case 1'1
case
end
sync always
update \src3__data_o $0\src3__data_o[1:0]
end
- attribute \src "libresoc.v:202818.3-202826.6"
- process $proc$libresoc.v:202818$14496
+ attribute \src "libresoc.v:202714.3-202722.6"
+ process $proc$libresoc.v:202714$14288
assign { } { }
assign { } { }
- assign $0\ren_delay$next[2:0]$14497 $1\ren_delay$next[2:0]$14498
- attribute \src "libresoc.v:202819.5-202819.29"
+ assign $0\ren_delay$next[2:0]$14289 $1\ren_delay$next[2:0]$14290
+ attribute \src "libresoc.v:202715.5-202715.29"
switch \initial
- attribute \src "libresoc.v:202819.9-202819.17"
+ attribute \src "libresoc.v:202715.9-202715.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$next[2:0]$14498 3'000
+ assign $1\ren_delay$next[2:0]$14290 3'000
case
- assign $1\ren_delay$next[2:0]$14498 \src1__ren
+ assign $1\ren_delay$next[2:0]$14290 \src1__ren
end
sync always
- update \ren_delay$next $0\ren_delay$next[2:0]$14497
+ update \ren_delay$next $0\ren_delay$next[2:0]$14289
end
- attribute \src "libresoc.v:202827.3-202836.6"
- process $proc$libresoc.v:202827$14499
+ attribute \src "libresoc.v:202723.3-202732.6"
+ process $proc$libresoc.v:202723$14291
assign { } { }
assign { } { }
assign $0\src1__data_o[1:0] $1\src1__data_o[1:0]
- attribute \src "libresoc.v:202828.5-202828.29"
+ attribute \src "libresoc.v:202724.5-202724.29"
switch \initial
- attribute \src "libresoc.v:202828.9-202828.17"
+ attribute \src "libresoc.v:202724.9-202724.17"
case 1'1
case
end
sync always
update \src1__data_o $0\src1__data_o[1:0]
end
- attribute \src "libresoc.v:202837.3-202845.6"
- process $proc$libresoc.v:202837$14500
+ attribute \src "libresoc.v:202733.3-202741.6"
+ process $proc$libresoc.v:202733$14292
assign { } { }
assign { } { }
- assign $0\ren_delay$11$next[2:0]$14501 $1\ren_delay$11$next[2:0]$14502
- attribute \src "libresoc.v:202838.5-202838.29"
+ assign $0\ren_delay$11$next[2:0]$14293 $1\ren_delay$11$next[2:0]$14294
+ attribute \src "libresoc.v:202734.5-202734.29"
switch \initial
- attribute \src "libresoc.v:202838.9-202838.17"
+ attribute \src "libresoc.v:202734.9-202734.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ren_delay$11$next[2:0]$14502 3'000
+ assign $1\ren_delay$11$next[2:0]$14294 3'000
case
- assign $1\ren_delay$11$next[2:0]$14502 \src2__ren
+ assign $1\ren_delay$11$next[2:0]$14294 \src2__ren
end
sync always
- update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14501
+ update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14293
end
- attribute \src "libresoc.v:202846.3-202855.6"
- process $proc$libresoc.v:202846$14503
+ attribute \src "libresoc.v:202742.3-202751.6"
+ process $proc$libresoc.v:202742$14295
assign { } { }
assign { } { }
assign $0\src2__data_o[1:0] $1\src2__data_o[1:0]
- attribute \src "libresoc.v:202847.5-202847.29"
+ attribute \src "libresoc.v:202743.5-202743.29"
switch \initial
- attribute \src "libresoc.v:202847.9-202847.17"
+ attribute \src "libresoc.v:202743.9-202743.17"
case 1'1
case
end
sync always
update \src2__data_o $0\src2__data_o[1:0]
end
- connect \$9 $or$libresoc.v:202724$14478_Y
- connect \$12 $reduce_or$libresoc.v:202725$14479_Y
- connect \$14 $or$libresoc.v:202726$14480_Y
- connect \$16 $or$libresoc.v:202727$14481_Y
- connect \$19 $reduce_or$libresoc.v:202728$14482_Y
- connect \$21 $or$libresoc.v:202729$14483_Y
- connect \$23 $or$libresoc.v:202730$14484_Y
- connect \$5 $reduce_or$libresoc.v:202731$14485_Y
- connect \$7 $or$libresoc.v:202732$14486_Y
+ connect \$9 $or$libresoc.v:202620$14270_Y
+ connect \$12 $reduce_or$libresoc.v:202621$14271_Y
+ connect \$14 $or$libresoc.v:202622$14272_Y
+ connect \$16 $or$libresoc.v:202623$14273_Y
+ connect \$19 $reduce_or$libresoc.v:202624$14274_Y
+ connect \$21 $or$libresoc.v:202625$14275_Y
+ connect \$23 $or$libresoc.v:202626$14276_Y
+ connect \$5 $reduce_or$libresoc.v:202627$14277_Y
+ connect \$7 $or$libresoc.v:202628$14278_Y
connect \full_wr__data_i 6'000000
connect \full_wr__wen 3'000
connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000
connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
end
-attribute \src "libresoc.v:202881.1-203198.10"
+attribute \src "libresoc.v:202777.1-203094.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:203062.3-203090.6"
+ attribute \src "libresoc.v:202958.3-202986.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:203113.3-203121.6"
- wire $0\core_irq_o$next[0:0]$14545
- attribute \src "libresoc.v:203001.3-203002.37"
+ attribute \src "libresoc.v:203009.3-203017.6"
+ wire $0\core_irq_o$next[0:0]$14337
+ attribute \src "libresoc.v:202897.3-202898.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $0\cppr$10[7:0]$14549
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 8 $0\cppr$next[7:0]$14528
- attribute \src "libresoc.v:203005.3-203006.25"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $0\cppr$10[7:0]$14341
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 8 $0\cppr$next[7:0]$14320
+ attribute \src "libresoc.v:202901.3-202902.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:203122.3-203131.6"
+ attribute \src "libresoc.v:203018.3-203027.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:202882.7-202882.20"
+ attribute \src "libresoc.v:202778.7-202778.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire $0\irq$12[0:0]$14550
- attribute \src "libresoc.v:203015.3-203030.6"
- wire $0\irq$next[0:0]$14529
- attribute \src "libresoc.v:203009.3-203010.23"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire $0\irq$12[0:0]$14342
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire $0\irq$next[0:0]$14321
+ attribute \src "libresoc.v:202905.3-202906.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $0\mfrr$11[7:0]$14551
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 8 $0\mfrr$next[7:0]$14530
- attribute \src "libresoc.v:203007.3-203008.25"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $0\mfrr$11[7:0]$14343
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 8 $0\mfrr$next[7:0]$14322
+ attribute \src "libresoc.v:202903.3-202904.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:203101.3-203112.6"
+ attribute \src "libresoc.v:202997.3-203008.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:203091.3-203100.6"
+ attribute \src "libresoc.v:202987.3-202996.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire $0\wb_ack$14[0:0]$14552
- attribute \src "libresoc.v:203015.3-203030.6"
- wire $0\wb_ack$next[0:0]$14531
- attribute \src "libresoc.v:203013.3-203014.29"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire $0\wb_ack$14[0:0]$14344
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire $0\wb_ack$next[0:0]$14323
+ attribute \src "libresoc.v:202909.3-202910.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 32 $0\wb_rd_data$13[31:0]$14553
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 32 $0\wb_rd_data$next[31:0]$14532
- attribute \src "libresoc.v:203011.3-203012.37"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 32 $0\wb_rd_data$13[31:0]$14345
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 32 $0\wb_rd_data$next[31:0]$14324
+ attribute \src "libresoc.v:202907.3-202908.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:203031.3-203061.6"
+ attribute \src "libresoc.v:202927.3-202957.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 24 $0\xisr$9[23:0]$14554
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 24 $0\xisr$next[23:0]$14533
- attribute \src "libresoc.v:203003.3-203004.25"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 24 $0\xisr$9[23:0]$14346
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 24 $0\xisr$next[23:0]$14325
+ attribute \src "libresoc.v:202899.3-202900.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:203062.3-203090.6"
+ attribute \src "libresoc.v:202958.3-202986.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:203113.3-203121.6"
- wire $1\core_irq_o$next[0:0]$14546
- attribute \src "libresoc.v:202911.7-202911.24"
+ attribute \src "libresoc.v:203009.3-203017.6"
+ wire $1\core_irq_o$next[0:0]$14338
+ attribute \src "libresoc.v:202807.7-202807.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $1\cppr$10[7:0]$14555
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 8 $1\cppr$next[7:0]$14534
- attribute \src "libresoc.v:202915.13-202915.25"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $1\cppr$10[7:0]$14347
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 8 $1\cppr$next[7:0]$14326
+ attribute \src "libresoc.v:202811.13-202811.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:203122.3-203131.6"
+ attribute \src "libresoc.v:203018.3-203027.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire $1\irq$12[0:0]$14565
- attribute \src "libresoc.v:203015.3-203030.6"
- wire $1\irq$next[0:0]$14535
- attribute \src "libresoc.v:202944.7-202944.17"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire $1\irq$12[0:0]$14357
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire $1\irq$next[0:0]$14327
+ attribute \src "libresoc.v:202840.7-202840.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $1\mfrr$11[7:0]$14556
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 8 $1\mfrr$next[7:0]$14536
- attribute \src "libresoc.v:202952.13-202952.25"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $1\mfrr$11[7:0]$14348
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 8 $1\mfrr$next[7:0]$14328
+ attribute \src "libresoc.v:202848.13-202848.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:203101.3-203112.6"
+ attribute \src "libresoc.v:202997.3-203008.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:203091.3-203100.6"
+ attribute \src "libresoc.v:202987.3-202996.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire $1\wb_ack$14[0:0]$14557
- attribute \src "libresoc.v:203015.3-203030.6"
- wire $1\wb_ack$next[0:0]$14537
- attribute \src "libresoc.v:202966.7-202966.20"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire $1\wb_ack$14[0:0]$14349
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire $1\wb_ack$next[0:0]$14329
+ attribute \src "libresoc.v:202862.7-202862.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 32 $1\wb_rd_data$next[31:0]$14538
- attribute \src "libresoc.v:202974.14-202974.32"
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 32 $1\wb_rd_data$next[31:0]$14330
+ attribute \src "libresoc.v:202870.14-202870.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:203031.3-203061.6"
+ attribute \src "libresoc.v:202927.3-202957.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 24 $1\xisr$9[23:0]$14562
- attribute \src "libresoc.v:203015.3-203030.6"
- wire width 24 $1\xisr$next[23:0]$14539
- attribute \src "libresoc.v:202984.14-202984.31"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 24 $1\xisr$9[23:0]$14354
+ attribute \src "libresoc.v:202911.3-202926.6"
+ wire width 24 $1\xisr$next[23:0]$14331
+ attribute \src "libresoc.v:202880.14-202880.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:203062.3-203090.6"
+ attribute \src "libresoc.v:202958.3-202986.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $2\cppr$10[7:0]$14558
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $2\mfrr$11[7:0]$14559
- attribute \src "libresoc.v:203031.3-203061.6"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $2\cppr$10[7:0]$14350
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $2\mfrr$11[7:0]$14351
+ attribute \src "libresoc.v:202927.3-202957.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 24 $2\xisr$9[23:0]$14563
- attribute \src "libresoc.v:203062.3-203090.6"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 24 $2\xisr$9[23:0]$14355
+ attribute \src "libresoc.v:202958.3-202986.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $3\cppr$10[7:0]$14560
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $3\mfrr$11[7:0]$14561
- attribute \src "libresoc.v:203031.3-203061.6"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $3\cppr$10[7:0]$14352
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $3\mfrr$11[7:0]$14353
+ attribute \src "libresoc.v:202927.3-202957.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:203132.3-203194.6"
- wire width 8 $4\cppr$10[7:0]$14564
- attribute \src "libresoc.v:203031.3-203061.6"
+ attribute \src "libresoc.v:203028.3-203090.6"
+ wire width 8 $4\cppr$10[7:0]$14356
+ attribute \src "libresoc.v:202927.3-202957.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:202991.18-202991.116"
- wire $and$libresoc.v:202991$14510_Y
- attribute \src "libresoc.v:202995.18-202995.116"
- wire $and$libresoc.v:202995$14514_Y
- attribute \src "libresoc.v:202997.18-202997.116"
- wire $and$libresoc.v:202997$14516_Y
- attribute \src "libresoc.v:203000.17-203000.109"
- wire $and$libresoc.v:203000$14519_Y
- attribute \src "libresoc.v:202996.18-202996.110"
- wire $eq$libresoc.v:202996$14515_Y
- attribute \src "libresoc.v:202993.18-202993.114"
- wire $lt$libresoc.v:202993$14512_Y
- attribute \src "libresoc.v:202994.18-202994.109"
- wire $lt$libresoc.v:202994$14513_Y
- attribute \src "libresoc.v:202999.18-202999.114"
- wire $lt$libresoc.v:202999$14518_Y
- attribute \src "libresoc.v:202992.18-202992.109"
- wire $ne$libresoc.v:202992$14511_Y
- attribute \src "libresoc.v:202998.18-202998.109"
- wire $ne$libresoc.v:202998$14517_Y
+ attribute \src "libresoc.v:202887.18-202887.116"
+ wire $and$libresoc.v:202887$14302_Y
+ attribute \src "libresoc.v:202891.18-202891.116"
+ wire $and$libresoc.v:202891$14306_Y
+ attribute \src "libresoc.v:202893.18-202893.116"
+ wire $and$libresoc.v:202893$14308_Y
+ attribute \src "libresoc.v:202896.17-202896.109"
+ wire $and$libresoc.v:202896$14311_Y
+ attribute \src "libresoc.v:202892.18-202892.110"
+ wire $eq$libresoc.v:202892$14307_Y
+ attribute \src "libresoc.v:202889.18-202889.114"
+ wire $lt$libresoc.v:202889$14304_Y
+ attribute \src "libresoc.v:202890.18-202890.109"
+ wire $lt$libresoc.v:202890$14305_Y
+ attribute \src "libresoc.v:202895.18-202895.114"
+ wire $lt$libresoc.v:202895$14310_Y
+ attribute \src "libresoc.v:202888.18-202888.109"
+ wire $ne$libresoc.v:202888$14303_Y
+ attribute \src "libresoc.v:202894.18-202894.109"
+ wire $ne$libresoc.v:202894$14309_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 13 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83"
wire output 4 \core_irq_o
wire width 8 input 3 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 input 2 \ics_i_src
- attribute \src "libresoc.v:202882.7-202882.15"
+ attribute \src "libresoc.v:202778.7-202778.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
wire width 8 \min_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106"
wire width 8 \pending_priority
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66"
wire \wb_ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:202991$14510
+ cell $and $and$libresoc.v:202887$14302
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:202991$14510_Y
+ connect \Y $and$libresoc.v:202887$14302_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:202995$14514
+ cell $and $and$libresoc.v:202891$14306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:202995$14514_Y
+ connect \Y $and$libresoc.v:202891$14306_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:202997$14516
+ cell $and $and$libresoc.v:202893$14308
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:202997$14516_Y
+ connect \Y $and$libresoc.v:202893$14308_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:203000$14519
+ cell $and $and$libresoc.v:202896$14311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:203000$14519_Y
+ connect \Y $and$libresoc.v:202896$14311_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:202996$14515
+ cell $eq $eq$libresoc.v:202892$14307
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:202996$14515_Y
+ connect \Y $eq$libresoc.v:202892$14307_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:202993$14512
+ cell $lt $lt$libresoc.v:202889$14304
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:202993$14512_Y
+ connect \Y $lt$libresoc.v:202889$14304_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:202994$14513
+ cell $lt $lt$libresoc.v:202890$14305
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:202994$14513_Y
+ connect \Y $lt$libresoc.v:202890$14305_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:202999$14518
+ cell $lt $lt$libresoc.v:202895$14310
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:202999$14518_Y
+ connect \Y $lt$libresoc.v:202895$14310_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:202992$14511
+ cell $ne $ne$libresoc.v:202888$14303
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:202992$14511_Y
+ connect \Y $ne$libresoc.v:202888$14303_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:202998$14517
+ cell $ne $ne$libresoc.v:202894$14309
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:202998$14517_Y
+ connect \Y $ne$libresoc.v:202894$14309_Y
end
- attribute \src "libresoc.v:202882.7-202882.20"
- process $proc$libresoc.v:202882$14566
+ attribute \src "libresoc.v:202778.7-202778.20"
+ process $proc$libresoc.v:202778$14358
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:202911.7-202911.24"
- process $proc$libresoc.v:202911$14567
+ attribute \src "libresoc.v:202807.7-202807.24"
+ process $proc$libresoc.v:202807$14359
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:202915.13-202915.25"
- process $proc$libresoc.v:202915$14568
+ attribute \src "libresoc.v:202811.13-202811.25"
+ process $proc$libresoc.v:202811$14360
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:202944.7-202944.17"
- process $proc$libresoc.v:202944$14569
+ attribute \src "libresoc.v:202840.7-202840.17"
+ process $proc$libresoc.v:202840$14361
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:202952.13-202952.25"
- process $proc$libresoc.v:202952$14570
+ attribute \src "libresoc.v:202848.13-202848.25"
+ process $proc$libresoc.v:202848$14362
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:202966.7-202966.20"
- process $proc$libresoc.v:202966$14571
+ attribute \src "libresoc.v:202862.7-202862.20"
+ process $proc$libresoc.v:202862$14363
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:202974.14-202974.32"
- process $proc$libresoc.v:202974$14572
+ attribute \src "libresoc.v:202870.14-202870.32"
+ process $proc$libresoc.v:202870$14364
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:202984.14-202984.31"
- process $proc$libresoc.v:202984$14573
+ attribute \src "libresoc.v:202880.14-202880.31"
+ process $proc$libresoc.v:202880$14365
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:203001.3-203002.37"
- process $proc$libresoc.v:203001$14520
+ attribute \src "libresoc.v:202897.3-202898.37"
+ process $proc$libresoc.v:202897$14312
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
sync posedge \clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:203003.3-203004.25"
- process $proc$libresoc.v:203003$14521
+ attribute \src "libresoc.v:202899.3-202900.25"
+ process $proc$libresoc.v:202899$14313
assign { } { }
assign $0\xisr[23:0] \xisr$next
sync posedge \clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:203005.3-203006.25"
- process $proc$libresoc.v:203005$14522
+ attribute \src "libresoc.v:202901.3-202902.25"
+ process $proc$libresoc.v:202901$14314
assign { } { }
assign $0\cppr[7:0] \cppr$next
sync posedge \clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:203007.3-203008.25"
- process $proc$libresoc.v:203007$14523
+ attribute \src "libresoc.v:202903.3-202904.25"
+ process $proc$libresoc.v:202903$14315
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
sync posedge \clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:203009.3-203010.23"
- process $proc$libresoc.v:203009$14524
+ attribute \src "libresoc.v:202905.3-202906.23"
+ process $proc$libresoc.v:202905$14316
assign { } { }
assign $0\irq[0:0] \irq$next
sync posedge \clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:203011.3-203012.37"
- process $proc$libresoc.v:203011$14525
+ attribute \src "libresoc.v:202907.3-202908.37"
+ process $proc$libresoc.v:202907$14317
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
sync posedge \clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:203013.3-203014.29"
- process $proc$libresoc.v:203013$14526
+ attribute \src "libresoc.v:202909.3-202910.29"
+ process $proc$libresoc.v:202909$14318
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
sync posedge \clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:203015.3-203030.6"
- process $proc$libresoc.v:203015$14527
+ attribute \src "libresoc.v:202911.3-202926.6"
+ process $proc$libresoc.v:202911$14319
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cppr$next[7:0]$14528 $1\cppr$next[7:0]$14534
- assign $0\irq$next[0:0]$14529 $1\irq$next[0:0]$14535
- assign $0\mfrr$next[7:0]$14530 $1\mfrr$next[7:0]$14536
- assign $0\wb_ack$next[0:0]$14531 $1\wb_ack$next[0:0]$14537
- assign $0\wb_rd_data$next[31:0]$14532 $1\wb_rd_data$next[31:0]$14538
- assign $0\xisr$next[23:0]$14533 $1\xisr$next[23:0]$14539
- attribute \src "libresoc.v:203016.5-203016.29"
+ assign $0\cppr$next[7:0]$14320 $1\cppr$next[7:0]$14326
+ assign $0\irq$next[0:0]$14321 $1\irq$next[0:0]$14327
+ assign $0\mfrr$next[7:0]$14322 $1\mfrr$next[7:0]$14328
+ assign $0\wb_ack$next[0:0]$14323 $1\wb_ack$next[0:0]$14329
+ assign $0\wb_rd_data$next[31:0]$14324 $1\wb_rd_data$next[31:0]$14330
+ assign $0\xisr$next[23:0]$14325 $1\xisr$next[23:0]$14331
+ attribute \src "libresoc.v:202912.5-202912.29"
switch \initial
- attribute \src "libresoc.v:203016.9-203016.17"
+ attribute \src "libresoc.v:202912.9-202912.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xisr$next[23:0]$14539 24'000000000000000000000000
- assign $1\cppr$next[7:0]$14534 8'00000000
- assign $1\mfrr$next[7:0]$14536 8'11111111
- assign $1\irq$next[0:0]$14535 1'0
- assign $1\wb_rd_data$next[31:0]$14538 0
- assign $1\wb_ack$next[0:0]$14537 1'0
+ assign $1\xisr$next[23:0]$14331 24'000000000000000000000000
+ assign $1\cppr$next[7:0]$14326 8'00000000
+ assign $1\mfrr$next[7:0]$14328 8'11111111
+ assign $1\irq$next[0:0]$14327 1'0
+ assign $1\wb_rd_data$next[31:0]$14330 0
+ assign $1\wb_ack$next[0:0]$14329 1'0
case
- assign $1\cppr$next[7:0]$14534 \cppr$2
- assign $1\irq$next[0:0]$14535 \irq$4
- assign $1\mfrr$next[7:0]$14536 \mfrr$3
- assign $1\wb_ack$next[0:0]$14537 \wb_ack$6
- assign $1\wb_rd_data$next[31:0]$14538 \wb_rd_data$5
- assign $1\xisr$next[23:0]$14539 \xisr$1
+ assign $1\cppr$next[7:0]$14326 \cppr$2
+ assign $1\irq$next[0:0]$14327 \irq$4
+ assign $1\mfrr$next[7:0]$14328 \mfrr$3
+ assign $1\wb_ack$next[0:0]$14329 \wb_ack$6
+ assign $1\wb_rd_data$next[31:0]$14330 \wb_rd_data$5
+ assign $1\xisr$next[23:0]$14331 \xisr$1
end
sync always
- update \cppr$next $0\cppr$next[7:0]$14528
- update \irq$next $0\irq$next[0:0]$14529
- update \mfrr$next $0\mfrr$next[7:0]$14530
- update \wb_ack$next $0\wb_ack$next[0:0]$14531
- update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14532
- update \xisr$next $0\xisr$next[23:0]$14533
+ update \cppr$next $0\cppr$next[7:0]$14320
+ update \irq$next $0\irq$next[0:0]$14321
+ update \mfrr$next $0\mfrr$next[7:0]$14322
+ update \wb_ack$next $0\wb_ack$next[0:0]$14323
+ update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14324
+ update \xisr$next $0\xisr$next[23:0]$14325
end
- attribute \src "libresoc.v:203031.3-203061.6"
- process $proc$libresoc.v:203031$14540
+ attribute \src "libresoc.v:202927.3-202957.6"
+ process $proc$libresoc.v:202927$14332
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:203032.5-203032.29"
+ attribute \src "libresoc.v:202928.5-202928.29"
switch \initial
- attribute \src "libresoc.v:203032.9-203032.17"
+ attribute \src "libresoc.v:202928.9-202928.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:203062.3-203090.6"
- process $proc$libresoc.v:203062$14541
+ attribute \src "libresoc.v:202958.3-202986.6"
+ process $proc$libresoc.v:202958$14333
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:203063.5-203063.29"
+ attribute \src "libresoc.v:202959.5-202959.29"
switch \initial
- attribute \src "libresoc.v:203063.9-203063.17"
+ attribute \src "libresoc.v:202959.9-202959.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:203091.3-203100.6"
- process $proc$libresoc.v:203091$14542
+ attribute \src "libresoc.v:202987.3-202996.6"
+ process $proc$libresoc.v:202987$14334
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:203092.5-203092.29"
+ attribute \src "libresoc.v:202988.5-202988.29"
switch \initial
- attribute \src "libresoc.v:203092.9-203092.17"
+ attribute \src "libresoc.v:202988.9-202988.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:203101.3-203112.6"
- process $proc$libresoc.v:203101$14543
+ attribute \src "libresoc.v:202997.3-203008.6"
+ process $proc$libresoc.v:202997$14335
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:203102.5-203102.29"
+ attribute \src "libresoc.v:202998.5-202998.29"
switch \initial
- attribute \src "libresoc.v:203102.9-203102.17"
+ attribute \src "libresoc.v:202998.9-202998.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:203113.3-203121.6"
- process $proc$libresoc.v:203113$14544
+ attribute \src "libresoc.v:203009.3-203017.6"
+ process $proc$libresoc.v:203009$14336
assign { } { }
assign { } { }
- assign $0\core_irq_o$next[0:0]$14545 $1\core_irq_o$next[0:0]$14546
- attribute \src "libresoc.v:203114.5-203114.29"
+ assign $0\core_irq_o$next[0:0]$14337 $1\core_irq_o$next[0:0]$14338
+ attribute \src "libresoc.v:203010.5-203010.29"
switch \initial
- attribute \src "libresoc.v:203114.9-203114.17"
+ attribute \src "libresoc.v:203010.9-203010.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_irq_o$next[0:0]$14546 1'0
+ assign $1\core_irq_o$next[0:0]$14338 1'0
case
- assign $1\core_irq_o$next[0:0]$14546 \irq
+ assign $1\core_irq_o$next[0:0]$14338 \irq
end
sync always
- update \core_irq_o$next $0\core_irq_o$next[0:0]$14545
+ update \core_irq_o$next $0\core_irq_o$next[0:0]$14337
end
- attribute \src "libresoc.v:203122.3-203131.6"
- process $proc$libresoc.v:203122$14547
+ attribute \src "libresoc.v:203018.3-203027.6"
+ process $proc$libresoc.v:203018$14339
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:203123.5-203123.29"
+ attribute \src "libresoc.v:203019.5-203019.29"
switch \initial
- attribute \src "libresoc.v:203123.9-203123.17"
+ attribute \src "libresoc.v:203019.9-203019.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:203132.3-203194.6"
- process $proc$libresoc.v:203132$14548
+ attribute \src "libresoc.v:203028.3-203090.6"
+ process $proc$libresoc.v:203028$14340
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mfrr$11[7:0]$14551 $1\mfrr$11[7:0]$14556
- assign $0\wb_ack$14[0:0]$14552 $1\wb_ack$14[0:0]$14557
+ assign $0\mfrr$11[7:0]$14343 $1\mfrr$11[7:0]$14348
+ assign $0\wb_ack$14[0:0]$14344 $1\wb_ack$14[0:0]$14349
assign { } { }
assign { } { }
assign { } { }
- assign $0\xisr$9[23:0]$14554 $2\xisr$9[23:0]$14563
- assign $0\cppr$10[7:0]$14549 $4\cppr$10[7:0]$14564
- assign $0\wb_rd_data$13[31:0]$14553 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
- assign $0\irq$12[0:0]$14550 $1\irq$12[0:0]$14565
- attribute \src "libresoc.v:203133.5-203133.29"
+ assign $0\xisr$9[23:0]$14346 $2\xisr$9[23:0]$14355
+ assign $0\cppr$10[7:0]$14341 $4\cppr$10[7:0]$14356
+ assign $0\wb_rd_data$13[31:0]$14345 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $0\irq$12[0:0]$14342 $1\irq$12[0:0]$14357
+ attribute \src "libresoc.v:203029.5-203029.29"
switch \initial
- attribute \src "libresoc.v:203133.9-203133.17"
+ attribute \src "libresoc.v:203029.9-203029.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wb_ack$14[0:0]$14557 1'1
- assign $1\cppr$10[7:0]$14555 $2\cppr$10[7:0]$14558
- assign $1\mfrr$11[7:0]$14556 $2\mfrr$11[7:0]$14559
+ assign $1\wb_ack$14[0:0]$14349 1'1
+ assign $1\cppr$10[7:0]$14347 $2\cppr$10[7:0]$14350
+ assign $1\mfrr$11[7:0]$14348 $2\mfrr$11[7:0]$14351
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
switch \icp_wb__we
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
- assign $2\cppr$10[7:0]$14558 $3\cppr$10[7:0]$14560
- assign $2\mfrr$11[7:0]$14559 $3\mfrr$11[7:0]$14561
+ assign $2\cppr$10[7:0]$14350 $3\cppr$10[7:0]$14352
+ assign $2\mfrr$11[7:0]$14351 $3\mfrr$11[7:0]$14353
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
switch \icp_wb__adr [5:0]
attribute \src "libresoc.v:0.0-0.0"
case 6'000000
assign { } { }
- assign $3\mfrr$11[7:0]$14561 \mfrr
- assign $3\cppr$10[7:0]$14560 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14353 \mfrr
+ assign $3\cppr$10[7:0]$14352 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000001
assign { } { }
- assign $3\mfrr$11[7:0]$14561 \mfrr
- assign $3\cppr$10[7:0]$14560 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14353 \mfrr
+ assign $3\cppr$10[7:0]$14352 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000011
- assign $3\cppr$10[7:0]$14560 \cppr
+ assign $3\cppr$10[7:0]$14352 \cppr
assign { } { }
- assign $3\mfrr$11[7:0]$14561 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$14353 \be_in [31:24]
case
- assign $3\cppr$10[7:0]$14560 \cppr
- assign $3\mfrr$11[7:0]$14561 \mfrr
+ assign $3\cppr$10[7:0]$14352 \cppr
+ assign $3\mfrr$11[7:0]$14353 \mfrr
end
case
- assign $2\cppr$10[7:0]$14558 \cppr
- assign $2\mfrr$11[7:0]$14559 \mfrr
+ assign $2\cppr$10[7:0]$14350 \cppr
+ assign $2\mfrr$11[7:0]$14351 \mfrr
end
case
- assign $1\cppr$10[7:0]$14555 \cppr
- assign $1\mfrr$11[7:0]$14556 \mfrr
- assign $1\wb_ack$14[0:0]$14557 1'0
+ assign $1\cppr$10[7:0]$14347 \cppr
+ assign $1\mfrr$11[7:0]$14348 \mfrr
+ assign $1\wb_ack$14[0:0]$14349 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xisr$9[23:0]$14562 { 20'00000000000000000001 \ics_i_src }
+ assign $1\xisr$9[23:0]$14354 { 20'00000000000000000001 \ics_i_src }
case
- assign $1\xisr$9[23:0]$14562 24'000000000000000000000000
+ assign $1\xisr$9[23:0]$14354 24'000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xisr$9[23:0]$14563 24'000000000000000000000010
+ assign $2\xisr$9[23:0]$14355 24'000000000000000000000010
case
- assign $2\xisr$9[23:0]$14563 $1\xisr$9[23:0]$14562
+ assign $2\xisr$9[23:0]$14355 $1\xisr$9[23:0]$14354
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
switch \xirr_accept_rd
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cppr$10[7:0]$14564 \min_pri
+ assign $4\cppr$10[7:0]$14356 \min_pri
case
- assign $4\cppr$10[7:0]$14564 $1\cppr$10[7:0]$14555
+ assign $4\cppr$10[7:0]$14356 $1\cppr$10[7:0]$14347
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
switch { \irq \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\irq$12[0:0]$14565 1'1
+ assign $1\irq$12[0:0]$14357 1'1
case
- assign $1\irq$12[0:0]$14565 1'0
+ assign $1\irq$12[0:0]$14357 1'0
end
sync always
- update \cppr$10 $0\cppr$10[7:0]$14549
- update \irq$12 $0\irq$12[0:0]$14550
- update \mfrr$11 $0\mfrr$11[7:0]$14551
- update \wb_ack$14 $0\wb_ack$14[0:0]$14552
- update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14553
- update \xisr$9 $0\xisr$9[23:0]$14554
+ update \cppr$10 $0\cppr$10[7:0]$14341
+ update \irq$12 $0\irq$12[0:0]$14342
+ update \mfrr$11 $0\mfrr$11[7:0]$14343
+ update \wb_ack$14 $0\wb_ack$14[0:0]$14344
+ update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14345
+ update \xisr$9 $0\xisr$9[23:0]$14346
end
- connect \$15 $and$libresoc.v:202991$14510_Y
- connect \$17 $ne$libresoc.v:202992$14511_Y
- connect \$19 $lt$libresoc.v:202993$14512_Y
- connect \$21 $lt$libresoc.v:202994$14513_Y
- connect \$23 $and$libresoc.v:202995$14514_Y
- connect \$25 $eq$libresoc.v:202996$14515_Y
- connect \$27 $and$libresoc.v:202997$14516_Y
- connect \$29 $ne$libresoc.v:202998$14517_Y
- connect \$31 $lt$libresoc.v:202999$14518_Y
- connect \$7 $and$libresoc.v:203000$14519_Y
+ connect \$15 $and$libresoc.v:202887$14302_Y
+ connect \$17 $ne$libresoc.v:202888$14303_Y
+ connect \$19 $lt$libresoc.v:202889$14304_Y
+ connect \$21 $lt$libresoc.v:202890$14305_Y
+ connect \$23 $and$libresoc.v:202891$14306_Y
+ connect \$25 $eq$libresoc.v:202892$14307_Y
+ connect \$27 $and$libresoc.v:202893$14308_Y
+ connect \$29 $ne$libresoc.v:202894$14309_Y
+ connect \$31 $lt$libresoc.v:202895$14310_Y
+ connect \$7 $and$libresoc.v:202896$14311_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:203202.1-204251.10"
+attribute \src "libresoc.v:203098.1-204147.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:204132.3-204181.6"
+ attribute \src "libresoc.v:204028.3-204077.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:203843.3-203852.6"
+ attribute \src "libresoc.v:203739.3-203748.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:204052.3-204061.6"
+ attribute \src "libresoc.v:203948.3-203957.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:204072.3-204081.6"
+ attribute \src "libresoc.v:203968.3-203977.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:204092.3-204101.6"
+ attribute \src "libresoc.v:203988.3-203997.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:204112.3-204121.6"
+ attribute \src "libresoc.v:204008.3-204017.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:204182.3-204191.6"
+ attribute \src "libresoc.v:204078.3-204087.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:204202.3-204211.6"
+ attribute \src "libresoc.v:204098.3-204107.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:203863.3-203872.6"
+ attribute \src "libresoc.v:203759.3-203768.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:203883.3-203892.6"
+ attribute \src "libresoc.v:203779.3-203788.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:203903.3-203912.6"
+ attribute \src "libresoc.v:203799.3-203808.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:203932.3-203941.6"
+ attribute \src "libresoc.v:203828.3-203837.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:203952.3-203961.6"
+ attribute \src "libresoc.v:203848.3-203857.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:203972.3-203981.6"
+ attribute \src "libresoc.v:203868.3-203877.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:203992.3-204001.6"
+ attribute \src "libresoc.v:203888.3-203897.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:204012.3-204021.6"
+ attribute \src "libresoc.v:203908.3-203917.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:204032.3-204041.6"
+ attribute \src "libresoc.v:203928.3-203937.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:203833.3-203842.6"
+ attribute \src "libresoc.v:203729.3-203738.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:204042.3-204051.6"
+ attribute \src "libresoc.v:203938.3-203947.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:204062.3-204071.6"
+ attribute \src "libresoc.v:203958.3-203967.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:204082.3-204091.6"
+ attribute \src "libresoc.v:203978.3-203987.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:204102.3-204111.6"
+ attribute \src "libresoc.v:203998.3-204007.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:204122.3-204131.6"
+ attribute \src "libresoc.v:204018.3-204027.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:204192.3-204201.6"
+ attribute \src "libresoc.v:204088.3-204097.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:203853.3-203862.6"
+ attribute \src "libresoc.v:203749.3-203758.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:203873.3-203882.6"
+ attribute \src "libresoc.v:203769.3-203778.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:203893.3-203902.6"
+ attribute \src "libresoc.v:203789.3-203798.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:203913.3-203922.6"
+ attribute \src "libresoc.v:203809.3-203818.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:203942.3-203951.6"
+ attribute \src "libresoc.v:203838.3-203847.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:203962.3-203971.6"
+ attribute \src "libresoc.v:203858.3-203867.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:203982.3-203991.6"
+ attribute \src "libresoc.v:203878.3-203887.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:204002.3-204011.6"
+ attribute \src "libresoc.v:203898.3-203907.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:204022.3-204031.6"
+ attribute \src "libresoc.v:203918.3-203927.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:204212.3-204221.6"
+ attribute \src "libresoc.v:204108.3-204117.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:203707.3-203708.25"
+ attribute \src "libresoc.v:203603.3-203604.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:203705.3-203706.28"
+ attribute \src "libresoc.v:203601.3-203602.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:204231.3-204239.6"
- wire $0\ics_wb__ack$next[0:0]$14820
- attribute \src "libresoc.v:203741.3-203742.39"
+ attribute \src "libresoc.v:204127.3-204135.6"
+ wire $0\ics_wb__ack$next[0:0]$14612
+ attribute \src "libresoc.v:203637.3-203638.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:204222.3-204230.6"
- wire width 32 $0\ics_wb__dat_r$next[31:0]$14817
- attribute \src "libresoc.v:203743.3-203744.43"
+ attribute \src "libresoc.v:204118.3-204126.6"
+ wire width 32 $0\ics_wb__dat_r$next[31:0]$14609
+ attribute \src "libresoc.v:203639.3-203640.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:203203.7-203203.20"
+ attribute \src "libresoc.v:203099.7-203099.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:203923.3-203931.6"
- wire width 16 $0\int_level_l$next[15:0]$14789
- attribute \src "libresoc.v:203745.3-203746.39"
+ attribute \src "libresoc.v:203819.3-203827.6"
+ wire width 16 $0\int_level_l$next[15:0]$14581
+ attribute \src "libresoc.v:203641.3-203642.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive0_pri$next[7:0]$14699
- attribute \src "libresoc.v:203709.3-203710.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive0_pri$next[7:0]$14491
+ attribute \src "libresoc.v:203605.3-203606.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive10_pri$next[7:0]$14700
- attribute \src "libresoc.v:203729.3-203730.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive10_pri$next[7:0]$14492
+ attribute \src "libresoc.v:203625.3-203626.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive11_pri$next[7:0]$14701
- attribute \src "libresoc.v:203731.3-203732.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive11_pri$next[7:0]$14493
+ attribute \src "libresoc.v:203627.3-203628.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive12_pri$next[7:0]$14702
- attribute \src "libresoc.v:203733.3-203734.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive12_pri$next[7:0]$14494
+ attribute \src "libresoc.v:203629.3-203630.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive13_pri$next[7:0]$14703
- attribute \src "libresoc.v:203735.3-203736.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive13_pri$next[7:0]$14495
+ attribute \src "libresoc.v:203631.3-203632.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive14_pri$next[7:0]$14704
- attribute \src "libresoc.v:203737.3-203738.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive14_pri$next[7:0]$14496
+ attribute \src "libresoc.v:203633.3-203634.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive15_pri$next[7:0]$14705
- attribute \src "libresoc.v:203739.3-203740.37"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive15_pri$next[7:0]$14497
+ attribute \src "libresoc.v:203635.3-203636.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive1_pri$next[7:0]$14706
- attribute \src "libresoc.v:203711.3-203712.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive1_pri$next[7:0]$14498
+ attribute \src "libresoc.v:203607.3-203608.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive2_pri$next[7:0]$14707
- attribute \src "libresoc.v:203713.3-203714.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive2_pri$next[7:0]$14499
+ attribute \src "libresoc.v:203609.3-203610.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive3_pri$next[7:0]$14708
- attribute \src "libresoc.v:203715.3-203716.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive3_pri$next[7:0]$14500
+ attribute \src "libresoc.v:203611.3-203612.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive4_pri$next[7:0]$14709
- attribute \src "libresoc.v:203717.3-203718.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive4_pri$next[7:0]$14501
+ attribute \src "libresoc.v:203613.3-203614.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive5_pri$next[7:0]$14710
- attribute \src "libresoc.v:203719.3-203720.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive5_pri$next[7:0]$14502
+ attribute \src "libresoc.v:203615.3-203616.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive6_pri$next[7:0]$14711
- attribute \src "libresoc.v:203721.3-203722.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive6_pri$next[7:0]$14503
+ attribute \src "libresoc.v:203617.3-203618.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive7_pri$next[7:0]$14712
- attribute \src "libresoc.v:203723.3-203724.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive7_pri$next[7:0]$14504
+ attribute \src "libresoc.v:203619.3-203620.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive8_pri$next[7:0]$14713
- attribute \src "libresoc.v:203725.3-203726.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive8_pri$next[7:0]$14505
+ attribute \src "libresoc.v:203621.3-203622.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $0\xive9_pri$next[7:0]$14714
- attribute \src "libresoc.v:203727.3-203728.35"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $0\xive9_pri$next[7:0]$14506
+ attribute \src "libresoc.v:203623.3-203624.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:204132.3-204181.6"
+ attribute \src "libresoc.v:204028.3-204077.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:203843.3-203852.6"
+ attribute \src "libresoc.v:203739.3-203748.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:204052.3-204061.6"
+ attribute \src "libresoc.v:203948.3-203957.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:204072.3-204081.6"
+ attribute \src "libresoc.v:203968.3-203977.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:204092.3-204101.6"
+ attribute \src "libresoc.v:203988.3-203997.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:204112.3-204121.6"
+ attribute \src "libresoc.v:204008.3-204017.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:204182.3-204191.6"
+ attribute \src "libresoc.v:204078.3-204087.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:204202.3-204211.6"
+ attribute \src "libresoc.v:204098.3-204107.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:203863.3-203872.6"
+ attribute \src "libresoc.v:203759.3-203768.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:203883.3-203892.6"
+ attribute \src "libresoc.v:203779.3-203788.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:203903.3-203912.6"
+ attribute \src "libresoc.v:203799.3-203808.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:203932.3-203941.6"
+ attribute \src "libresoc.v:203828.3-203837.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:203952.3-203961.6"
+ attribute \src "libresoc.v:203848.3-203857.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:203972.3-203981.6"
+ attribute \src "libresoc.v:203868.3-203877.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:203992.3-204001.6"
+ attribute \src "libresoc.v:203888.3-203897.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:204012.3-204021.6"
+ attribute \src "libresoc.v:203908.3-203917.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:204032.3-204041.6"
+ attribute \src "libresoc.v:203928.3-203937.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:203833.3-203842.6"
+ attribute \src "libresoc.v:203729.3-203738.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:204042.3-204051.6"
+ attribute \src "libresoc.v:203938.3-203947.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:204062.3-204071.6"
+ attribute \src "libresoc.v:203958.3-203967.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:204082.3-204091.6"
+ attribute \src "libresoc.v:203978.3-203987.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:204102.3-204111.6"
+ attribute \src "libresoc.v:203998.3-204007.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:204122.3-204131.6"
+ attribute \src "libresoc.v:204018.3-204027.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:204192.3-204201.6"
+ attribute \src "libresoc.v:204088.3-204097.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:203853.3-203862.6"
+ attribute \src "libresoc.v:203749.3-203758.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:203873.3-203882.6"
+ attribute \src "libresoc.v:203769.3-203778.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:203893.3-203902.6"
+ attribute \src "libresoc.v:203789.3-203798.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:203913.3-203922.6"
+ attribute \src "libresoc.v:203809.3-203818.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:203942.3-203951.6"
+ attribute \src "libresoc.v:203838.3-203847.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:203962.3-203971.6"
+ attribute \src "libresoc.v:203858.3-203867.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:203982.3-203991.6"
+ attribute \src "libresoc.v:203878.3-203887.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:204002.3-204011.6"
+ attribute \src "libresoc.v:203898.3-203907.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:204022.3-204031.6"
+ attribute \src "libresoc.v:203918.3-203927.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:204212.3-204221.6"
+ attribute \src "libresoc.v:204108.3-204117.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:203484.13-203484.30"
+ attribute \src "libresoc.v:203380.13-203380.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:203489.13-203489.29"
+ attribute \src "libresoc.v:203385.13-203385.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:204231.3-204239.6"
- wire $1\ics_wb__ack$next[0:0]$14821
- attribute \src "libresoc.v:203498.7-203498.25"
+ attribute \src "libresoc.v:204127.3-204135.6"
+ wire $1\ics_wb__ack$next[0:0]$14613
+ attribute \src "libresoc.v:203394.7-203394.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:204222.3-204230.6"
- wire width 32 $1\ics_wb__dat_r$next[31:0]$14818
- attribute \src "libresoc.v:203507.14-203507.35"
+ attribute \src "libresoc.v:204118.3-204126.6"
+ wire width 32 $1\ics_wb__dat_r$next[31:0]$14610
+ attribute \src "libresoc.v:203403.14-203403.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:203923.3-203931.6"
- wire width 16 $1\int_level_l$next[15:0]$14790
- attribute \src "libresoc.v:203519.14-203519.36"
+ attribute \src "libresoc.v:203819.3-203827.6"
+ wire width 16 $1\int_level_l$next[15:0]$14582
+ attribute \src "libresoc.v:203415.14-203415.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive0_pri$next[7:0]$14715
- attribute \src "libresoc.v:203539.13-203539.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive0_pri$next[7:0]$14507
+ attribute \src "libresoc.v:203435.13-203435.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive10_pri$next[7:0]$14716
- attribute \src "libresoc.v:203543.13-203543.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive10_pri$next[7:0]$14508
+ attribute \src "libresoc.v:203439.13-203439.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive11_pri$next[7:0]$14717
- attribute \src "libresoc.v:203547.13-203547.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive11_pri$next[7:0]$14509
+ attribute \src "libresoc.v:203443.13-203443.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive12_pri$next[7:0]$14718
- attribute \src "libresoc.v:203551.13-203551.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive12_pri$next[7:0]$14510
+ attribute \src "libresoc.v:203447.13-203447.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive13_pri$next[7:0]$14719
- attribute \src "libresoc.v:203555.13-203555.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive13_pri$next[7:0]$14511
+ attribute \src "libresoc.v:203451.13-203451.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive14_pri$next[7:0]$14720
- attribute \src "libresoc.v:203559.13-203559.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive14_pri$next[7:0]$14512
+ attribute \src "libresoc.v:203455.13-203455.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive15_pri$next[7:0]$14721
- attribute \src "libresoc.v:203563.13-203563.31"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive15_pri$next[7:0]$14513
+ attribute \src "libresoc.v:203459.13-203459.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive1_pri$next[7:0]$14722
- attribute \src "libresoc.v:203567.13-203567.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive1_pri$next[7:0]$14514
+ attribute \src "libresoc.v:203463.13-203463.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive2_pri$next[7:0]$14723
- attribute \src "libresoc.v:203571.13-203571.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive2_pri$next[7:0]$14515
+ attribute \src "libresoc.v:203467.13-203467.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive3_pri$next[7:0]$14724
- attribute \src "libresoc.v:203575.13-203575.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive3_pri$next[7:0]$14516
+ attribute \src "libresoc.v:203471.13-203471.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive4_pri$next[7:0]$14725
- attribute \src "libresoc.v:203579.13-203579.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive4_pri$next[7:0]$14517
+ attribute \src "libresoc.v:203475.13-203475.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive5_pri$next[7:0]$14726
- attribute \src "libresoc.v:203583.13-203583.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive5_pri$next[7:0]$14518
+ attribute \src "libresoc.v:203479.13-203479.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive6_pri$next[7:0]$14727
- attribute \src "libresoc.v:203587.13-203587.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive6_pri$next[7:0]$14519
+ attribute \src "libresoc.v:203483.13-203483.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive7_pri$next[7:0]$14728
- attribute \src "libresoc.v:203591.13-203591.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive7_pri$next[7:0]$14520
+ attribute \src "libresoc.v:203487.13-203487.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive8_pri$next[7:0]$14729
- attribute \src "libresoc.v:203595.13-203595.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive8_pri$next[7:0]$14521
+ attribute \src "libresoc.v:203491.13-203491.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $1\xive9_pri$next[7:0]$14730
- attribute \src "libresoc.v:203599.13-203599.30"
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $1\xive9_pri$next[7:0]$14522
+ attribute \src "libresoc.v:203495.13-203495.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:204132.3-204181.6"
+ attribute \src "libresoc.v:204028.3-204077.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive0_pri$next[7:0]$14731
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive10_pri$next[7:0]$14732
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive11_pri$next[7:0]$14733
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive12_pri$next[7:0]$14734
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive13_pri$next[7:0]$14735
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive14_pri$next[7:0]$14736
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive15_pri$next[7:0]$14737
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive1_pri$next[7:0]$14738
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive2_pri$next[7:0]$14739
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive3_pri$next[7:0]$14740
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive4_pri$next[7:0]$14741
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive5_pri$next[7:0]$14742
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive6_pri$next[7:0]$14743
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive7_pri$next[7:0]$14744
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive8_pri$next[7:0]$14745
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $2\xive9_pri$next[7:0]$14746
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive0_pri$next[7:0]$14747
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive10_pri$next[7:0]$14748
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive11_pri$next[7:0]$14749
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive12_pri$next[7:0]$14750
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive13_pri$next[7:0]$14751
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive14_pri$next[7:0]$14752
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive15_pri$next[7:0]$14753
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive1_pri$next[7:0]$14754
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive2_pri$next[7:0]$14755
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive3_pri$next[7:0]$14756
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive4_pri$next[7:0]$14757
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive5_pri$next[7:0]$14758
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive6_pri$next[7:0]$14759
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive7_pri$next[7:0]$14760
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive8_pri$next[7:0]$14761
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $3\xive9_pri$next[7:0]$14762
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive0_pri$next[7:0]$14763
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive10_pri$next[7:0]$14764
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive11_pri$next[7:0]$14765
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive12_pri$next[7:0]$14766
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive13_pri$next[7:0]$14767
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive14_pri$next[7:0]$14768
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive15_pri$next[7:0]$14769
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive1_pri$next[7:0]$14770
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive2_pri$next[7:0]$14771
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive3_pri$next[7:0]$14772
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive4_pri$next[7:0]$14773
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive5_pri$next[7:0]$14774
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive6_pri$next[7:0]$14775
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive7_pri$next[7:0]$14776
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive8_pri$next[7:0]$14777
- attribute \src "libresoc.v:203747.3-203832.6"
- wire width 8 $4\xive9_pri$next[7:0]$14778
- attribute \src "libresoc.v:203604.19-203604.113"
- wire $and$libresoc.v:203604$14576_Y
- attribute \src "libresoc.v:203606.19-203606.114"
- wire $and$libresoc.v:203606$14578_Y
- attribute \src "libresoc.v:203608.19-203608.114"
- wire $and$libresoc.v:203608$14580_Y
- attribute \src "libresoc.v:203610.19-203610.114"
- wire $and$libresoc.v:203610$14582_Y
- attribute \src "libresoc.v:203612.19-203612.114"
- wire $and$libresoc.v:203612$14584_Y
- attribute \src "libresoc.v:203614.19-203614.114"
- wire $and$libresoc.v:203614$14586_Y
- attribute \src "libresoc.v:203616.19-203616.114"
- wire $and$libresoc.v:203616$14588_Y
- attribute \src "libresoc.v:203619.19-203619.114"
- wire $and$libresoc.v:203619$14591_Y
- attribute \src "libresoc.v:203621.19-203621.114"
- wire $and$libresoc.v:203621$14593_Y
- attribute \src "libresoc.v:203623.19-203623.114"
- wire $and$libresoc.v:203623$14595_Y
- attribute \src "libresoc.v:203626.19-203626.114"
- wire $and$libresoc.v:203626$14598_Y
- attribute \src "libresoc.v:203628.19-203628.114"
- wire $and$libresoc.v:203628$14600_Y
- attribute \src "libresoc.v:203630.19-203630.114"
- wire $and$libresoc.v:203630$14602_Y
- attribute \src "libresoc.v:203632.19-203632.114"
- wire $and$libresoc.v:203632$14604_Y
- attribute \src "libresoc.v:203634.19-203634.115"
- wire $and$libresoc.v:203634$14606_Y
- attribute \src "libresoc.v:203636.19-203636.115"
- wire $and$libresoc.v:203636$14608_Y
- attribute \src "libresoc.v:203638.19-203638.115"
- wire $and$libresoc.v:203638$14610_Y
- attribute \src "libresoc.v:203641.19-203641.115"
- wire $and$libresoc.v:203641$14613_Y
- attribute \src "libresoc.v:203643.19-203643.115"
- wire $and$libresoc.v:203643$14615_Y
- attribute \src "libresoc.v:203645.19-203645.115"
- wire $and$libresoc.v:203645$14617_Y
- attribute \src "libresoc.v:203648.19-203648.115"
- wire $and$libresoc.v:203648$14620_Y
- attribute \src "libresoc.v:203650.19-203650.115"
- wire $and$libresoc.v:203650$14622_Y
- attribute \src "libresoc.v:203652.19-203652.115"
- wire $and$libresoc.v:203652$14624_Y
- attribute \src "libresoc.v:203654.19-203654.115"
- wire $and$libresoc.v:203654$14626_Y
- attribute \src "libresoc.v:203656.19-203656.115"
- wire $and$libresoc.v:203656$14628_Y
- attribute \src "libresoc.v:203659.19-203659.115"
- wire $and$libresoc.v:203659$14631_Y
- attribute \src "libresoc.v:203683.17-203683.115"
- wire $and$libresoc.v:203683$14655_Y
- attribute \src "libresoc.v:203691.18-203691.112"
- wire $and$libresoc.v:203691$14663_Y
- attribute \src "libresoc.v:203693.18-203693.112"
- wire $and$libresoc.v:203693$14665_Y
- attribute \src "libresoc.v:203695.18-203695.112"
- wire $and$libresoc.v:203695$14667_Y
- attribute \src "libresoc.v:203697.18-203697.112"
- wire $and$libresoc.v:203697$14669_Y
- attribute \src "libresoc.v:203700.18-203700.112"
- wire $and$libresoc.v:203700$14672_Y
- attribute \src "libresoc.v:203702.18-203702.112"
- wire $and$libresoc.v:203702$14674_Y
- attribute \src "libresoc.v:203704.18-203704.112"
- wire $and$libresoc.v:203704$14676_Y
- attribute \src "libresoc.v:203618.18-203618.109"
- wire $eq$libresoc.v:203618$14590_Y
- attribute \src "libresoc.v:203640.18-203640.109"
- wire $eq$libresoc.v:203640$14612_Y
- attribute \src "libresoc.v:203657.17-203657.114"
- wire $eq$libresoc.v:203657$14629_Y
- attribute \src "libresoc.v:203660.19-203660.110"
- wire $eq$libresoc.v:203660$14632_Y
- attribute \src "libresoc.v:203662.18-203662.109"
- wire $eq$libresoc.v:203662$14634_Y
- attribute \src "libresoc.v:203664.18-203664.109"
- wire $eq$libresoc.v:203664$14636_Y
- attribute \src "libresoc.v:203666.18-203666.109"
- wire $eq$libresoc.v:203666$14638_Y
- attribute \src "libresoc.v:203668.18-203668.109"
- wire $eq$libresoc.v:203668$14640_Y
- attribute \src "libresoc.v:203670.18-203670.109"
- wire $eq$libresoc.v:203670$14642_Y
- attribute \src "libresoc.v:203672.17-203672.114"
- wire $eq$libresoc.v:203672$14644_Y
- attribute \src "libresoc.v:203673.18-203673.109"
- wire $eq$libresoc.v:203673$14645_Y
- attribute \src "libresoc.v:203675.18-203675.109"
- wire $eq$libresoc.v:203675$14647_Y
- attribute \src "libresoc.v:203677.18-203677.110"
- wire $eq$libresoc.v:203677$14649_Y
- attribute \src "libresoc.v:203679.18-203679.110"
- wire $eq$libresoc.v:203679$14651_Y
- attribute \src "libresoc.v:203681.18-203681.110"
- wire $eq$libresoc.v:203681$14653_Y
- attribute \src "libresoc.v:203684.18-203684.110"
- wire $eq$libresoc.v:203684$14656_Y
- attribute \src "libresoc.v:203686.18-203686.110"
- wire $eq$libresoc.v:203686$14658_Y
- attribute \src "libresoc.v:203688.18-203688.110"
- wire $eq$libresoc.v:203688$14660_Y
- attribute \src "libresoc.v:203699.17-203699.108"
- wire $eq$libresoc.v:203699$14671_Y
- attribute \src "libresoc.v:203603.18-203603.111"
- wire $lt$libresoc.v:203603$14575_Y
- attribute \src "libresoc.v:203605.19-203605.112"
- wire $lt$libresoc.v:203605$14577_Y
- attribute \src "libresoc.v:203607.19-203607.112"
- wire $lt$libresoc.v:203607$14579_Y
- attribute \src "libresoc.v:203609.19-203609.112"
- wire $lt$libresoc.v:203609$14581_Y
- attribute \src "libresoc.v:203611.19-203611.112"
- wire $lt$libresoc.v:203611$14583_Y
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- wire $lt$libresoc.v:203613$14585_Y
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- wire $lt$libresoc.v:203637$14609_Y
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- wire width 8 $ternary$libresoc.v:203669$14641_Y
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- wire width 8 $ternary$libresoc.v:203676$14648_Y
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- wire width 8 $ternary$libresoc.v:203680$14652_Y
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- wire width 8 $ternary$libresoc.v:203685$14657_Y
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- wire width 8 $ternary$libresoc.v:203687$14659_Y
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- wire width 8 $ternary$libresoc.v:203689$14661_Y
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
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+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive15_pri$next[7:0]$14561
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+ wire width 8 $4\xive1_pri$next[7:0]$14562
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive2_pri$next[7:0]$14563
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive3_pri$next[7:0]$14564
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive4_pri$next[7:0]$14565
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive5_pri$next[7:0]$14566
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive6_pri$next[7:0]$14567
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive7_pri$next[7:0]$14568
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive8_pri$next[7:0]$14569
+ attribute \src "libresoc.v:203643.3-203728.6"
+ wire width 8 $4\xive9_pri$next[7:0]$14570
+ attribute \src "libresoc.v:203500.19-203500.113"
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+ wire $and$libresoc.v:203517$14385_Y
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+ wire $and$libresoc.v:203530$14398_Y
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+ wire $and$libresoc.v:203532$14400_Y
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+ wire $and$libresoc.v:203534$14402_Y
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+ wire $and$libresoc.v:203537$14405_Y
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+ wire $and$libresoc.v:203541$14409_Y
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+ wire $eq$libresoc.v:203569$14437_Y
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+ wire $lt$libresoc.v:203554$14422_Y
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+ wire $lt$libresoc.v:203588$14456_Y
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+ wire $lt$libresoc.v:203590$14458_Y
+ attribute \src "libresoc.v:203592.18-203592.111"
+ wire $lt$libresoc.v:203592$14460_Y
+ attribute \src "libresoc.v:203594.18-203594.111"
+ wire $lt$libresoc.v:203594$14462_Y
+ attribute \src "libresoc.v:203597.18-203597.111"
+ wire $lt$libresoc.v:203597$14465_Y
+ attribute \src "libresoc.v:203599.18-203599.111"
+ wire $lt$libresoc.v:203599$14467_Y
+ attribute \src "libresoc.v:203586.18-203586.40"
+ wire width 16 $shr$libresoc.v:203586$14454_Y
+ attribute \src "libresoc.v:203498.17-203498.114"
+ wire width 8 $ternary$libresoc.v:203498$14366_Y
+ attribute \src "libresoc.v:203520.18-203520.116"
+ wire width 8 $ternary$libresoc.v:203520$14388_Y
+ attribute \src "libresoc.v:203542.18-203542.116"
+ wire width 8 $ternary$libresoc.v:203542$14410_Y
+ attribute \src "libresoc.v:203557.19-203557.118"
+ wire width 8 $ternary$libresoc.v:203557$14425_Y
+ attribute \src "libresoc.v:203559.18-203559.116"
+ wire width 8 $ternary$libresoc.v:203559$14427_Y
+ attribute \src "libresoc.v:203561.18-203561.116"
+ wire width 8 $ternary$libresoc.v:203561$14429_Y
+ attribute \src "libresoc.v:203563.18-203563.116"
+ wire width 8 $ternary$libresoc.v:203563$14431_Y
+ attribute \src "libresoc.v:203565.18-203565.116"
+ wire width 8 $ternary$libresoc.v:203565$14433_Y
+ attribute \src "libresoc.v:203567.18-203567.116"
+ wire width 8 $ternary$libresoc.v:203567$14435_Y
+ attribute \src "libresoc.v:203570.18-203570.116"
+ wire width 8 $ternary$libresoc.v:203570$14438_Y
+ attribute \src "libresoc.v:203572.18-203572.116"
+ wire width 8 $ternary$libresoc.v:203572$14440_Y
+ attribute \src "libresoc.v:203574.18-203574.117"
+ wire width 8 $ternary$libresoc.v:203574$14442_Y
+ attribute \src "libresoc.v:203576.18-203576.117"
+ wire width 8 $ternary$libresoc.v:203576$14444_Y
+ attribute \src "libresoc.v:203578.18-203578.117"
+ wire width 8 $ternary$libresoc.v:203578$14446_Y
+ attribute \src "libresoc.v:203581.18-203581.117"
+ wire width 8 $ternary$libresoc.v:203581$14449_Y
+ attribute \src "libresoc.v:203583.18-203583.117"
+ wire width 8 $ternary$libresoc.v:203583$14451_Y
+ attribute \src "libresoc.v:203585.18-203585.117"
+ wire width 8 $ternary$libresoc.v:203585$14453_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire width 32 \be_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308"
wire width 32 \be_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 12 \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365"
wire width 4 \cur_idx0
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:203203.7-203203.15"
+ attribute \src "libresoc.v:203099.7-203099.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
wire \reg_is_debug
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286"
wire \reg_is_xive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794"
wire input 1 \rst
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260"
wire \wb_valid
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203604$14576
+ cell $and $and$libresoc.v:203500$14368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:203604$14576_Y
+ connect \Y $and$libresoc.v:203500$14368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203606$14578
+ cell $and $and$libresoc.v:203502$14370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:203606$14578_Y
+ connect \Y $and$libresoc.v:203502$14370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203608$14580
+ cell $and $and$libresoc.v:203504$14372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:203608$14580_Y
+ connect \Y $and$libresoc.v:203504$14372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203610$14582
+ cell $and $and$libresoc.v:203506$14374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:203610$14582_Y
+ connect \Y $and$libresoc.v:203506$14374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203612$14584
+ cell $and $and$libresoc.v:203508$14376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:203612$14584_Y
+ connect \Y $and$libresoc.v:203508$14376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203614$14586
+ cell $and $and$libresoc.v:203510$14378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:203614$14586_Y
+ connect \Y $and$libresoc.v:203510$14378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203616$14588
+ cell $and $and$libresoc.v:203512$14380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:203616$14588_Y
+ connect \Y $and$libresoc.v:203512$14380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203619$14591
+ cell $and $and$libresoc.v:203515$14383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:203619$14591_Y
+ connect \Y $and$libresoc.v:203515$14383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203621$14593
+ cell $and $and$libresoc.v:203517$14385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:203621$14593_Y
+ connect \Y $and$libresoc.v:203517$14385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203623$14595
+ cell $and $and$libresoc.v:203519$14387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:203623$14595_Y
+ connect \Y $and$libresoc.v:203519$14387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203626$14598
+ cell $and $and$libresoc.v:203522$14390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:203626$14598_Y
+ connect \Y $and$libresoc.v:203522$14390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203628$14600
+ cell $and $and$libresoc.v:203524$14392
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:203628$14600_Y
+ connect \Y $and$libresoc.v:203524$14392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203630$14602
+ cell $and $and$libresoc.v:203526$14394
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:203630$14602_Y
+ connect \Y $and$libresoc.v:203526$14394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203632$14604
+ cell $and $and$libresoc.v:203528$14396
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:203632$14604_Y
+ connect \Y $and$libresoc.v:203528$14396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203634$14606
+ cell $and $and$libresoc.v:203530$14398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:203634$14606_Y
+ connect \Y $and$libresoc.v:203530$14398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203636$14608
+ cell $and $and$libresoc.v:203532$14400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:203636$14608_Y
+ connect \Y $and$libresoc.v:203532$14400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203638$14610
+ cell $and $and$libresoc.v:203534$14402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:203638$14610_Y
+ connect \Y $and$libresoc.v:203534$14402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203641$14613
+ cell $and $and$libresoc.v:203537$14405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:203641$14613_Y
+ connect \Y $and$libresoc.v:203537$14405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203643$14615
+ cell $and $and$libresoc.v:203539$14407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:203643$14615_Y
+ connect \Y $and$libresoc.v:203539$14407_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203645$14617
+ cell $and $and$libresoc.v:203541$14409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:203645$14617_Y
+ connect \Y $and$libresoc.v:203541$14409_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203648$14620
+ cell $and $and$libresoc.v:203544$14412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:203648$14620_Y
+ connect \Y $and$libresoc.v:203544$14412_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203650$14622
+ cell $and $and$libresoc.v:203546$14414
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:203650$14622_Y
+ connect \Y $and$libresoc.v:203546$14414_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203652$14624
+ cell $and $and$libresoc.v:203548$14416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:203652$14624_Y
+ connect \Y $and$libresoc.v:203548$14416_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203654$14626
+ cell $and $and$libresoc.v:203550$14418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:203654$14626_Y
+ connect \Y $and$libresoc.v:203550$14418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203656$14628
+ cell $and $and$libresoc.v:203552$14420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:203656$14628_Y
+ connect \Y $and$libresoc.v:203552$14420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203659$14631
+ cell $and $and$libresoc.v:203555$14423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:203659$14631_Y
+ connect \Y $and$libresoc.v:203555$14423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:203683$14655
+ cell $and $and$libresoc.v:203579$14447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:203683$14655_Y
+ connect \Y $and$libresoc.v:203579$14447_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:203691$14663
+ cell $and $and$libresoc.v:203587$14455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:203691$14663_Y
+ connect \Y $and$libresoc.v:203587$14455_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203693$14665
+ cell $and $and$libresoc.v:203589$14457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:203693$14665_Y
+ connect \Y $and$libresoc.v:203589$14457_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203695$14667
+ cell $and $and$libresoc.v:203591$14459
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:203695$14667_Y
+ connect \Y $and$libresoc.v:203591$14459_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203697$14669
+ cell $and $and$libresoc.v:203593$14461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:203697$14669_Y
+ connect \Y $and$libresoc.v:203593$14461_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203700$14672
+ cell $and $and$libresoc.v:203596$14464
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:203700$14672_Y
+ connect \Y $and$libresoc.v:203596$14464_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203702$14674
+ cell $and $and$libresoc.v:203598$14466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:203702$14674_Y
+ connect \Y $and$libresoc.v:203598$14466_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:203704$14676
+ cell $and $and$libresoc.v:203600$14468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:203704$14676_Y
+ connect \Y $and$libresoc.v:203600$14468_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203618$14590
+ cell $eq $eq$libresoc.v:203514$14382
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203618$14590_Y
+ connect \Y $eq$libresoc.v:203514$14382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203640$14612
+ cell $eq $eq$libresoc.v:203536$14404
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203640$14612_Y
+ connect \Y $eq$libresoc.v:203536$14404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:203657$14629
+ cell $eq $eq$libresoc.v:203553$14421
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:203657$14629_Y
+ connect \Y $eq$libresoc.v:203553$14421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203660$14632
+ cell $eq $eq$libresoc.v:203556$14424
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203660$14632_Y
+ connect \Y $eq$libresoc.v:203556$14424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203662$14634
+ cell $eq $eq$libresoc.v:203558$14426
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203662$14634_Y
+ connect \Y $eq$libresoc.v:203558$14426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203664$14636
+ cell $eq $eq$libresoc.v:203560$14428
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203664$14636_Y
+ connect \Y $eq$libresoc.v:203560$14428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203666$14638
+ cell $eq $eq$libresoc.v:203562$14430
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203666$14638_Y
+ connect \Y $eq$libresoc.v:203562$14430_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203668$14640
+ cell $eq $eq$libresoc.v:203564$14432
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203668$14640_Y
+ connect \Y $eq$libresoc.v:203564$14432_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203670$14642
+ cell $eq $eq$libresoc.v:203566$14434
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203670$14642_Y
+ connect \Y $eq$libresoc.v:203566$14434_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:203672$14644
+ cell $eq $eq$libresoc.v:203568$14436
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:203672$14644_Y
+ connect \Y $eq$libresoc.v:203568$14436_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203673$14645
+ cell $eq $eq$libresoc.v:203569$14437
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203673$14645_Y
+ connect \Y $eq$libresoc.v:203569$14437_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203675$14647
+ cell $eq $eq$libresoc.v:203571$14439
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203675$14647_Y
+ connect \Y $eq$libresoc.v:203571$14439_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203677$14649
+ cell $eq $eq$libresoc.v:203573$14441
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203677$14649_Y
+ connect \Y $eq$libresoc.v:203573$14441_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203679$14651
+ cell $eq $eq$libresoc.v:203575$14443
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203679$14651_Y
+ connect \Y $eq$libresoc.v:203575$14443_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203681$14653
+ cell $eq $eq$libresoc.v:203577$14445
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203681$14653_Y
+ connect \Y $eq$libresoc.v:203577$14445_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203684$14656
+ cell $eq $eq$libresoc.v:203580$14448
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203684$14656_Y
+ connect \Y $eq$libresoc.v:203580$14448_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203686$14658
+ cell $eq $eq$libresoc.v:203582$14450
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203686$14658_Y
+ connect \Y $eq$libresoc.v:203582$14450_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203688$14660
+ cell $eq $eq$libresoc.v:203584$14452
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203688$14660_Y
+ connect \Y $eq$libresoc.v:203584$14452_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:203699$14671
+ cell $eq $eq$libresoc.v:203595$14463
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:203699$14671_Y
+ connect \Y $eq$libresoc.v:203595$14463_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203603$14575
+ cell $lt $lt$libresoc.v:203499$14367
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:203603$14575_Y
+ connect \Y $lt$libresoc.v:203499$14367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203605$14577
+ cell $lt $lt$libresoc.v:203501$14369
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:203605$14577_Y
+ connect \Y $lt$libresoc.v:203501$14369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203607$14579
+ cell $lt $lt$libresoc.v:203503$14371
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:203607$14579_Y
+ connect \Y $lt$libresoc.v:203503$14371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203609$14581
+ cell $lt $lt$libresoc.v:203505$14373
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:203609$14581_Y
+ connect \Y $lt$libresoc.v:203505$14373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203611$14583
+ cell $lt $lt$libresoc.v:203507$14375
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:203611$14583_Y
+ connect \Y $lt$libresoc.v:203507$14375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203613$14585
+ cell $lt $lt$libresoc.v:203509$14377
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:203613$14585_Y
+ connect \Y $lt$libresoc.v:203509$14377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203615$14587
+ cell $lt $lt$libresoc.v:203511$14379
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:203615$14587_Y
+ connect \Y $lt$libresoc.v:203511$14379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203617$14589
+ cell $lt $lt$libresoc.v:203513$14381
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:203617$14589_Y
+ connect \Y $lt$libresoc.v:203513$14381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203620$14592
+ cell $lt $lt$libresoc.v:203516$14384
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:203620$14592_Y
+ connect \Y $lt$libresoc.v:203516$14384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203622$14594
+ cell $lt $lt$libresoc.v:203518$14386
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:203622$14594_Y
+ connect \Y $lt$libresoc.v:203518$14386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203625$14597
+ cell $lt $lt$libresoc.v:203521$14389
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:203625$14597_Y
+ connect \Y $lt$libresoc.v:203521$14389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203627$14599
+ cell $lt $lt$libresoc.v:203523$14391
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:203627$14599_Y
+ connect \Y $lt$libresoc.v:203523$14391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203629$14601
+ cell $lt $lt$libresoc.v:203525$14393
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:203629$14601_Y
+ connect \Y $lt$libresoc.v:203525$14393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203631$14603
+ cell $lt $lt$libresoc.v:203527$14395
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:203631$14603_Y
+ connect \Y $lt$libresoc.v:203527$14395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203633$14605
+ cell $lt $lt$libresoc.v:203529$14397
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:203633$14605_Y
+ connect \Y $lt$libresoc.v:203529$14397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203635$14607
+ cell $lt $lt$libresoc.v:203531$14399
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:203635$14607_Y
+ connect \Y $lt$libresoc.v:203531$14399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203637$14609
+ cell $lt $lt$libresoc.v:203533$14401
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:203637$14609_Y
+ connect \Y $lt$libresoc.v:203533$14401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203639$14611
+ cell $lt $lt$libresoc.v:203535$14403
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:203639$14611_Y
+ connect \Y $lt$libresoc.v:203535$14403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203642$14614
+ cell $lt $lt$libresoc.v:203538$14406
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:203642$14614_Y
+ connect \Y $lt$libresoc.v:203538$14406_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203644$14616
+ cell $lt $lt$libresoc.v:203540$14408
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:203644$14616_Y
+ connect \Y $lt$libresoc.v:203540$14408_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203647$14619
+ cell $lt $lt$libresoc.v:203543$14411
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:203647$14619_Y
+ connect \Y $lt$libresoc.v:203543$14411_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203649$14621
+ cell $lt $lt$libresoc.v:203545$14413
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:203649$14621_Y
+ connect \Y $lt$libresoc.v:203545$14413_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203651$14623
+ cell $lt $lt$libresoc.v:203547$14415
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:203651$14623_Y
+ connect \Y $lt$libresoc.v:203547$14415_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203653$14625
+ cell $lt $lt$libresoc.v:203549$14417
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:203653$14625_Y
+ connect \Y $lt$libresoc.v:203549$14417_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203655$14627
+ cell $lt $lt$libresoc.v:203551$14419
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:203655$14627_Y
+ connect \Y $lt$libresoc.v:203551$14419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203658$14630
+ cell $lt $lt$libresoc.v:203554$14422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:203658$14630_Y
+ connect \Y $lt$libresoc.v:203554$14422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203692$14664
+ cell $lt $lt$libresoc.v:203588$14456
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:203692$14664_Y
+ connect \Y $lt$libresoc.v:203588$14456_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203694$14666
+ cell $lt $lt$libresoc.v:203590$14458
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:203694$14666_Y
+ connect \Y $lt$libresoc.v:203590$14458_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203696$14668
+ cell $lt $lt$libresoc.v:203592$14460
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:203696$14668_Y
+ connect \Y $lt$libresoc.v:203592$14460_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203698$14670
+ cell $lt $lt$libresoc.v:203594$14462
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:203698$14670_Y
+ connect \Y $lt$libresoc.v:203594$14462_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203701$14673
+ cell $lt $lt$libresoc.v:203597$14465
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:203701$14673_Y
+ connect \Y $lt$libresoc.v:203597$14465_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:203703$14675
+ cell $lt $lt$libresoc.v:203599$14467
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:203703$14675_Y
+ connect \Y $lt$libresoc.v:203599$14467_Y
end
- attribute \src "libresoc.v:203690.18-203690.40"
- cell $shr $shr$libresoc.v:203690$14662
+ attribute \src "libresoc.v:203586.18-203586.40"
+ cell $shr $shr$libresoc.v:203586$14454
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:203690$14662_Y
+ connect \Y $shr$libresoc.v:203586$14454_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203602$14574
+ cell $mux $ternary$libresoc.v:203498$14366
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:203602$14574_Y
+ connect \Y $ternary$libresoc.v:203498$14366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203624$14596
+ cell $mux $ternary$libresoc.v:203520$14388
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:203624$14596_Y
+ connect \Y $ternary$libresoc.v:203520$14388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203646$14618
+ cell $mux $ternary$libresoc.v:203542$14410
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:203646$14618_Y
+ connect \Y $ternary$libresoc.v:203542$14410_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203661$14633
+ cell $mux $ternary$libresoc.v:203557$14425
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:203661$14633_Y
+ connect \Y $ternary$libresoc.v:203557$14425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203663$14635
+ cell $mux $ternary$libresoc.v:203559$14427
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:203663$14635_Y
+ connect \Y $ternary$libresoc.v:203559$14427_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203665$14637
+ cell $mux $ternary$libresoc.v:203561$14429
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:203665$14637_Y
+ connect \Y $ternary$libresoc.v:203561$14429_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203667$14639
+ cell $mux $ternary$libresoc.v:203563$14431
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:203667$14639_Y
+ connect \Y $ternary$libresoc.v:203563$14431_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203669$14641
+ cell $mux $ternary$libresoc.v:203565$14433
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:203669$14641_Y
+ connect \Y $ternary$libresoc.v:203565$14433_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203671$14643
+ cell $mux $ternary$libresoc.v:203567$14435
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:203671$14643_Y
+ connect \Y $ternary$libresoc.v:203567$14435_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203674$14646
+ cell $mux $ternary$libresoc.v:203570$14438
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:203674$14646_Y
+ connect \Y $ternary$libresoc.v:203570$14438_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203676$14648
+ cell $mux $ternary$libresoc.v:203572$14440
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:203676$14648_Y
+ connect \Y $ternary$libresoc.v:203572$14440_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203678$14650
+ cell $mux $ternary$libresoc.v:203574$14442
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:203678$14650_Y
+ connect \Y $ternary$libresoc.v:203574$14442_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203680$14652
+ cell $mux $ternary$libresoc.v:203576$14444
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:203680$14652_Y
+ connect \Y $ternary$libresoc.v:203576$14444_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203682$14654
+ cell $mux $ternary$libresoc.v:203578$14446
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:203682$14654_Y
+ connect \Y $ternary$libresoc.v:203578$14446_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203685$14657
+ cell $mux $ternary$libresoc.v:203581$14449
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:203685$14657_Y
+ connect \Y $ternary$libresoc.v:203581$14449_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203687$14659
+ cell $mux $ternary$libresoc.v:203583$14451
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:203687$14659_Y
+ connect \Y $ternary$libresoc.v:203583$14451_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:203689$14661
+ cell $mux $ternary$libresoc.v:203585$14453
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:203689$14661_Y
+ connect \Y $ternary$libresoc.v:203585$14453_Y
end
- attribute \src "libresoc.v:203203.7-203203.20"
- process $proc$libresoc.v:203203$14822
+ attribute \src "libresoc.v:203099.7-203099.20"
+ process $proc$libresoc.v:203099$14614
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:203484.13-203484.30"
- process $proc$libresoc.v:203484$14823
+ attribute \src "libresoc.v:203380.13-203380.30"
+ process $proc$libresoc.v:203380$14615
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:203489.13-203489.29"
- process $proc$libresoc.v:203489$14824
+ attribute \src "libresoc.v:203385.13-203385.29"
+ process $proc$libresoc.v:203385$14616
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:203498.7-203498.25"
- process $proc$libresoc.v:203498$14825
+ attribute \src "libresoc.v:203394.7-203394.25"
+ process $proc$libresoc.v:203394$14617
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:203507.14-203507.35"
- process $proc$libresoc.v:203507$14826
+ attribute \src "libresoc.v:203403.14-203403.35"
+ process $proc$libresoc.v:203403$14618
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:203519.14-203519.36"
- process $proc$libresoc.v:203519$14827
+ attribute \src "libresoc.v:203415.14-203415.36"
+ process $proc$libresoc.v:203415$14619
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:203539.13-203539.30"
- process $proc$libresoc.v:203539$14828
+ attribute \src "libresoc.v:203435.13-203435.30"
+ process $proc$libresoc.v:203435$14620
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:203543.13-203543.31"
- process $proc$libresoc.v:203543$14829
+ attribute \src "libresoc.v:203439.13-203439.31"
+ process $proc$libresoc.v:203439$14621
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:203547.13-203547.31"
- process $proc$libresoc.v:203547$14830
+ attribute \src "libresoc.v:203443.13-203443.31"
+ process $proc$libresoc.v:203443$14622
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:203551.13-203551.31"
- process $proc$libresoc.v:203551$14831
+ attribute \src "libresoc.v:203447.13-203447.31"
+ process $proc$libresoc.v:203447$14623
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:203555.13-203555.31"
- process $proc$libresoc.v:203555$14832
+ attribute \src "libresoc.v:203451.13-203451.31"
+ process $proc$libresoc.v:203451$14624
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:203559.13-203559.31"
- process $proc$libresoc.v:203559$14833
+ attribute \src "libresoc.v:203455.13-203455.31"
+ process $proc$libresoc.v:203455$14625
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:203563.13-203563.31"
- process $proc$libresoc.v:203563$14834
+ attribute \src "libresoc.v:203459.13-203459.31"
+ process $proc$libresoc.v:203459$14626
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:203567.13-203567.30"
- process $proc$libresoc.v:203567$14835
+ attribute \src "libresoc.v:203463.13-203463.30"
+ process $proc$libresoc.v:203463$14627
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:203571.13-203571.30"
- process $proc$libresoc.v:203571$14836
+ attribute \src "libresoc.v:203467.13-203467.30"
+ process $proc$libresoc.v:203467$14628
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:203575.13-203575.30"
- process $proc$libresoc.v:203575$14837
+ attribute \src "libresoc.v:203471.13-203471.30"
+ process $proc$libresoc.v:203471$14629
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:203579.13-203579.30"
- process $proc$libresoc.v:203579$14838
+ attribute \src "libresoc.v:203475.13-203475.30"
+ process $proc$libresoc.v:203475$14630
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:203583.13-203583.30"
- process $proc$libresoc.v:203583$14839
+ attribute \src "libresoc.v:203479.13-203479.30"
+ process $proc$libresoc.v:203479$14631
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:203587.13-203587.30"
- process $proc$libresoc.v:203587$14840
+ attribute \src "libresoc.v:203483.13-203483.30"
+ process $proc$libresoc.v:203483$14632
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:203591.13-203591.30"
- process $proc$libresoc.v:203591$14841
+ attribute \src "libresoc.v:203487.13-203487.30"
+ process $proc$libresoc.v:203487$14633
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:203595.13-203595.30"
- process $proc$libresoc.v:203595$14842
+ attribute \src "libresoc.v:203491.13-203491.30"
+ process $proc$libresoc.v:203491$14634
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:203599.13-203599.30"
- process $proc$libresoc.v:203599$14843
+ attribute \src "libresoc.v:203495.13-203495.30"
+ process $proc$libresoc.v:203495$14635
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:203705.3-203706.28"
- process $proc$libresoc.v:203705$14677
+ attribute \src "libresoc.v:203601.3-203602.28"
+ process $proc$libresoc.v:203601$14469
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
sync posedge \clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:203707.3-203708.25"
- process $proc$libresoc.v:203707$14678
+ attribute \src "libresoc.v:203603.3-203604.25"
+ process $proc$libresoc.v:203603$14470
assign { } { }
assign $0\icp_o_pri[7:0] \$203
sync posedge \clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:203709.3-203710.35"
- process $proc$libresoc.v:203709$14679
+ attribute \src "libresoc.v:203605.3-203606.35"
+ process $proc$libresoc.v:203605$14471
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
sync posedge \clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:203711.3-203712.35"
- process $proc$libresoc.v:203711$14680
+ attribute \src "libresoc.v:203607.3-203608.35"
+ process $proc$libresoc.v:203607$14472
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
sync posedge \clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:203713.3-203714.35"
- process $proc$libresoc.v:203713$14681
+ attribute \src "libresoc.v:203609.3-203610.35"
+ process $proc$libresoc.v:203609$14473
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
sync posedge \clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:203715.3-203716.35"
- process $proc$libresoc.v:203715$14682
+ attribute \src "libresoc.v:203611.3-203612.35"
+ process $proc$libresoc.v:203611$14474
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
sync posedge \clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:203717.3-203718.35"
- process $proc$libresoc.v:203717$14683
+ attribute \src "libresoc.v:203613.3-203614.35"
+ process $proc$libresoc.v:203613$14475
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
sync posedge \clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:203719.3-203720.35"
- process $proc$libresoc.v:203719$14684
+ attribute \src "libresoc.v:203615.3-203616.35"
+ process $proc$libresoc.v:203615$14476
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
sync posedge \clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:203721.3-203722.35"
- process $proc$libresoc.v:203721$14685
+ attribute \src "libresoc.v:203617.3-203618.35"
+ process $proc$libresoc.v:203617$14477
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
sync posedge \clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:203723.3-203724.35"
- process $proc$libresoc.v:203723$14686
+ attribute \src "libresoc.v:203619.3-203620.35"
+ process $proc$libresoc.v:203619$14478
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
sync posedge \clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:203725.3-203726.35"
- process $proc$libresoc.v:203725$14687
+ attribute \src "libresoc.v:203621.3-203622.35"
+ process $proc$libresoc.v:203621$14479
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
sync posedge \clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:203727.3-203728.35"
- process $proc$libresoc.v:203727$14688
+ attribute \src "libresoc.v:203623.3-203624.35"
+ process $proc$libresoc.v:203623$14480
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
sync posedge \clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:203729.3-203730.37"
- process $proc$libresoc.v:203729$14689
+ attribute \src "libresoc.v:203625.3-203626.37"
+ process $proc$libresoc.v:203625$14481
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
sync posedge \clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:203731.3-203732.37"
- process $proc$libresoc.v:203731$14690
+ attribute \src "libresoc.v:203627.3-203628.37"
+ process $proc$libresoc.v:203627$14482
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
sync posedge \clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:203733.3-203734.37"
- process $proc$libresoc.v:203733$14691
+ attribute \src "libresoc.v:203629.3-203630.37"
+ process $proc$libresoc.v:203629$14483
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
sync posedge \clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:203735.3-203736.37"
- process $proc$libresoc.v:203735$14692
+ attribute \src "libresoc.v:203631.3-203632.37"
+ process $proc$libresoc.v:203631$14484
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
sync posedge \clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:203737.3-203738.37"
- process $proc$libresoc.v:203737$14693
+ attribute \src "libresoc.v:203633.3-203634.37"
+ process $proc$libresoc.v:203633$14485
assign { } { }
assign $0\xive14_pri[7:0] \xive14_pri$next
sync posedge \clk
update \xive14_pri $0\xive14_pri[7:0]
end
- attribute \src "libresoc.v:203739.3-203740.37"
- process $proc$libresoc.v:203739$14694
+ attribute \src "libresoc.v:203635.3-203636.37"
+ process $proc$libresoc.v:203635$14486
assign { } { }
assign $0\xive15_pri[7:0] \xive15_pri$next
sync posedge \clk
update \xive15_pri $0\xive15_pri[7:0]
end
- attribute \src "libresoc.v:203741.3-203742.39"
- process $proc$libresoc.v:203741$14695
+ attribute \src "libresoc.v:203637.3-203638.39"
+ process $proc$libresoc.v:203637$14487
assign { } { }
assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
sync posedge \clk
update \ics_wb__ack $0\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:203743.3-203744.43"
- process $proc$libresoc.v:203743$14696
+ attribute \src "libresoc.v:203639.3-203640.43"
+ process $proc$libresoc.v:203639$14488
assign { } { }
assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
sync posedge \clk
update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:203745.3-203746.39"
- process $proc$libresoc.v:203745$14697
+ attribute \src "libresoc.v:203641.3-203642.39"
+ process $proc$libresoc.v:203641$14489
assign { } { }
assign $0\int_level_l[15:0] \int_level_l$next
sync posedge \clk
update \int_level_l $0\int_level_l[15:0]
end
- attribute \src "libresoc.v:203747.3-203832.6"
- process $proc$libresoc.v:203747$14698
+ attribute \src "libresoc.v:203643.3-203728.6"
+ process $proc$libresoc.v:203643$14490
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xive0_pri$next[7:0]$14699 $4\xive0_pri$next[7:0]$14763
- assign $0\xive10_pri$next[7:0]$14700 $4\xive10_pri$next[7:0]$14764
- assign $0\xive11_pri$next[7:0]$14701 $4\xive11_pri$next[7:0]$14765
- assign $0\xive12_pri$next[7:0]$14702 $4\xive12_pri$next[7:0]$14766
- assign $0\xive13_pri$next[7:0]$14703 $4\xive13_pri$next[7:0]$14767
- assign $0\xive14_pri$next[7:0]$14704 $4\xive14_pri$next[7:0]$14768
- assign $0\xive15_pri$next[7:0]$14705 $4\xive15_pri$next[7:0]$14769
- assign $0\xive1_pri$next[7:0]$14706 $4\xive1_pri$next[7:0]$14770
- assign $0\xive2_pri$next[7:0]$14707 $4\xive2_pri$next[7:0]$14771
- assign $0\xive3_pri$next[7:0]$14708 $4\xive3_pri$next[7:0]$14772
- assign $0\xive4_pri$next[7:0]$14709 $4\xive4_pri$next[7:0]$14773
- assign $0\xive5_pri$next[7:0]$14710 $4\xive5_pri$next[7:0]$14774
- assign $0\xive6_pri$next[7:0]$14711 $4\xive6_pri$next[7:0]$14775
- assign $0\xive7_pri$next[7:0]$14712 $4\xive7_pri$next[7:0]$14776
- assign $0\xive8_pri$next[7:0]$14713 $4\xive8_pri$next[7:0]$14777
- assign $0\xive9_pri$next[7:0]$14714 $4\xive9_pri$next[7:0]$14778
- attribute \src "libresoc.v:203748.5-203748.29"
+ assign $0\xive0_pri$next[7:0]$14491 $4\xive0_pri$next[7:0]$14555
+ assign $0\xive10_pri$next[7:0]$14492 $4\xive10_pri$next[7:0]$14556
+ assign $0\xive11_pri$next[7:0]$14493 $4\xive11_pri$next[7:0]$14557
+ assign $0\xive12_pri$next[7:0]$14494 $4\xive12_pri$next[7:0]$14558
+ assign $0\xive13_pri$next[7:0]$14495 $4\xive13_pri$next[7:0]$14559
+ assign $0\xive14_pri$next[7:0]$14496 $4\xive14_pri$next[7:0]$14560
+ assign $0\xive15_pri$next[7:0]$14497 $4\xive15_pri$next[7:0]$14561
+ assign $0\xive1_pri$next[7:0]$14498 $4\xive1_pri$next[7:0]$14562
+ assign $0\xive2_pri$next[7:0]$14499 $4\xive2_pri$next[7:0]$14563
+ assign $0\xive3_pri$next[7:0]$14500 $4\xive3_pri$next[7:0]$14564
+ assign $0\xive4_pri$next[7:0]$14501 $4\xive4_pri$next[7:0]$14565
+ assign $0\xive5_pri$next[7:0]$14502 $4\xive5_pri$next[7:0]$14566
+ assign $0\xive6_pri$next[7:0]$14503 $4\xive6_pri$next[7:0]$14567
+ assign $0\xive7_pri$next[7:0]$14504 $4\xive7_pri$next[7:0]$14568
+ assign $0\xive8_pri$next[7:0]$14505 $4\xive8_pri$next[7:0]$14569
+ assign $0\xive9_pri$next[7:0]$14506 $4\xive9_pri$next[7:0]$14570
+ attribute \src "libresoc.v:203644.5-203644.29"
switch \initial
- attribute \src "libresoc.v:203748.9-203748.17"
+ attribute \src "libresoc.v:203644.9-203644.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xive0_pri$next[7:0]$14715 $2\xive0_pri$next[7:0]$14731
- assign $1\xive10_pri$next[7:0]$14716 $2\xive10_pri$next[7:0]$14732
- assign $1\xive11_pri$next[7:0]$14717 $2\xive11_pri$next[7:0]$14733
- assign $1\xive12_pri$next[7:0]$14718 $2\xive12_pri$next[7:0]$14734
- assign $1\xive13_pri$next[7:0]$14719 $2\xive13_pri$next[7:0]$14735
- assign $1\xive14_pri$next[7:0]$14720 $2\xive14_pri$next[7:0]$14736
- assign $1\xive15_pri$next[7:0]$14721 $2\xive15_pri$next[7:0]$14737
- assign $1\xive1_pri$next[7:0]$14722 $2\xive1_pri$next[7:0]$14738
- assign $1\xive2_pri$next[7:0]$14723 $2\xive2_pri$next[7:0]$14739
- assign $1\xive3_pri$next[7:0]$14724 $2\xive3_pri$next[7:0]$14740
- assign $1\xive4_pri$next[7:0]$14725 $2\xive4_pri$next[7:0]$14741
- assign $1\xive5_pri$next[7:0]$14726 $2\xive5_pri$next[7:0]$14742
- assign $1\xive6_pri$next[7:0]$14727 $2\xive6_pri$next[7:0]$14743
- assign $1\xive7_pri$next[7:0]$14728 $2\xive7_pri$next[7:0]$14744
- assign $1\xive8_pri$next[7:0]$14729 $2\xive8_pri$next[7:0]$14745
- assign $1\xive9_pri$next[7:0]$14730 $2\xive9_pri$next[7:0]$14746
+ assign $1\xive0_pri$next[7:0]$14507 $2\xive0_pri$next[7:0]$14523
+ assign $1\xive10_pri$next[7:0]$14508 $2\xive10_pri$next[7:0]$14524
+ assign $1\xive11_pri$next[7:0]$14509 $2\xive11_pri$next[7:0]$14525
+ assign $1\xive12_pri$next[7:0]$14510 $2\xive12_pri$next[7:0]$14526
+ assign $1\xive13_pri$next[7:0]$14511 $2\xive13_pri$next[7:0]$14527
+ assign $1\xive14_pri$next[7:0]$14512 $2\xive14_pri$next[7:0]$14528
+ assign $1\xive15_pri$next[7:0]$14513 $2\xive15_pri$next[7:0]$14529
+ assign $1\xive1_pri$next[7:0]$14514 $2\xive1_pri$next[7:0]$14530
+ assign $1\xive2_pri$next[7:0]$14515 $2\xive2_pri$next[7:0]$14531
+ assign $1\xive3_pri$next[7:0]$14516 $2\xive3_pri$next[7:0]$14532
+ assign $1\xive4_pri$next[7:0]$14517 $2\xive4_pri$next[7:0]$14533
+ assign $1\xive5_pri$next[7:0]$14518 $2\xive5_pri$next[7:0]$14534
+ assign $1\xive6_pri$next[7:0]$14519 $2\xive6_pri$next[7:0]$14535
+ assign $1\xive7_pri$next[7:0]$14520 $2\xive7_pri$next[7:0]$14536
+ assign $1\xive8_pri$next[7:0]$14521 $2\xive8_pri$next[7:0]$14537
+ assign $1\xive9_pri$next[7:0]$14522 $2\xive9_pri$next[7:0]$14538
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
switch \reg_is_xive
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\xive0_pri$next[7:0]$14731 $3\xive0_pri$next[7:0]$14747
- assign $2\xive10_pri$next[7:0]$14732 $3\xive10_pri$next[7:0]$14748
- assign $2\xive11_pri$next[7:0]$14733 $3\xive11_pri$next[7:0]$14749
- assign $2\xive12_pri$next[7:0]$14734 $3\xive12_pri$next[7:0]$14750
- assign $2\xive13_pri$next[7:0]$14735 $3\xive13_pri$next[7:0]$14751
- assign $2\xive14_pri$next[7:0]$14736 $3\xive14_pri$next[7:0]$14752
- assign $2\xive15_pri$next[7:0]$14737 $3\xive15_pri$next[7:0]$14753
- assign $2\xive1_pri$next[7:0]$14738 $3\xive1_pri$next[7:0]$14754
- assign $2\xive2_pri$next[7:0]$14739 $3\xive2_pri$next[7:0]$14755
- assign $2\xive3_pri$next[7:0]$14740 $3\xive3_pri$next[7:0]$14756
- assign $2\xive4_pri$next[7:0]$14741 $3\xive4_pri$next[7:0]$14757
- assign $2\xive5_pri$next[7:0]$14742 $3\xive5_pri$next[7:0]$14758
- assign $2\xive6_pri$next[7:0]$14743 $3\xive6_pri$next[7:0]$14759
- assign $2\xive7_pri$next[7:0]$14744 $3\xive7_pri$next[7:0]$14760
- assign $2\xive8_pri$next[7:0]$14745 $3\xive8_pri$next[7:0]$14761
- assign $2\xive9_pri$next[7:0]$14746 $3\xive9_pri$next[7:0]$14762
+ assign $2\xive0_pri$next[7:0]$14523 $3\xive0_pri$next[7:0]$14539
+ assign $2\xive10_pri$next[7:0]$14524 $3\xive10_pri$next[7:0]$14540
+ assign $2\xive11_pri$next[7:0]$14525 $3\xive11_pri$next[7:0]$14541
+ assign $2\xive12_pri$next[7:0]$14526 $3\xive12_pri$next[7:0]$14542
+ assign $2\xive13_pri$next[7:0]$14527 $3\xive13_pri$next[7:0]$14543
+ assign $2\xive14_pri$next[7:0]$14528 $3\xive14_pri$next[7:0]$14544
+ assign $2\xive15_pri$next[7:0]$14529 $3\xive15_pri$next[7:0]$14545
+ assign $2\xive1_pri$next[7:0]$14530 $3\xive1_pri$next[7:0]$14546
+ assign $2\xive2_pri$next[7:0]$14531 $3\xive2_pri$next[7:0]$14547
+ assign $2\xive3_pri$next[7:0]$14532 $3\xive3_pri$next[7:0]$14548
+ assign $2\xive4_pri$next[7:0]$14533 $3\xive4_pri$next[7:0]$14549
+ assign $2\xive5_pri$next[7:0]$14534 $3\xive5_pri$next[7:0]$14550
+ assign $2\xive6_pri$next[7:0]$14535 $3\xive6_pri$next[7:0]$14551
+ assign $2\xive7_pri$next[7:0]$14536 $3\xive7_pri$next[7:0]$14552
+ assign $2\xive8_pri$next[7:0]$14537 $3\xive8_pri$next[7:0]$14553
+ assign $2\xive9_pri$next[7:0]$14538 $3\xive9_pri$next[7:0]$14554
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
switch \reg_idx
attribute \src "libresoc.v:0.0-0.0"
case 4'0000
assign { } { }
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive0_pri$next[7:0]$14747 \be_in [7:0]
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14539 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
assign { } { }
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive1_pri$next[7:0]$14754 \be_in [7:0]
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive1_pri$next[7:0]$14546 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
assign { } { }
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive2_pri$next[7:0]$14755 \be_in [7:0]
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive2_pri$next[7:0]$14547 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0011
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
assign { } { }
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive3_pri$next[7:0]$14756 \be_in [7:0]
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive3_pri$next[7:0]$14548 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0100
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
assign { } { }
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive4_pri$next[7:0]$14757 \be_in [7:0]
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive4_pri$next[7:0]$14549 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
assign { } { }
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive5_pri$next[7:0]$14758 \be_in [7:0]
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive5_pri$next[7:0]$14550 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0110
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
assign { } { }
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive6_pri$next[7:0]$14759 \be_in [7:0]
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive6_pri$next[7:0]$14551 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0111
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
assign { } { }
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive7_pri$next[7:0]$14760 \be_in [7:0]
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive7_pri$next[7:0]$14552 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive8_pri$next[7:0]$14761 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive8_pri$next[7:0]$14553 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$14762 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$14554 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1010
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
assign { } { }
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive10_pri$next[7:0]$14748 \be_in [7:0]
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive10_pri$next[7:0]$14540 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1011
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
assign { } { }
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive11_pri$next[7:0]$14749 \be_in [7:0]
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive11_pri$next[7:0]$14541 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1100
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
assign { } { }
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive12_pri$next[7:0]$14750 \be_in [7:0]
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive12_pri$next[7:0]$14542 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1101
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
assign { } { }
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive13_pri$next[7:0]$14751 \be_in [7:0]
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive13_pri$next[7:0]$14543 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1110
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
assign { } { }
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive14_pri$next[7:0]$14752 \be_in [7:0]
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive14_pri$next[7:0]$14544 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'----
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
assign { } { }
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
- assign $3\xive15_pri$next[7:0]$14753 \be_in [7:0]
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
+ assign $3\xive15_pri$next[7:0]$14545 \be_in [7:0]
case
- assign $3\xive0_pri$next[7:0]$14747 \xive0_pri
- assign $3\xive10_pri$next[7:0]$14748 \xive10_pri
- assign $3\xive11_pri$next[7:0]$14749 \xive11_pri
- assign $3\xive12_pri$next[7:0]$14750 \xive12_pri
- assign $3\xive13_pri$next[7:0]$14751 \xive13_pri
- assign $3\xive14_pri$next[7:0]$14752 \xive14_pri
- assign $3\xive15_pri$next[7:0]$14753 \xive15_pri
- assign $3\xive1_pri$next[7:0]$14754 \xive1_pri
- assign $3\xive2_pri$next[7:0]$14755 \xive2_pri
- assign $3\xive3_pri$next[7:0]$14756 \xive3_pri
- assign $3\xive4_pri$next[7:0]$14757 \xive4_pri
- assign $3\xive5_pri$next[7:0]$14758 \xive5_pri
- assign $3\xive6_pri$next[7:0]$14759 \xive6_pri
- assign $3\xive7_pri$next[7:0]$14760 \xive7_pri
- assign $3\xive8_pri$next[7:0]$14761 \xive8_pri
- assign $3\xive9_pri$next[7:0]$14762 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$14539 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$14540 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$14541 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$14542 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$14543 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$14544 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$14545 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$14546 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$14547 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$14548 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$14549 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$14550 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$14551 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$14552 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$14553 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$14554 \xive9_pri
end
case
- assign $2\xive0_pri$next[7:0]$14731 \xive0_pri
- assign $2\xive10_pri$next[7:0]$14732 \xive10_pri
- assign $2\xive11_pri$next[7:0]$14733 \xive11_pri
- assign $2\xive12_pri$next[7:0]$14734 \xive12_pri
- assign $2\xive13_pri$next[7:0]$14735 \xive13_pri
- assign $2\xive14_pri$next[7:0]$14736 \xive14_pri
- assign $2\xive15_pri$next[7:0]$14737 \xive15_pri
- assign $2\xive1_pri$next[7:0]$14738 \xive1_pri
- assign $2\xive2_pri$next[7:0]$14739 \xive2_pri
- assign $2\xive3_pri$next[7:0]$14740 \xive3_pri
- assign $2\xive4_pri$next[7:0]$14741 \xive4_pri
- assign $2\xive5_pri$next[7:0]$14742 \xive5_pri
- assign $2\xive6_pri$next[7:0]$14743 \xive6_pri
- assign $2\xive7_pri$next[7:0]$14744 \xive7_pri
- assign $2\xive8_pri$next[7:0]$14745 \xive8_pri
- assign $2\xive9_pri$next[7:0]$14746 \xive9_pri
+ assign $2\xive0_pri$next[7:0]$14523 \xive0_pri
+ assign $2\xive10_pri$next[7:0]$14524 \xive10_pri
+ assign $2\xive11_pri$next[7:0]$14525 \xive11_pri
+ assign $2\xive12_pri$next[7:0]$14526 \xive12_pri
+ assign $2\xive13_pri$next[7:0]$14527 \xive13_pri
+ assign $2\xive14_pri$next[7:0]$14528 \xive14_pri
+ assign $2\xive15_pri$next[7:0]$14529 \xive15_pri
+ assign $2\xive1_pri$next[7:0]$14530 \xive1_pri
+ assign $2\xive2_pri$next[7:0]$14531 \xive2_pri
+ assign $2\xive3_pri$next[7:0]$14532 \xive3_pri
+ assign $2\xive4_pri$next[7:0]$14533 \xive4_pri
+ assign $2\xive5_pri$next[7:0]$14534 \xive5_pri
+ assign $2\xive6_pri$next[7:0]$14535 \xive6_pri
+ assign $2\xive7_pri$next[7:0]$14536 \xive7_pri
+ assign $2\xive8_pri$next[7:0]$14537 \xive8_pri
+ assign $2\xive9_pri$next[7:0]$14538 \xive9_pri
end
case
- assign $1\xive0_pri$next[7:0]$14715 \xive0_pri
- assign $1\xive10_pri$next[7:0]$14716 \xive10_pri
- assign $1\xive11_pri$next[7:0]$14717 \xive11_pri
- assign $1\xive12_pri$next[7:0]$14718 \xive12_pri
- assign $1\xive13_pri$next[7:0]$14719 \xive13_pri
- assign $1\xive14_pri$next[7:0]$14720 \xive14_pri
- assign $1\xive15_pri$next[7:0]$14721 \xive15_pri
- assign $1\xive1_pri$next[7:0]$14722 \xive1_pri
- assign $1\xive2_pri$next[7:0]$14723 \xive2_pri
- assign $1\xive3_pri$next[7:0]$14724 \xive3_pri
- assign $1\xive4_pri$next[7:0]$14725 \xive4_pri
- assign $1\xive5_pri$next[7:0]$14726 \xive5_pri
- assign $1\xive6_pri$next[7:0]$14727 \xive6_pri
- assign $1\xive7_pri$next[7:0]$14728 \xive7_pri
- assign $1\xive8_pri$next[7:0]$14729 \xive8_pri
- assign $1\xive9_pri$next[7:0]$14730 \xive9_pri
+ assign $1\xive0_pri$next[7:0]$14507 \xive0_pri
+ assign $1\xive10_pri$next[7:0]$14508 \xive10_pri
+ assign $1\xive11_pri$next[7:0]$14509 \xive11_pri
+ assign $1\xive12_pri$next[7:0]$14510 \xive12_pri
+ assign $1\xive13_pri$next[7:0]$14511 \xive13_pri
+ assign $1\xive14_pri$next[7:0]$14512 \xive14_pri
+ assign $1\xive15_pri$next[7:0]$14513 \xive15_pri
+ assign $1\xive1_pri$next[7:0]$14514 \xive1_pri
+ assign $1\xive2_pri$next[7:0]$14515 \xive2_pri
+ assign $1\xive3_pri$next[7:0]$14516 \xive3_pri
+ assign $1\xive4_pri$next[7:0]$14517 \xive4_pri
+ assign $1\xive5_pri$next[7:0]$14518 \xive5_pri
+ assign $1\xive6_pri$next[7:0]$14519 \xive6_pri
+ assign $1\xive7_pri$next[7:0]$14520 \xive7_pri
+ assign $1\xive8_pri$next[7:0]$14521 \xive8_pri
+ assign $1\xive9_pri$next[7:0]$14522 \xive9_pri
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\xive0_pri$next[7:0]$14763 8'11111111
- assign $4\xive1_pri$next[7:0]$14770 8'11111111
- assign $4\xive2_pri$next[7:0]$14771 8'11111111
- assign $4\xive3_pri$next[7:0]$14772 8'11111111
- assign $4\xive4_pri$next[7:0]$14773 8'11111111
- assign $4\xive5_pri$next[7:0]$14774 8'11111111
- assign $4\xive6_pri$next[7:0]$14775 8'11111111
- assign $4\xive7_pri$next[7:0]$14776 8'11111111
- assign $4\xive8_pri$next[7:0]$14777 8'11111111
- assign $4\xive9_pri$next[7:0]$14778 8'11111111
- assign $4\xive10_pri$next[7:0]$14764 8'11111111
- assign $4\xive11_pri$next[7:0]$14765 8'11111111
- assign $4\xive12_pri$next[7:0]$14766 8'11111111
- assign $4\xive13_pri$next[7:0]$14767 8'11111111
- assign $4\xive14_pri$next[7:0]$14768 8'11111111
- assign $4\xive15_pri$next[7:0]$14769 8'11111111
+ assign $4\xive0_pri$next[7:0]$14555 8'11111111
+ assign $4\xive1_pri$next[7:0]$14562 8'11111111
+ assign $4\xive2_pri$next[7:0]$14563 8'11111111
+ assign $4\xive3_pri$next[7:0]$14564 8'11111111
+ assign $4\xive4_pri$next[7:0]$14565 8'11111111
+ assign $4\xive5_pri$next[7:0]$14566 8'11111111
+ assign $4\xive6_pri$next[7:0]$14567 8'11111111
+ assign $4\xive7_pri$next[7:0]$14568 8'11111111
+ assign $4\xive8_pri$next[7:0]$14569 8'11111111
+ assign $4\xive9_pri$next[7:0]$14570 8'11111111
+ assign $4\xive10_pri$next[7:0]$14556 8'11111111
+ assign $4\xive11_pri$next[7:0]$14557 8'11111111
+ assign $4\xive12_pri$next[7:0]$14558 8'11111111
+ assign $4\xive13_pri$next[7:0]$14559 8'11111111
+ assign $4\xive14_pri$next[7:0]$14560 8'11111111
+ assign $4\xive15_pri$next[7:0]$14561 8'11111111
case
- assign $4\xive0_pri$next[7:0]$14763 $1\xive0_pri$next[7:0]$14715
- assign $4\xive10_pri$next[7:0]$14764 $1\xive10_pri$next[7:0]$14716
- assign $4\xive11_pri$next[7:0]$14765 $1\xive11_pri$next[7:0]$14717
- assign $4\xive12_pri$next[7:0]$14766 $1\xive12_pri$next[7:0]$14718
- assign $4\xive13_pri$next[7:0]$14767 $1\xive13_pri$next[7:0]$14719
- assign $4\xive14_pri$next[7:0]$14768 $1\xive14_pri$next[7:0]$14720
- assign $4\xive15_pri$next[7:0]$14769 $1\xive15_pri$next[7:0]$14721
- assign $4\xive1_pri$next[7:0]$14770 $1\xive1_pri$next[7:0]$14722
- assign $4\xive2_pri$next[7:0]$14771 $1\xive2_pri$next[7:0]$14723
- assign $4\xive3_pri$next[7:0]$14772 $1\xive3_pri$next[7:0]$14724
- assign $4\xive4_pri$next[7:0]$14773 $1\xive4_pri$next[7:0]$14725
- assign $4\xive5_pri$next[7:0]$14774 $1\xive5_pri$next[7:0]$14726
- assign $4\xive6_pri$next[7:0]$14775 $1\xive6_pri$next[7:0]$14727
- assign $4\xive7_pri$next[7:0]$14776 $1\xive7_pri$next[7:0]$14728
- assign $4\xive8_pri$next[7:0]$14777 $1\xive8_pri$next[7:0]$14729
- assign $4\xive9_pri$next[7:0]$14778 $1\xive9_pri$next[7:0]$14730
+ assign $4\xive0_pri$next[7:0]$14555 $1\xive0_pri$next[7:0]$14507
+ assign $4\xive10_pri$next[7:0]$14556 $1\xive10_pri$next[7:0]$14508
+ assign $4\xive11_pri$next[7:0]$14557 $1\xive11_pri$next[7:0]$14509
+ assign $4\xive12_pri$next[7:0]$14558 $1\xive12_pri$next[7:0]$14510
+ assign $4\xive13_pri$next[7:0]$14559 $1\xive13_pri$next[7:0]$14511
+ assign $4\xive14_pri$next[7:0]$14560 $1\xive14_pri$next[7:0]$14512
+ assign $4\xive15_pri$next[7:0]$14561 $1\xive15_pri$next[7:0]$14513
+ assign $4\xive1_pri$next[7:0]$14562 $1\xive1_pri$next[7:0]$14514
+ assign $4\xive2_pri$next[7:0]$14563 $1\xive2_pri$next[7:0]$14515
+ assign $4\xive3_pri$next[7:0]$14564 $1\xive3_pri$next[7:0]$14516
+ assign $4\xive4_pri$next[7:0]$14565 $1\xive4_pri$next[7:0]$14517
+ assign $4\xive5_pri$next[7:0]$14566 $1\xive5_pri$next[7:0]$14518
+ assign $4\xive6_pri$next[7:0]$14567 $1\xive6_pri$next[7:0]$14519
+ assign $4\xive7_pri$next[7:0]$14568 $1\xive7_pri$next[7:0]$14520
+ assign $4\xive8_pri$next[7:0]$14569 $1\xive8_pri$next[7:0]$14521
+ assign $4\xive9_pri$next[7:0]$14570 $1\xive9_pri$next[7:0]$14522
end
sync always
- update \xive0_pri$next $0\xive0_pri$next[7:0]$14699
- update \xive10_pri$next $0\xive10_pri$next[7:0]$14700
- update \xive11_pri$next $0\xive11_pri$next[7:0]$14701
- update \xive12_pri$next $0\xive12_pri$next[7:0]$14702
- update \xive13_pri$next $0\xive13_pri$next[7:0]$14703
- update \xive14_pri$next $0\xive14_pri$next[7:0]$14704
- update \xive15_pri$next $0\xive15_pri$next[7:0]$14705
- update \xive1_pri$next $0\xive1_pri$next[7:0]$14706
- update \xive2_pri$next $0\xive2_pri$next[7:0]$14707
- update \xive3_pri$next $0\xive3_pri$next[7:0]$14708
- update \xive4_pri$next $0\xive4_pri$next[7:0]$14709
- update \xive5_pri$next $0\xive5_pri$next[7:0]$14710
- update \xive6_pri$next $0\xive6_pri$next[7:0]$14711
- update \xive7_pri$next $0\xive7_pri$next[7:0]$14712
- update \xive8_pri$next $0\xive8_pri$next[7:0]$14713
- update \xive9_pri$next $0\xive9_pri$next[7:0]$14714
+ update \xive0_pri$next $0\xive0_pri$next[7:0]$14491
+ update \xive10_pri$next $0\xive10_pri$next[7:0]$14492
+ update \xive11_pri$next $0\xive11_pri$next[7:0]$14493
+ update \xive12_pri$next $0\xive12_pri$next[7:0]$14494
+ update \xive13_pri$next $0\xive13_pri$next[7:0]$14495
+ update \xive14_pri$next $0\xive14_pri$next[7:0]$14496
+ update \xive15_pri$next $0\xive15_pri$next[7:0]$14497
+ update \xive1_pri$next $0\xive1_pri$next[7:0]$14498
+ update \xive2_pri$next $0\xive2_pri$next[7:0]$14499
+ update \xive3_pri$next $0\xive3_pri$next[7:0]$14500
+ update \xive4_pri$next $0\xive4_pri$next[7:0]$14501
+ update \xive5_pri$next $0\xive5_pri$next[7:0]$14502
+ update \xive6_pri$next $0\xive6_pri$next[7:0]$14503
+ update \xive7_pri$next $0\xive7_pri$next[7:0]$14504
+ update \xive8_pri$next $0\xive8_pri$next[7:0]$14505
+ update \xive9_pri$next $0\xive9_pri$next[7:0]$14506
end
- attribute \src "libresoc.v:203833.3-203842.6"
- process $proc$libresoc.v:203833$14779
+ attribute \src "libresoc.v:203729.3-203738.6"
+ process $proc$libresoc.v:203729$14571
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:203834.5-203834.29"
+ attribute \src "libresoc.v:203730.5-203730.29"
switch \initial
- attribute \src "libresoc.v:203834.9-203834.17"
+ attribute \src "libresoc.v:203730.9-203730.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:203843.3-203852.6"
- process $proc$libresoc.v:203843$14780
+ attribute \src "libresoc.v:203739.3-203748.6"
+ process $proc$libresoc.v:203739$14572
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:203844.5-203844.29"
+ attribute \src "libresoc.v:203740.5-203740.29"
switch \initial
- attribute \src "libresoc.v:203844.9-203844.17"
+ attribute \src "libresoc.v:203740.9-203740.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:203853.3-203862.6"
- process $proc$libresoc.v:203853$14781
+ attribute \src "libresoc.v:203749.3-203758.6"
+ process $proc$libresoc.v:203749$14573
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:203854.5-203854.29"
+ attribute \src "libresoc.v:203750.5-203750.29"
switch \initial
- attribute \src "libresoc.v:203854.9-203854.17"
+ attribute \src "libresoc.v:203750.9-203750.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:203863.3-203872.6"
- process $proc$libresoc.v:203863$14782
+ attribute \src "libresoc.v:203759.3-203768.6"
+ process $proc$libresoc.v:203759$14574
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:203864.5-203864.29"
+ attribute \src "libresoc.v:203760.5-203760.29"
switch \initial
- attribute \src "libresoc.v:203864.9-203864.17"
+ attribute \src "libresoc.v:203760.9-203760.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:203873.3-203882.6"
- process $proc$libresoc.v:203873$14783
+ attribute \src "libresoc.v:203769.3-203778.6"
+ process $proc$libresoc.v:203769$14575
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:203874.5-203874.29"
+ attribute \src "libresoc.v:203770.5-203770.29"
switch \initial
- attribute \src "libresoc.v:203874.9-203874.17"
+ attribute \src "libresoc.v:203770.9-203770.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:203883.3-203892.6"
- process $proc$libresoc.v:203883$14784
+ attribute \src "libresoc.v:203779.3-203788.6"
+ process $proc$libresoc.v:203779$14576
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:203884.5-203884.29"
+ attribute \src "libresoc.v:203780.5-203780.29"
switch \initial
- attribute \src "libresoc.v:203884.9-203884.17"
+ attribute \src "libresoc.v:203780.9-203780.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:203893.3-203902.6"
- process $proc$libresoc.v:203893$14785
+ attribute \src "libresoc.v:203789.3-203798.6"
+ process $proc$libresoc.v:203789$14577
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:203894.5-203894.29"
+ attribute \src "libresoc.v:203790.5-203790.29"
switch \initial
- attribute \src "libresoc.v:203894.9-203894.17"
+ attribute \src "libresoc.v:203790.9-203790.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:203903.3-203912.6"
- process $proc$libresoc.v:203903$14786
+ attribute \src "libresoc.v:203799.3-203808.6"
+ process $proc$libresoc.v:203799$14578
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:203904.5-203904.29"
+ attribute \src "libresoc.v:203800.5-203800.29"
switch \initial
- attribute \src "libresoc.v:203904.9-203904.17"
+ attribute \src "libresoc.v:203800.9-203800.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:203913.3-203922.6"
- process $proc$libresoc.v:203913$14787
+ attribute \src "libresoc.v:203809.3-203818.6"
+ process $proc$libresoc.v:203809$14579
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:203914.5-203914.29"
+ attribute \src "libresoc.v:203810.5-203810.29"
switch \initial
- attribute \src "libresoc.v:203914.9-203914.17"
+ attribute \src "libresoc.v:203810.9-203810.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:203923.3-203931.6"
- process $proc$libresoc.v:203923$14788
+ attribute \src "libresoc.v:203819.3-203827.6"
+ process $proc$libresoc.v:203819$14580
assign { } { }
assign { } { }
- assign $0\int_level_l$next[15:0]$14789 $1\int_level_l$next[15:0]$14790
- attribute \src "libresoc.v:203924.5-203924.29"
+ assign $0\int_level_l$next[15:0]$14581 $1\int_level_l$next[15:0]$14582
+ attribute \src "libresoc.v:203820.5-203820.29"
switch \initial
- attribute \src "libresoc.v:203924.9-203924.17"
+ attribute \src "libresoc.v:203820.9-203820.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\int_level_l$next[15:0]$14790 16'0000000000000000
+ assign $1\int_level_l$next[15:0]$14582 16'0000000000000000
case
- assign $1\int_level_l$next[15:0]$14790 \int_level_i
+ assign $1\int_level_l$next[15:0]$14582 \int_level_i
end
sync always
- update \int_level_l$next $0\int_level_l$next[15:0]$14789
+ update \int_level_l$next $0\int_level_l$next[15:0]$14581
end
- attribute \src "libresoc.v:203932.3-203941.6"
- process $proc$libresoc.v:203932$14791
+ attribute \src "libresoc.v:203828.3-203837.6"
+ process $proc$libresoc.v:203828$14583
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:203933.5-203933.29"
+ attribute \src "libresoc.v:203829.5-203829.29"
switch \initial
- attribute \src "libresoc.v:203933.9-203933.17"
+ attribute \src "libresoc.v:203829.9-203829.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:203942.3-203951.6"
- process $proc$libresoc.v:203942$14792
+ attribute \src "libresoc.v:203838.3-203847.6"
+ process $proc$libresoc.v:203838$14584
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:203943.5-203943.29"
+ attribute \src "libresoc.v:203839.5-203839.29"
switch \initial
- attribute \src "libresoc.v:203943.9-203943.17"
+ attribute \src "libresoc.v:203839.9-203839.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:203952.3-203961.6"
- process $proc$libresoc.v:203952$14793
+ attribute \src "libresoc.v:203848.3-203857.6"
+ process $proc$libresoc.v:203848$14585
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:203953.5-203953.29"
+ attribute \src "libresoc.v:203849.5-203849.29"
switch \initial
- attribute \src "libresoc.v:203953.9-203953.17"
+ attribute \src "libresoc.v:203849.9-203849.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:203962.3-203971.6"
- process $proc$libresoc.v:203962$14794
+ attribute \src "libresoc.v:203858.3-203867.6"
+ process $proc$libresoc.v:203858$14586
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:203963.5-203963.29"
+ attribute \src "libresoc.v:203859.5-203859.29"
switch \initial
- attribute \src "libresoc.v:203963.9-203963.17"
+ attribute \src "libresoc.v:203859.9-203859.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:203972.3-203981.6"
- process $proc$libresoc.v:203972$14795
+ attribute \src "libresoc.v:203868.3-203877.6"
+ process $proc$libresoc.v:203868$14587
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:203973.5-203973.29"
+ attribute \src "libresoc.v:203869.5-203869.29"
switch \initial
- attribute \src "libresoc.v:203973.9-203973.17"
+ attribute \src "libresoc.v:203869.9-203869.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:203982.3-203991.6"
- process $proc$libresoc.v:203982$14796
+ attribute \src "libresoc.v:203878.3-203887.6"
+ process $proc$libresoc.v:203878$14588
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:203983.5-203983.29"
+ attribute \src "libresoc.v:203879.5-203879.29"
switch \initial
- attribute \src "libresoc.v:203983.9-203983.17"
+ attribute \src "libresoc.v:203879.9-203879.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:203992.3-204001.6"
- process $proc$libresoc.v:203992$14797
+ attribute \src "libresoc.v:203888.3-203897.6"
+ process $proc$libresoc.v:203888$14589
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:203993.5-203993.29"
+ attribute \src "libresoc.v:203889.5-203889.29"
switch \initial
- attribute \src "libresoc.v:203993.9-203993.17"
+ attribute \src "libresoc.v:203889.9-203889.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:204002.3-204011.6"
- process $proc$libresoc.v:204002$14798
+ attribute \src "libresoc.v:203898.3-203907.6"
+ process $proc$libresoc.v:203898$14590
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:204003.5-204003.29"
+ attribute \src "libresoc.v:203899.5-203899.29"
switch \initial
- attribute \src "libresoc.v:204003.9-204003.17"
+ attribute \src "libresoc.v:203899.9-203899.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:204012.3-204021.6"
- process $proc$libresoc.v:204012$14799
+ attribute \src "libresoc.v:203908.3-203917.6"
+ process $proc$libresoc.v:203908$14591
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:204013.5-204013.29"
+ attribute \src "libresoc.v:203909.5-203909.29"
switch \initial
- attribute \src "libresoc.v:204013.9-204013.17"
+ attribute \src "libresoc.v:203909.9-203909.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:204022.3-204031.6"
- process $proc$libresoc.v:204022$14800
+ attribute \src "libresoc.v:203918.3-203927.6"
+ process $proc$libresoc.v:203918$14592
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:204023.5-204023.29"
+ attribute \src "libresoc.v:203919.5-203919.29"
switch \initial
- attribute \src "libresoc.v:204023.9-204023.17"
+ attribute \src "libresoc.v:203919.9-203919.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:204032.3-204041.6"
- process $proc$libresoc.v:204032$14801
+ attribute \src "libresoc.v:203928.3-203937.6"
+ process $proc$libresoc.v:203928$14593
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:204033.5-204033.29"
+ attribute \src "libresoc.v:203929.5-203929.29"
switch \initial
- attribute \src "libresoc.v:204033.9-204033.17"
+ attribute \src "libresoc.v:203929.9-203929.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:204042.3-204051.6"
- process $proc$libresoc.v:204042$14802
+ attribute \src "libresoc.v:203938.3-203947.6"
+ process $proc$libresoc.v:203938$14594
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:204043.5-204043.29"
+ attribute \src "libresoc.v:203939.5-203939.29"
switch \initial
- attribute \src "libresoc.v:204043.9-204043.17"
+ attribute \src "libresoc.v:203939.9-203939.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:204052.3-204061.6"
- process $proc$libresoc.v:204052$14803
+ attribute \src "libresoc.v:203948.3-203957.6"
+ process $proc$libresoc.v:203948$14595
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:204053.5-204053.29"
+ attribute \src "libresoc.v:203949.5-203949.29"
switch \initial
- attribute \src "libresoc.v:204053.9-204053.17"
+ attribute \src "libresoc.v:203949.9-203949.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:204062.3-204071.6"
- process $proc$libresoc.v:204062$14804
+ attribute \src "libresoc.v:203958.3-203967.6"
+ process $proc$libresoc.v:203958$14596
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:204063.5-204063.29"
+ attribute \src "libresoc.v:203959.5-203959.29"
switch \initial
- attribute \src "libresoc.v:204063.9-204063.17"
+ attribute \src "libresoc.v:203959.9-203959.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:204072.3-204081.6"
- process $proc$libresoc.v:204072$14805
+ attribute \src "libresoc.v:203968.3-203977.6"
+ process $proc$libresoc.v:203968$14597
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:204073.5-204073.29"
+ attribute \src "libresoc.v:203969.5-203969.29"
switch \initial
- attribute \src "libresoc.v:204073.9-204073.17"
+ attribute \src "libresoc.v:203969.9-203969.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:204082.3-204091.6"
- process $proc$libresoc.v:204082$14806
+ attribute \src "libresoc.v:203978.3-203987.6"
+ process $proc$libresoc.v:203978$14598
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:204083.5-204083.29"
+ attribute \src "libresoc.v:203979.5-203979.29"
switch \initial
- attribute \src "libresoc.v:204083.9-204083.17"
+ attribute \src "libresoc.v:203979.9-203979.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:204092.3-204101.6"
- process $proc$libresoc.v:204092$14807
+ attribute \src "libresoc.v:203988.3-203997.6"
+ process $proc$libresoc.v:203988$14599
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:204093.5-204093.29"
+ attribute \src "libresoc.v:203989.5-203989.29"
switch \initial
- attribute \src "libresoc.v:204093.9-204093.17"
+ attribute \src "libresoc.v:203989.9-203989.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:204102.3-204111.6"
- process $proc$libresoc.v:204102$14808
+ attribute \src "libresoc.v:203998.3-204007.6"
+ process $proc$libresoc.v:203998$14600
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:204103.5-204103.29"
+ attribute \src "libresoc.v:203999.5-203999.29"
switch \initial
- attribute \src "libresoc.v:204103.9-204103.17"
+ attribute \src "libresoc.v:203999.9-203999.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:204112.3-204121.6"
- process $proc$libresoc.v:204112$14809
+ attribute \src "libresoc.v:204008.3-204017.6"
+ process $proc$libresoc.v:204008$14601
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:204113.5-204113.29"
+ attribute \src "libresoc.v:204009.5-204009.29"
switch \initial
- attribute \src "libresoc.v:204113.9-204113.17"
+ attribute \src "libresoc.v:204009.9-204009.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:204122.3-204131.6"
- process $proc$libresoc.v:204122$14810
+ attribute \src "libresoc.v:204018.3-204027.6"
+ process $proc$libresoc.v:204018$14602
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:204123.5-204123.29"
+ attribute \src "libresoc.v:204019.5-204019.29"
switch \initial
- attribute \src "libresoc.v:204123.9-204123.17"
+ attribute \src "libresoc.v:204019.9-204019.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:204132.3-204181.6"
- process $proc$libresoc.v:204132$14811
+ attribute \src "libresoc.v:204028.3-204077.6"
+ process $proc$libresoc.v:204028$14603
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:204133.5-204133.29"
+ attribute \src "libresoc.v:204029.5-204029.29"
switch \initial
- attribute \src "libresoc.v:204133.9-204133.17"
+ attribute \src "libresoc.v:204029.9-204029.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:204182.3-204191.6"
- process $proc$libresoc.v:204182$14812
+ attribute \src "libresoc.v:204078.3-204087.6"
+ process $proc$libresoc.v:204078$14604
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:204183.5-204183.29"
+ attribute \src "libresoc.v:204079.5-204079.29"
switch \initial
- attribute \src "libresoc.v:204183.9-204183.17"
+ attribute \src "libresoc.v:204079.9-204079.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:204192.3-204201.6"
- process $proc$libresoc.v:204192$14813
+ attribute \src "libresoc.v:204088.3-204097.6"
+ process $proc$libresoc.v:204088$14605
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:204193.5-204193.29"
+ attribute \src "libresoc.v:204089.5-204089.29"
switch \initial
- attribute \src "libresoc.v:204193.9-204193.17"
+ attribute \src "libresoc.v:204089.9-204089.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:204202.3-204211.6"
- process $proc$libresoc.v:204202$14814
+ attribute \src "libresoc.v:204098.3-204107.6"
+ process $proc$libresoc.v:204098$14606
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:204203.5-204203.29"
+ attribute \src "libresoc.v:204099.5-204099.29"
switch \initial
- attribute \src "libresoc.v:204203.9-204203.17"
+ attribute \src "libresoc.v:204099.9-204099.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:204212.3-204221.6"
- process $proc$libresoc.v:204212$14815
+ attribute \src "libresoc.v:204108.3-204117.6"
+ process $proc$libresoc.v:204108$14607
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:204213.5-204213.29"
+ attribute \src "libresoc.v:204109.5-204109.29"
switch \initial
- attribute \src "libresoc.v:204213.9-204213.17"
+ attribute \src "libresoc.v:204109.9-204109.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:204222.3-204230.6"
- process $proc$libresoc.v:204222$14816
+ attribute \src "libresoc.v:204118.3-204126.6"
+ process $proc$libresoc.v:204118$14608
assign { } { }
assign { } { }
- assign $0\ics_wb__dat_r$next[31:0]$14817 $1\ics_wb__dat_r$next[31:0]$14818
- attribute \src "libresoc.v:204223.5-204223.29"
+ assign $0\ics_wb__dat_r$next[31:0]$14609 $1\ics_wb__dat_r$next[31:0]$14610
+ attribute \src "libresoc.v:204119.5-204119.29"
switch \initial
- attribute \src "libresoc.v:204223.9-204223.17"
+ attribute \src "libresoc.v:204119.9-204119.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__dat_r$next[31:0]$14818 0
+ assign $1\ics_wb__dat_r$next[31:0]$14610 0
case
- assign $1\ics_wb__dat_r$next[31:0]$14818 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $1\ics_wb__dat_r$next[31:0]$14610 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
end
sync always
- update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14817
+ update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14609
end
- attribute \src "libresoc.v:204231.3-204239.6"
- process $proc$libresoc.v:204231$14819
+ attribute \src "libresoc.v:204127.3-204135.6"
+ process $proc$libresoc.v:204127$14611
assign { } { }
assign { } { }
- assign $0\ics_wb__ack$next[0:0]$14820 $1\ics_wb__ack$next[0:0]$14821
- attribute \src "libresoc.v:204232.5-204232.29"
+ assign $0\ics_wb__ack$next[0:0]$14612 $1\ics_wb__ack$next[0:0]$14613
+ attribute \src "libresoc.v:204128.5-204128.29"
switch \initial
- attribute \src "libresoc.v:204232.9-204232.17"
+ attribute \src "libresoc.v:204128.9-204128.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__ack$next[0:0]$14821 1'0
- case
- assign $1\ics_wb__ack$next[0:0]$14821 \wb_valid
- end
- sync always
- update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14820
- end
- connect \$7 $ternary$libresoc.v:203602$14574_Y
- connect \$99 $lt$libresoc.v:203603$14575_Y
- connect \$101 $and$libresoc.v:203604$14576_Y
- connect \$103 $lt$libresoc.v:203605$14577_Y
- connect \$105 $and$libresoc.v:203606$14578_Y
- connect \$107 $lt$libresoc.v:203607$14579_Y
- connect \$109 $and$libresoc.v:203608$14580_Y
- connect \$111 $lt$libresoc.v:203609$14581_Y
- connect \$113 $and$libresoc.v:203610$14582_Y
- connect \$115 $lt$libresoc.v:203611$14583_Y
- connect \$117 $and$libresoc.v:203612$14584_Y
- connect \$119 $lt$libresoc.v:203613$14585_Y
- connect \$121 $and$libresoc.v:203614$14586_Y
- connect \$123 $lt$libresoc.v:203615$14587_Y
- connect \$125 $and$libresoc.v:203616$14588_Y
- connect \$127 $lt$libresoc.v:203617$14589_Y
- connect \$12 $eq$libresoc.v:203618$14590_Y
- connect \$129 $and$libresoc.v:203619$14591_Y
- connect \$131 $lt$libresoc.v:203620$14592_Y
- connect \$133 $and$libresoc.v:203621$14593_Y
- connect \$135 $lt$libresoc.v:203622$14594_Y
- connect \$137 $and$libresoc.v:203623$14595_Y
- connect \$11 $ternary$libresoc.v:203624$14596_Y
- connect \$139 $lt$libresoc.v:203625$14597_Y
- connect \$141 $and$libresoc.v:203626$14598_Y
- connect \$143 $lt$libresoc.v:203627$14599_Y
- connect \$145 $and$libresoc.v:203628$14600_Y
- connect \$147 $lt$libresoc.v:203629$14601_Y
- connect \$149 $and$libresoc.v:203630$14602_Y
- connect \$151 $lt$libresoc.v:203631$14603_Y
- connect \$153 $and$libresoc.v:203632$14604_Y
- connect \$155 $lt$libresoc.v:203633$14605_Y
- connect \$157 $and$libresoc.v:203634$14606_Y
- connect \$159 $lt$libresoc.v:203635$14607_Y
- connect \$161 $and$libresoc.v:203636$14608_Y
- connect \$163 $lt$libresoc.v:203637$14609_Y
- connect \$165 $and$libresoc.v:203638$14610_Y
- connect \$167 $lt$libresoc.v:203639$14611_Y
- connect \$16 $eq$libresoc.v:203640$14612_Y
- connect \$169 $and$libresoc.v:203641$14613_Y
- connect \$171 $lt$libresoc.v:203642$14614_Y
- connect \$173 $and$libresoc.v:203643$14615_Y
- connect \$175 $lt$libresoc.v:203644$14616_Y
- connect \$177 $and$libresoc.v:203645$14617_Y
- connect \$15 $ternary$libresoc.v:203646$14618_Y
- connect \$179 $lt$libresoc.v:203647$14619_Y
- connect \$181 $and$libresoc.v:203648$14620_Y
- connect \$183 $lt$libresoc.v:203649$14621_Y
- connect \$185 $and$libresoc.v:203650$14622_Y
- connect \$187 $lt$libresoc.v:203651$14623_Y
- connect \$189 $and$libresoc.v:203652$14624_Y
- connect \$191 $lt$libresoc.v:203653$14625_Y
- connect \$193 $and$libresoc.v:203654$14626_Y
- connect \$195 $lt$libresoc.v:203655$14627_Y
- connect \$197 $and$libresoc.v:203656$14628_Y
- connect \$1 $eq$libresoc.v:203657$14629_Y
- connect \$199 $lt$libresoc.v:203658$14630_Y
- connect \$201 $and$libresoc.v:203659$14631_Y
- connect \$204 $eq$libresoc.v:203660$14632_Y
- connect \$203 $ternary$libresoc.v:203661$14633_Y
- connect \$20 $eq$libresoc.v:203662$14634_Y
- connect \$19 $ternary$libresoc.v:203663$14635_Y
- connect \$24 $eq$libresoc.v:203664$14636_Y
- connect \$23 $ternary$libresoc.v:203665$14637_Y
- connect \$28 $eq$libresoc.v:203666$14638_Y
- connect \$27 $ternary$libresoc.v:203667$14639_Y
- connect \$32 $eq$libresoc.v:203668$14640_Y
- connect \$31 $ternary$libresoc.v:203669$14641_Y
- connect \$36 $eq$libresoc.v:203670$14642_Y
- connect \$35 $ternary$libresoc.v:203671$14643_Y
- connect \$3 $eq$libresoc.v:203672$14644_Y
- connect \$40 $eq$libresoc.v:203673$14645_Y
- connect \$39 $ternary$libresoc.v:203674$14646_Y
- connect \$44 $eq$libresoc.v:203675$14647_Y
- connect \$43 $ternary$libresoc.v:203676$14648_Y
- connect \$48 $eq$libresoc.v:203677$14649_Y
- connect \$47 $ternary$libresoc.v:203678$14650_Y
- connect \$52 $eq$libresoc.v:203679$14651_Y
- connect \$51 $ternary$libresoc.v:203680$14652_Y
- connect \$56 $eq$libresoc.v:203681$14653_Y
- connect \$55 $ternary$libresoc.v:203682$14654_Y
- connect \$5 $and$libresoc.v:203683$14655_Y
- connect \$60 $eq$libresoc.v:203684$14656_Y
- connect \$59 $ternary$libresoc.v:203685$14657_Y
- connect \$64 $eq$libresoc.v:203686$14658_Y
- connect \$63 $ternary$libresoc.v:203687$14659_Y
- connect \$68 $eq$libresoc.v:203688$14660_Y
- connect \$67 $ternary$libresoc.v:203689$14661_Y
- connect \$71 $shr$libresoc.v:203690$14662_Y [0]
- connect \$73 $and$libresoc.v:203691$14663_Y
- connect \$75 $lt$libresoc.v:203692$14664_Y
- connect \$77 $and$libresoc.v:203693$14665_Y
- connect \$79 $lt$libresoc.v:203694$14666_Y
- connect \$81 $and$libresoc.v:203695$14667_Y
- connect \$83 $lt$libresoc.v:203696$14668_Y
- connect \$85 $and$libresoc.v:203697$14669_Y
- connect \$87 $lt$libresoc.v:203698$14670_Y
- connect \$8 $eq$libresoc.v:203699$14671_Y
- connect \$89 $and$libresoc.v:203700$14672_Y
- connect \$91 $lt$libresoc.v:203701$14673_Y
- connect \$93 $and$libresoc.v:203702$14674_Y
- connect \$95 $lt$libresoc.v:203703$14675_Y
- connect \$97 $and$libresoc.v:203704$14676_Y
+ assign $1\ics_wb__ack$next[0:0]$14613 1'0
+ case
+ assign $1\ics_wb__ack$next[0:0]$14613 \wb_valid
+ end
+ sync always
+ update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14612
+ end
+ connect \$7 $ternary$libresoc.v:203498$14366_Y
+ connect \$99 $lt$libresoc.v:203499$14367_Y
+ connect \$101 $and$libresoc.v:203500$14368_Y
+ connect \$103 $lt$libresoc.v:203501$14369_Y
+ connect \$105 $and$libresoc.v:203502$14370_Y
+ connect \$107 $lt$libresoc.v:203503$14371_Y
+ connect \$109 $and$libresoc.v:203504$14372_Y
+ connect \$111 $lt$libresoc.v:203505$14373_Y
+ connect \$113 $and$libresoc.v:203506$14374_Y
+ connect \$115 $lt$libresoc.v:203507$14375_Y
+ connect \$117 $and$libresoc.v:203508$14376_Y
+ connect \$119 $lt$libresoc.v:203509$14377_Y
+ connect \$121 $and$libresoc.v:203510$14378_Y
+ connect \$123 $lt$libresoc.v:203511$14379_Y
+ connect \$125 $and$libresoc.v:203512$14380_Y
+ connect \$127 $lt$libresoc.v:203513$14381_Y
+ connect \$12 $eq$libresoc.v:203514$14382_Y
+ connect \$129 $and$libresoc.v:203515$14383_Y
+ connect \$131 $lt$libresoc.v:203516$14384_Y
+ connect \$133 $and$libresoc.v:203517$14385_Y
+ connect \$135 $lt$libresoc.v:203518$14386_Y
+ connect \$137 $and$libresoc.v:203519$14387_Y
+ connect \$11 $ternary$libresoc.v:203520$14388_Y
+ connect \$139 $lt$libresoc.v:203521$14389_Y
+ connect \$141 $and$libresoc.v:203522$14390_Y
+ connect \$143 $lt$libresoc.v:203523$14391_Y
+ connect \$145 $and$libresoc.v:203524$14392_Y
+ connect \$147 $lt$libresoc.v:203525$14393_Y
+ connect \$149 $and$libresoc.v:203526$14394_Y
+ connect \$151 $lt$libresoc.v:203527$14395_Y
+ connect \$153 $and$libresoc.v:203528$14396_Y
+ connect \$155 $lt$libresoc.v:203529$14397_Y
+ connect \$157 $and$libresoc.v:203530$14398_Y
+ connect \$159 $lt$libresoc.v:203531$14399_Y
+ connect \$161 $and$libresoc.v:203532$14400_Y
+ connect \$163 $lt$libresoc.v:203533$14401_Y
+ connect \$165 $and$libresoc.v:203534$14402_Y
+ connect \$167 $lt$libresoc.v:203535$14403_Y
+ connect \$16 $eq$libresoc.v:203536$14404_Y
+ connect \$169 $and$libresoc.v:203537$14405_Y
+ connect \$171 $lt$libresoc.v:203538$14406_Y
+ connect \$173 $and$libresoc.v:203539$14407_Y
+ connect \$175 $lt$libresoc.v:203540$14408_Y
+ connect \$177 $and$libresoc.v:203541$14409_Y
+ connect \$15 $ternary$libresoc.v:203542$14410_Y
+ connect \$179 $lt$libresoc.v:203543$14411_Y
+ connect \$181 $and$libresoc.v:203544$14412_Y
+ connect \$183 $lt$libresoc.v:203545$14413_Y
+ connect \$185 $and$libresoc.v:203546$14414_Y
+ connect \$187 $lt$libresoc.v:203547$14415_Y
+ connect \$189 $and$libresoc.v:203548$14416_Y
+ connect \$191 $lt$libresoc.v:203549$14417_Y
+ connect \$193 $and$libresoc.v:203550$14418_Y
+ connect \$195 $lt$libresoc.v:203551$14419_Y
+ connect \$197 $and$libresoc.v:203552$14420_Y
+ connect \$1 $eq$libresoc.v:203553$14421_Y
+ connect \$199 $lt$libresoc.v:203554$14422_Y
+ connect \$201 $and$libresoc.v:203555$14423_Y
+ connect \$204 $eq$libresoc.v:203556$14424_Y
+ connect \$203 $ternary$libresoc.v:203557$14425_Y
+ connect \$20 $eq$libresoc.v:203558$14426_Y
+ connect \$19 $ternary$libresoc.v:203559$14427_Y
+ connect \$24 $eq$libresoc.v:203560$14428_Y
+ connect \$23 $ternary$libresoc.v:203561$14429_Y
+ connect \$28 $eq$libresoc.v:203562$14430_Y
+ connect \$27 $ternary$libresoc.v:203563$14431_Y
+ connect \$32 $eq$libresoc.v:203564$14432_Y
+ connect \$31 $ternary$libresoc.v:203565$14433_Y
+ connect \$36 $eq$libresoc.v:203566$14434_Y
+ connect \$35 $ternary$libresoc.v:203567$14435_Y
+ connect \$3 $eq$libresoc.v:203568$14436_Y
+ connect \$40 $eq$libresoc.v:203569$14437_Y
+ connect \$39 $ternary$libresoc.v:203570$14438_Y
+ connect \$44 $eq$libresoc.v:203571$14439_Y
+ connect \$43 $ternary$libresoc.v:203572$14440_Y
+ connect \$48 $eq$libresoc.v:203573$14441_Y
+ connect \$47 $ternary$libresoc.v:203574$14442_Y
+ connect \$52 $eq$libresoc.v:203575$14443_Y
+ connect \$51 $ternary$libresoc.v:203576$14444_Y
+ connect \$56 $eq$libresoc.v:203577$14445_Y
+ connect \$55 $ternary$libresoc.v:203578$14446_Y
+ connect \$5 $and$libresoc.v:203579$14447_Y
+ connect \$60 $eq$libresoc.v:203580$14448_Y
+ connect \$59 $ternary$libresoc.v:203581$14449_Y
+ connect \$64 $eq$libresoc.v:203582$14450_Y
+ connect \$63 $ternary$libresoc.v:203583$14451_Y
+ connect \$68 $eq$libresoc.v:203584$14452_Y
+ connect \$67 $ternary$libresoc.v:203585$14453_Y
+ connect \$71 $shr$libresoc.v:203586$14454_Y [0]
+ connect \$73 $and$libresoc.v:203587$14455_Y
+ connect \$75 $lt$libresoc.v:203588$14456_Y
+ connect \$77 $and$libresoc.v:203589$14457_Y
+ connect \$79 $lt$libresoc.v:203590$14458_Y
+ connect \$81 $and$libresoc.v:203591$14459_Y
+ connect \$83 $lt$libresoc.v:203592$14460_Y
+ connect \$85 $and$libresoc.v:203593$14461_Y
+ connect \$87 $lt$libresoc.v:203594$14462_Y
+ connect \$8 $eq$libresoc.v:203595$14463_Y
+ connect \$89 $and$libresoc.v:203596$14464_Y
+ connect \$91 $lt$libresoc.v:203597$14465_Y
+ connect \$93 $and$libresoc.v:203598$14466_Y
+ connect \$95 $lt$libresoc.v:203599$14467_Y
+ connect \$97 $and$libresoc.v:203600$14468_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff