use common TestCase in alu

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index c6acbae1028215b04b2ef9bb0125c005866a2253..3e843a0c7d585137b525e205634dae9b0cf42307 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -12,17 +12,11 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
+from soc.fu.test.common import TestCase
 from soc.fu.alu.pipeline import ALUBasePipe
 from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
-class TestCase:
-    def __init__(self, program, regs, sprs, name):
-        self.program = program
-        self.regs = regs
-        self.sprs = sprs
-        self.name = name
-
 
 def get_cu_inputs(dec2, sim):
     """naming (res) must conform to ALUFunctionUnit input regspec
@@ -109,8 +103,8 @@ class ALUTestCase(FHDLTestCase):
     def __init__(self, name):
         super().__init__(name)
         self.test_name = name
-    def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
-        tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
+    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         test_data.append(tc)
 
     def test_rand(self):