syntax error

diff --git a/libreriscv b/libreriscv
index d9407bb55d4da65bbecdbf51d472a76fe4a5ba16..d83e5ccbacd56e762bedc660cdd930264e12b81b 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit d9407bb55d4da65bbecdbf51d472a76fe4a5ba16
+Subproject commit d83e5ccbacd56e762bedc660cdd930264e12b81b

diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py
index c37f23a8f0c4d45144783da01e6d25699f4a0efe..d391eb700500ede61a3615b897230cfba3a4ecf5 100644 (file)
--- a/src/soc/litex/core.py
+++ b/src/soc/litex/core.py
@@ -86,8 +86,8 @@ class LibreSOC(CPU):
             o_ibus__cti   = self.ibus.cti,
             o_ibus__bte   = self.ibus.bte,
             o_ibus__we    = self.ibus.we,
-            #o_ibus__adr   = self.ibus.adr, # 64-bit
-            sigh o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
+            # sigh o_ibus__adr   = self.ibus.adr, # for 32-bit
+            o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
             o_ibus__dat_w = self.ibus.dat_w,
             o_ibus__sel   = self.ibus.sel,
             i_ibus__ack   = self.ibus.ack,