Allow the Simulator to handle back-to-back signaling from TestIssuer

TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index b6be2f3a20581a2482e9beb80490153bdd97230c..2cfd60ee956d8206604d6a2c4c6ea1db4fab5cea 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -259,12 +259,8 @@ class TestRunner(FHDLTestCase):
                     counter = counter + 1
 
                     # wait until executed
-                    # wait for insn_done high
                     while not (yield issuer.insn_done):
                         yield
-                    # wait for insn_done low
-                    while (yield issuer.insn_done):
-                        yield
 
                     # set up simulated instruction (in simdec2)
                     try:
@@ -289,9 +285,6 @@ class TestRunner(FHDLTestCase):
                         yield
                         yield
 
-                    # wait one cycle for registers to settle
-                    yield
-
                     # register check
                     yield from check_regs(self, sim, core, test, code)