attempting to access self.msr directly

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2833e6f385bdec03480147565ab73f637c6b3088..aea6d035b351f92c0115c7ebeff5a9f707130d7a 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -577,8 +577,9 @@ class ISACaller:
                       MicrOp.OP_MTSPR.value] and spr_msb:
             instr_is_privileged = True
 
+        print ("is priv", instr_is_privileged, self.msr[63-MSR.PR])
         # check MSR priv bit and whether op is privileged: if so, throw trap
-        if instr_is_privileged and self.namespace['MSR'][63-MSR.PR] == 1:
+        if instr_is_privileged and self.msr[63-MSR.PR] == 1:
             self.TRAP(0x700, PI.PRIV)
             return